DATASHEET HI1171. Ordering Information. Typical Application Circuit. Pinout. 8-Bit, 40 MSPS, High Speed D/A Converter. FN3662 Rev.3.

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1 -Bit, 40 MSPS, High Speed D/A Converter Pb-Free and RoHS Compliant DATASHEET FN366 Rev.3.00 Features Throughput Rate MHz Resolution Bit Integral Linearity Error LSB Low Glitch Noise Single Supply Operation V Low Power Consumption (Max) mW Evaluation Board Available (HI7-EV) Direct Replacement for the Sony CXD7 Applications Wireless Telecommunications Signal Reconstruction Direct Digital Synthesis Imaging Presentation and Broadcast Video Graphics Displays Signal Generators Description The HI7 is an -bit, 40MHz, high speed D/A converter. The converter incorporates an -bit input data register with blanking capability, and current outputs. The HI7 features low glitch outputs. The architecture is a current cell arrangement to provide low linearity errors. The HI7 is available in an Industrial temperature range and is offered in a 4 lead (00 mil) SOIC plastic package. For dual version, please refer to the HI77 Data Sheet. For triple version, please refer to the HI7 Data Sheet. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. HI7JCB -40 to 5 4 Ld SOIC M4.-S HI7-EV 5 Evaluation Board Pinout Typical Application Circuit HI7 (SOIC) TOP VIEW 4 DV DD +5V HI7 DV DD (3, 4) (,, ) +5V D D D DV DD I OUT D6 D5 (MSB)() D6 (7) D5 (6) (7) V G (6) k D4 5 0 I OUT D4 D4 (5) D5 D6 BLNK DV SS VG DV SS D3 D D D0 D3 (4) D (3) D () D0 (LSB) () () () BLNK () DV SS (0, 3) (0) I OUT (5) () I OUT (4) 00 D/A OUT FN366 Rev.3.00 Page of 7

2 Functional Block Diagram D D D3 D4 D5 DECODER -BIT LATCH 6 MSBs CURRENT CELLS LSBs CURRENT CELLS I OUT I OUT D6 DECODER VG (MSB) BLNK CURRENT CELLS (FOR FULL SCALE) - + VB BIAS VOLTAGE GENERATOR CLOCK GENERATOR FN366 Rev.3.00 Page of 7

3 Absolute Maximum Ratings Digital Supply Voltage DV DD to DV SS V Analog Supply Voltage to V Input Voltage V DD to V SS V Output Current mA to 5mA Operating Conditions Temperature Range o C to 5 o C Thermal Information Thermal Resistance (Typical, Note ) JA ( o C/W) SOIC Package Maximum Junction Temperature, Plastic Package o C Maximum Storage Temperature Range o C to 50 o C Maximum Lead Temperature (Soldering 0s) o C (SOIC - Lead Tips Only) CAUTN: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications = +4.75V to +5.5V, DV DD = to +5.5V, = +.0V, f S = 40MHz, Pulse Width =.5ns, T A = 5 o C (Note 4) PARAMETER TEST CONDITNS MIN TYP MAX UNITS SYSTEM PERFORMANCE Resolution, n - - Bits Integral Linearity Error, INL f S = 40MHz (End Point) LSB Differential Linearity Error, DNL f S = 40MHz LSB Offset Error, V OS (Note ) - - mv Full Scale Error, FSE (Adjustable to Zero) (Note ) LSB Full Scale Output Current, I FS ma Full Scale Output Voltage, V FS..0. V Output Voltage Range, V FSR V DYNAMIC CHARACTERISTICS Throughput Rate See Figure MHz Glitch Energy, GE R OUT = pv-s Differential Gain, A V (Note 3) -. - % Differential Phase, (Note 3) Degree REFERENCE INPUT Voltage Reference Input Range V Reference Input Resistance (Note 3) M DIGITAL INPUTS Input Logic High Voltage, V IH (Note 3) V Input Logic Low Voltage, V IL (Note 3) V Input Logic Current, I IL, I IH (Note 3) A Digital Input Capacitance, C IN (Note 3) pf TIMING CHARACTERISTICS Data Setup Time, t SU See Figure ns Data Hold Time, t HLD See Figure ns FN366 Rev.3.00 Page 3 of 7

4 Electrical Specifications = +4.75V to +5.5V, DV DD = to +5.5V, = +.0V, f S = 40MHz, Pulse Width =.5ns, T A = 5 o C (Note 4) (Continued) PARAMETER TEST CONDITNS MIN TYP MAX UNITS Propagation Delay Time, t PD See Figure ns Settling Time, t SET (to / LSB) See Figure ns Pulse Width, t PW, t PW See Figure ns POWER SUPPLY CHARACTERISITICS I 4.3MHz, at Color Bar Data Input ma IDV DD 4.3MHz, at Color Bar Data Input ma Power Dissipation 00 load at V P-P Output mw NOTES:. Excludes error due to external reference drift. 3. Parameter guaranteed by design or characterization and not production tested. 4. Electrical specifications guaranteed only under the stated operating conditions. Timing Diagram t PW t PW t SU t SU t SU t HLD t HLD t HLD DATA t PD 00% D/AOUT 50% t PD t PD 0% FIGURE. FN366 Rev.3.00 Page 4 of 7

5 Typical Performance Curves OUTPUT FULL SCALE VOLTAGE (V) GLITCH ENERGY (pv/s) V DD = 5.0V, R = 00 6R =, T A = 5 o C REFERENCE VOLTAGE (V) FIGURE. OUTPUT FULL SCALE VOLTAGE vs REFERENCE VOLTAGE OUTPUT RESISTANCE ( ) FIGURE 3. OUTPUT RESISTANCE vs GLITCH ENERGY OUTPUT FULL SCALE VOLTAGE (V).0. V DD = 5.0V, =.0V R = 00 6R = T A = 5 o C AMBIENT TEMPERATURE ( o C) FIGURE 4. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE Pin Descriptions 4 PIN SOIC PIN NAME PIN DESCRIPTN - D0(LSB) thru (MSB) Digital Data Bit 0, the Least Significant Bit thru Digital Data Bit 7, the Most Significant Bit. BLNK Blanking Line, used to clear the internal data register to the zero condition when High, normal operation when Low. 0, 3 DV SS Digital Ground. VB Voltage Bias, connect a capacitor to DV SS. Data Clock Pin 00kHz to 40MHz. 4 Analog Ground. 5 Current Reference, used to set the current range. Connect a resistor to that is 6 times greater than the resistor on I OUT. (See Typical Applications Circuit). 6 Input Reference Voltage used to set the output full scale range. 7 VG Voltage Ground, connect a capacitor to.,, Analog Supply 4.75V to 7V. 0 I OUT Current Output Pin. FN366 Rev.3.00 Page 5 of 7

6 Pin Descriptions (Continued) 4 PIN PIN SOIC NAME PIN DESCRIPTN I OUT Current Output pin used for a virtual ground connection. Usually connected to. 3, 4 DV DD Digital Supply 4.75V to 7V. Detailed Description The HI7 is an -bit, current out D/A converter. The DAC can convert at 40MHz and run on a single +5V supply. The architecture is an encoded, switched current cell arrangement. Voltage Output Mode The output current of the HI7 can be converted into a voltage by connecting an external resistor to I OUT. To calculate the output resistor use the following equation: R OUT = V FS /I FS, where V FS can range from +0.5V to +.0V and I FS can range from 0mA to 5mA. In setting the output current the pin should have a resistor connected to it that is 6 times greater than the output resistor: R REF = 6 x R OUT As the values of both R OUT and R REF increase, power consumption is decreased, but glitch energy and output settling time is increased. Clock Phase Relationship The internal latch is closed when the clock line is high. The latch can be cleared by the BLNK line. When BLNK is set (HIGH) the contents of the internal data latch will be cleared. When BLNK is low data is updated by the. Noise Reduction To reduce power supply noise separate analog and digital power supplies should be used with ceramic capacitors placed as close to the body of the HI7 as possible. The analog ( ) and digital (DV SS ) ground returns should be connected together back at the power supply to ensure proper operation from power up. Test Circuits -BIT COUNTER WITH LATCH 0 VG 7 00 OSCILLOSCOPE 40MHz VB 6 5 V k FIGURE 5. MAXIMUM CONVERSN SPEED TEST CIRCUIT Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO00 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN366 Rev.3.00 Page 6 of 7

7 Test Circuits (Continued) CONTROLLER 0 7 V G 00 DVM 40MHz 6 5 V k FIGURE 6. DC CHARACTERISTICS TEST CIRCUIT 0 OSCILLOSCOPE 7 V G 00 0MHz FREQUENCY DEMULTIPLIER 6 5 V k FIGURE 7. PROPAGATN DELAY TIME TEST CIRCUIT -BIT COUNTER WITH LATCH 0 7 V G 75 OSCILLOSCOPE MHz DELAY CONTROLLER DELAY CONTROLLER 6 5 V k.k FIGURE. SET UP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT FN366 Rev.3.00 Page 7 of 7