8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter AD9057

Transcription

1 a FEATURES -Bit, Low Power ADC: 2 mw Typical 2 MHz Analog Bandwidth On-Chip 2. V Reference and Track-and-Hold V p-p Analog Input Range Single V Supply Operation V or 3 V Logic Interface Power-Down Mode: < mw 3 Performance Grades ( MSPS, 6 MSPS, MSPS) APPLICATIONS Digital Communications (QAM Demodulators) RGB and YC/Composite Video Processing Digital Data Storage Read Channels Medical Imaging Digital Instrumentation -Bit MSPS/6 MSPS/ MSPS A/D Converter FUNCTIONAL BLOCK DIAGRAM BIAS OUT VREF IN VREF OUT PWRDN D T/H 2. k ADC ENCODE D7 D PRODUCT DESCRIPTION The is an -bit monolithic analog-to-digital converter optimized for low cost, low power, small size, and ease of use. With MSPS, 6 MSPS, or MSPS encode rate capability and full-power analog bandwidth of 2 MHz, the component is ideal for applications requiring excellent dynamic performance. To minimize system cost and power dissipation, the includes an internal 2. V reference and a track-and-hold (T/H) circuit. The user must provide only a V power supply and an encode clock. No external reference or driver components are required for many applications. The s encode input is TTL/CMOS compatible, and the -bit digital outputs can be operated from V or 3 V supplies. A power-down function may be exercised to bring total consumption to < mw. In power-down mode, the digital outputs are driven to a high impedance state. Fabricated on an advanced BiCMOS process, the is available in a space-saving 2-lead shrink small outline package (2-lead SSOP) and is specified over the industrial temperature range ( C to + C). Customers desiring multichannel digitization may consider the AD99, a dual -bit, 6 MSPS monolithic based on the ADC core. The AD99 is available in a 2-lead surface-mount plastic package (2-lead SSOP) and is specified over the industrial temperature range. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: 7/ Fax: 7/ Analog Devices, Inc. All rights reserved.

2 * PRODUCT PAGE QUICK LINKS Last Content Update: 2/23/27 COMPARABLE PARTS View a parametric search of comparable parts. DOCUMENTATION Application Notes AN-3: Avoiding Passive-Component Pitfalls AN-: Aperture Uncertainty and ADC System Performance AN-7: A First Approach to IBIS Models: What They Are and How They Are Generated AN-737: How ADIsimADC Models an ADC AN-7: Little Known Characteristics of Phase Noise AN-76: Sampled Systems and the Effects of Clock Phase Noise and Jitter Data Sheet : -Bit, /6/ MSPS A/D Converter Data Sheet TOOLS AND SIMULATIONS IBIS Models REFERENCE MATERIALS Technical Articles Correlating High-Speed ADC Performance to Multicarrier 3G Requirements DNL and Some of its Effects on Converter Performance MS-22: Designing Power Supplies for High Speed ADC DESIGN RESOURCES Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints DISCUSSIONS View all EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

3 SPECIFICATIONS ( = V, D = 3 V; external reference, unless otherwise noted.) Test BRS- BRS-6 BRS- Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Bits DC ACCURACY Differential Nonlinearity 2 C I LSB Full VI LSB Integral Nonlinearity 2 C I LSB Full VI LSB No Missing Codes Full VI Guaranteed Guaranteed Guaranteed Gain Error 2 C I % FS Full VI % FS Gain Tempco Full V ± 7 ± 7 ± 7 ppm/ C ANALOG INPUT Input Voltage Range (Centered at 2. V) 2 C V... V p-p Input Offset Voltage 2 C I mv Full VI mv Input Resistance 2 C V kw Input Capacitance 2 C V pf Input Bias Current 2 C I ma Full VI ma Analog Bandwidth 2 C V MHz BAND GAP REFERENCE Output Voltage Full VI V Temperature Coefficient Full V ± ± ± ppm/ C SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 6 MSPS Minimum Conversion Rate Full IV MSPS Aperture Delay (t A ) 2 C V ns Aperture Uncertainty (Jitter) 2 C V ps rms Output Valid Time (t V ) 2 Full IV ns Output Propagation Delay (t PD ) 2 Full IV ns DYNAMIC PERFORMANCE 3 Transient Response 2 C V ns Overvoltage Recovery Time 2 C V ns Signal-to-Noise Ratio (SINAD) (With Harmonics) f IN =.3 MHz 2 C I f IN = 76 MHz 2 C V Effective Number of Bits (ENOB) f IN =.3 MHz 2 C I Bits f IN = 76 MHz 2 C V Bits Signal-to-Noise Ratio (SNR) (Without Harmonics) f IN =.3 MHz 2 C I f IN = 76 MHz 2 C V. Second Harmonic Distortion f IN =.3 MHz 2 C I c f IN = 76 MHz 2 C V c Third Harmonic Distortion f IN =.3 MHz 2 C I c f IN = 76 MHz 2 C V c Two Tone Intermodulation Distortion (IMD) 2 C V c Differential Phase 2 C V... Degrees Differential Gain 2 C V... % DIGITAL INPUTS Logic Voltage Full VI V Logic Voltage Full VI... V Logic Current Full VI ± ± ± ma Logic Current Full VI ± ± ± ma Input Capacitance 2 C V... pf Encode Pulsewidth High (t EH ) 2 C IV ns Encode Pulsewidth Low (t EL ) 2 C IV ns 2

4 Test BRS- BRS-6 BRS- Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit DIGITAL OUTPUTS Logic Voltage (D = 3 V) Full VI V Logic Voltage (D = V) Full IV V Logic Voltage Full VI... V Output Coding Offset Binary Code Offset Binary Code Offset Binary Code POWER SUPPLY Supply Current ( = V) Full VI 36 3 ma D Supply Current (D = 3 V) Full VI ma Power Dissipation, 6 Full VI mw Power-Down Dissipation Full VI mw Power Supply Rejection Ratio (PSRR) 2 C V mv/v NOTES Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2. V external reference). 2 t V and t PD are measured from the. V level of the encode to the %/9% levels of the digital output swing. The digital output load during test is not to exceed an ac load of pf or a dc current of ± ma. 3 SNR/harmonics based on an analog input voltage of. FS referenced to a. V full-scale input range. Digital supply current based on D = 3 V output drive with < pf loading under dynamic test conditions. Power dissipation is based on specified encode and.3 MHz analog input dynamic test conditions ( = V ± %, D = 3 V ± %). 6 Typical thermal impedance for the RS style (SSOP) 2-lead package: q JC = 6 C/W, q CA = C/W, and q JA = 26 C/W. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS Test Level Description I % production tested. II % production tested at 2 C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI % production tested at 2 C; guaranteed by design and characterization testing for industrial temperature range. N N + 3 N + N + N + 2 N + t A ENCODE t EH t EL t V DIGITAL OUTPUTS N 3 N 2 N N N + N + 2 t PD t A t EH t EL t V t PD APERTURE DELAY PULSEWIDTH HIGH PULSEWIDTH LOW OUTPUT VALID TIME OUTPUT PROP DELAY MIN TYP MAX 2.7 ns 66 ns 66 ns. ns 6.6 ns 9. ns Figure. Timing Diagram 3

5 ABSOLUTE MAXIMUM RATINGS*, D V Analog Inputs V to +. V Digital Inputs V to D +. V VREF Input V to +. V Digital Output Current ma Operating Temperature C to +2 C Storage Temperature C to + C Maximum Junction Temperature C Maximum Case Temperature C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Temperature Model Range Package Option* BRS- C to + C RS-2 BRS-6 C to + C RS-2 BRS- C to + C RS-2 /PCB 2 C Evaluation Board *RS = Shrink Small Outline Package (SSOP). Table I. Digital Coding (VREF = 2. V) Analog Input Voltage Level Digital Output 3. V Positive Full Scale 2.2 V Midscale +/2 LSB 2.9 V Midscale /2 LSB 2. V Negative Full Scale PIN CONFIGURATION PWRDN 2 D (LSB) VREF OUT 2 9 D VREF IN 3 D2 TOP VIEW (Not to Scale) 7 D3 6 BIAS OUT 6 D 7 9 D 3 D 2 D6 ENCODE D7 (MSB) PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function PWRDN Power-Down Function Select; Logic High for Power-Down Mode (Digital Outputs Go to High Impedance State). 2 VREF OUT Internal Reference Output (2. V typ); Bypass with. mf to Ground. 3 VREF IN Reference Input for ADC (2. V typ, ± %)., 9, 6 Ground (Analog/Digital)., Analog V Power Supply. 6 BIAS OUT Bias Pin for AC Coupling ( kw to REF IN). 7 Analog Input for ADC. ENCODE Encode Clock for ADC (ADC Samples on Rising Edge of Encode)., 7 2 D7 D Digital Outputs of ADC. D Digital Output Power Supply; Nominally 3 V to V. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

6 Typical Performance Characteristics 2 ANALOG IN =.3MHz,.FS SINAD = 6. ENOB = 7.36 BITS SNR = =.FS 3 SECOND HARMONIC THIRD HARMONIC FREQUENCY (MHz) TPC. Spectral Plot 6 MSPS,.3 MHz ANALOG INPUT FREQUENCY (MHz) TPC. Harmonic Distortion vs. Frequency 2 3 ANALOG IN = 76MHz,.FS SINAD =.9 ENOB = 7.6 BITS SNR = F IN = 7.FS F2 IN = 7.FS 2F F2 = 2.c 2F2 F = 3.c FREQUENCY (MHz) TPC 2. Spectral Plot 6 MSPS, 76 MHz FREQUENCY (MHz) TPC. Two-Tone Intermodulation Distortion 6 SNR SNR =.FS SINAD =.3MHz,.FS SINAD ANALOG INPUT FREQUENCY (MHz) TPC 3. SINAD/SNR vs. Frequency ENCODE RATE (MSPS) TPC 6. SINAD/SNR vs. Encode Rate

7 D =.. 9. D = 3V mw 2 =.3MHz,.FS D = 3V t PD (ns) D = ENCODE RATE (MSPS) TPC 7. Power Dissipation vs. Encode Rate TEMPERATURE ( C) TPC. t PD vs. Temperature/Supply (D = 3 V/ V) =.3MHz,.FS SNR SINAD TEMPERATURE ( C) TPC. SINAD/SNR vs. Temperature =.3MHz, FS SINAD SNR ENCODE HIGH PULSEWIDTH (ns) TPC. SINAD/SNR vs. Encode Pulsewidth G ERROR (%) ADC G () =.FS TEMPERATURE ( C) TPC 9. ADC Gain vs. Temperature (with External 2. V Reference) ANALOG FREQUENCY (MHz) TPC 2. ADC Frequency Response 6

8 THEORY OF OPERATION The combines Analog Devices proprietary MagAmp gray code conversion circuitry with flash converter technology to provide a high performance, low cost ADC. The design architecture ensures low power, high speed, and -bit accuracy. A single-ended TTL/CMOS compatible ENCODE input controls ADC timing for sampling the analog input pin and strobing the digital outputs (D7 D). An internal voltage reference (VREF OUT) may be used to control ADC gain and offset or an external reference may be applied. The analog input signal is buffered at the input of the ADC and applied to a high speed track-and-hold. The track-and-hold circuit holds the analog input value during the conversion process (beginning with the rising edge of the encode command). The track-and-hold s output signal passes through the gray code and flash conversion stages to generate coarse and fine digital representations of the held analog input level. Decode logic combines the multistage data and aligns the -bit word for strobed outputs on the rising edge of the encode command. The MagAmp/Flash architecture of the results in three pipeline delays for the output data. USING THE Analog Inputs The provides a single-ended analog input impedance of kw. The input requires a dc bias current of 6 ma (typical) centered near 2. V (±%). The dc bias may be provided by the user or may be derived from the ADC s internal voltage reference. Figure 2 shows a low cost dc bias implementation allowing the user to capacitively couple ac signals directly into the ADC without additional active circuitry. For best dynamic performance, the VREF OUT pin should be decoupled to ground with a. mf capacitor (to minimize modulation of the reference voltage) and the bias resistor should be approximately kw. A kw bias resistor (± 2%) is included within the and may be used to reduce application board size and complexity. VIN (V p-p) VREF OUT VREF IN k BIAS OUT Figure 2. Capacitively Coupled Figure 3 shows typical connections for high performance dc biasing using the ADC s internal voltage reference. All components may be powered from a single V supply. In the example, analog input signals are referenced to ground. VIN (. TO +.) k k AD k k VREF OUT VREF IN Figure 3. DC-Coupled (Inverted VIN) Voltage Reference A stable and accurate 2. V voltage reference is built into the (VREF OUT). The reference output may be used to set the ADC gain/offset by connecting VREF OUT to VREF IN. The internal reference is capable of providing 3 ma of drive current (for dc biasing the analog input or other user circuitry). Some applications may require greater accuracy, improved temperature performance, or gain adjustments that cannot be obtained using the internal reference. An external voltage may be applied to the VREF IN with VREF OUT disconnected for gain adjustment of up to ±% (the VREF IN pin is internally tied directly to the ADC circuitry). ADC gain and offset will vary simultaneously with external reference adjustment with a : ratio (a 2% or mv adjustment to the 2. V reference varies ADC gain by 2% and ADC input range center offset by mv). Theoretical input voltage range versus reference input voltage may be calculated from the following equations: V RANGE (p-p) = VREF IN/2. V MIDSCALE = VREF IN V TOP-OF-RANGE = VREF IN + V RANGE /2 V BOTTOM-OF-RANGE = VREF IN V RANGE /2 Digital Logic ( V/3 V Systems) The digital inputs and outputs of the can easily be configured to interface directly with 3 V or V logic systems. The encode and power-down (PWRDN) inputs are CMOS stages with TTL thresholds of. V, making the inputs compatible with TTL, V CMOS, and 3 V CMOS logic families. As with all high speed data converters, the encode signal should be clean and jitter free to prevent degradation of ADC dynamic performance. The s digital outputs will also interface directly with or 3 V CMOS logic systems. The voltage supply pin (D ) for these CMOS stages is isolated from the analog voltage supply. By varying the voltage on this supply pin, the digital output high level will change for V or 3 V systems. Optimum SNR is obtained running the outputs at 3 V. Care should be taken to isolate the D supply voltage from the V analog supply to minimize digital noise coupling into the ADC. 7

9 The provides high impedance digital output operation when the ADC is driven into power-down mode (PWRDN, logic high). A 2 ns (minimum) power-down time should be provided before a high impedance characteristic is required at the outputs. A 2 ns power-up period should be provided to ensure accurate ADC output data after reactivation (valid output data is available three clock cycles after the 2 ns delay). Timing The is guaranteed to operate with conversion rates from MSPS to MSPS depending on grade. The ADC is designed to operate with an encode duty cycle of %, but performance is insensitive to moderate variations. Pulsewidth variations of up to ±% (allowing the encode signal to meet the minimum/ maximum high/low specifications) will cause no degradation in ADC performance (see Figure timing diagram). Power Dissipation The power dissipation of the is specified to reflect a typical application setup under the following conditions: analog input is. FS at.3 MHz, is V, D is 3 V, and digital outputs are loaded with 7 pf typical ( pf maximum). The actual dissipation will vary as these conditions are modified in user applications. TPC 7 shows typical power consumption for the versus ADC encode frequency and D supply voltage. A power-down function allows users to reduce power dissipation when ADC data is not required. A TTL/CMOS high signal (PWRDN) shuts down portions of the ADC and brings total power dissipation to less than mw. The internal band gap voltage reference remains active during power-down mode to minimize ADC reactivation time. If the power-down function is not desired, Pin should be tied to ground. APPLICATIONS The wide analog bandwidth of the makes it attractive for a variety of high performance receiver and encoder applications. Figure shows two ADCs in a typical low cost I and Q demodulator implementation for cable, satellite, or wireless LAN modem receivers. The excellent dynamic performance of the ADC at higher analog input frequencies and encode rates empowers users to employ direct IF sampling techniques (refer to TPC 2 spectral plot). IF sampling eliminates or simplifies analog mixer and filter stages to reduce total system cost and power. IF IN 9 VCO BPF BPF VCO Figure. I and Q Digital Receiver The high sampling rate and analog bandwidth of the are ideal for computer RGB video digitizer applications. With a full-power analog bandwidth of 2 the maximum sampling rate, the ADC provides sufficient pixel-to-pixel transient settling time to ensure accurate 6 MSPS video digitization. Figure shows a typical RGB video digitizer implementation for the. RED GREEN BLUE H-SYNC PLL PIXEL CLOCK Figure. RGB Video Encoder Evaluation Board The /PCB evaluation board provides an easy-to-use analog/digital interface for the -bit, 6 MSPS ADC. The board includes typical hardware configurations for a variety of high speed digitization evaluations. On-board components include the (in the 2-lead SSOP package), an optional analog input buffer amplifier, a digital output latch, board timing drivers, an analog reconstruction digital-to-analog converter, and configurable jumpers for ac coupling, dc coupling, and power-down function testing. The board is configured at shipment for dc coupling using the s internal voltage reference. For dc-coupled analog input applications, amplifier U2 is configured to operate as a unity gain inverter with adjustable offset for the analog input signal. For full-scale ADC drive, the analog input signal should be V p-p into W (R) referenced to ground ( V). The amplifier offsets the analog signal by +VREF (2. V typical) to center the voltage for proper ADC input drive. For dc-coupled operation, connect E to E2 (analog input to R2) and E to E2 (amplifier output to analog input of ) using the board jumper connectors. DC offset of the analog input signal can be modified by adjusting potentiometer R. For ac-coupled analog input applications, amplifier U2 is removed from the analog signal path. The analog signal is coupled into the input of the through capacitor C2. The ADC pulls analog input bias current from the VREF IN voltage through the kw resistor internal to the (BIAS OUT). The analog input signal to the board should be V p-p into W (R) for full-scale ADC drive. For ac-coupled operation, connect E to E3 (analog input A to C2 feedthrough capacitor) and E to E2 (C2 to the analog input and internal bias resistor) using the board jumper connectors. The on-board reference voltage may be used to drive the ADC or an external reference may be applied. To use the internal voltage reference, connect E6 to E (VREF OUT to VREF IN). To apply an external voltage reference, connect E to E (external reference from the REF banana jack to VREF IN). The external voltage reference should be 2. V ± %.

10 The power-down function of the can be done through a board jumper connection. Connect E7 to E9 ( V to PWRDN) for power-down operation. For normal operation, connect E to E9 (ground to PWRDN). The encode signal source should be TTL/CMOS compatible and capable of driving a W termination (R7). The digital outputs of the are buffered through latches on the evaluation board (U3) and are available for the user at connector Pins 3 to 37. Latch timing is derived from the ADC encode clock and a digital clocking signal is provided for the board user at connector Pins 2 and 2. An on-board reconstruction digital-to-analog converter is available for quick evaluations of ADC performance using an oscilloscope or spectrum analyzer. The DAC converts the ADC s digital outputs to an analog signal for examination at the DAC OUT connector. The DAC is clocked at the ADC encode frequency. The AD976 is a -bit/ MSPS single V supply DAC. The reconstruction signal facilitates quick system troubleshooting or confirmation of ADC functionality without requiring external digital memory, timing, or display interfaces. The DAC can be used for limited dynamic testing, but customers should note that test results will be based on the combined performance of the ADC and DAC (the best ADC performance will be recognized by evaluating the digital outputs of the ADC directly). ENCODE PWRDN V REF IN Digital Inputs Analog Input D, 3V TO D D7 V REF IN k BIAS OUT Digital Outputs Bias Output 3k V REF OUT V REF IN 2.k V REF Output V REF Input Figure 6. Equivalent Circuits 9

11 U 7AC 2 3 U 7AC 6 U 7AC 2 3 U 7AC 9 R7 PWRDN VREF OUT VREF IN BIAS OUT ENC (LSB) D D D2 D3 D D D D6 (MSB) D D D D2 D3 D D D D6 D7 E2 E E C2 R6 C E E E6 J6, REF PWRDN E7 E9 E R 2k R R 2k 7 6 DIS +V S NC NC V S U2 ADQ C7 R2 k E2 R BNC J ANALOG IN DB9 DB DB7 DB6 DB DB DB3 DB2 DB DB (LSB) (MSB) CLOCK DVDD AVDD COMP2 COMP FS ADJ REFIO REFLO SLEEP IOUT A B 2 DAC AD976AR DA7 DA6 DA DA DA3 DA2 DA DA 22 2 PWRDN C C9 R9 2k C3 R R BNC J C37DRPF P DA DA DA2 DA3 DA DA DA6 DA7 D 7D 6D D D 3D 2D D Q 7Q 6Q Q Q 3Q 2Q Q CK OE D7 D6 D D D3 D2 D D DA7 DA6 DA DA DA3 DA2 DA DA U3 7ACQ7 R3 k BNC J3 ENCODE ANALOG RECONSTRUCT DAC OUT C F C + J7, D D J, C C C7 C2 F C9 C C + C3 J, DECOUPLING CAPS 2 3 E E3 Figure 7. Evaluation Board Schematic

12 Figure. Evaluation Board Layout

13 OUTLINE DIMENSIONS 2-Lead Shrink Small Outline Package [SSOP] (RS-2) Dimensions shown in millimeters C6 /3(D) 2. MAX.6. MIN BSC COPLANARITY SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-AE.9.7. Revision History Location Page /3 Data Sheet changed from REV. C to. Change to SPECIFICATIONS Updated OUTLINE DIMENSIONS / Data Sheet changed from REV. B to REV. C. Edit to ABSOLUTE MAXIMUM RATINGS