10-/12-/14-Bit, 125 MSPS Dual TxDAC+ Digital-to-Analog Converters AD9763/AD9765/AD9767

Transcription

1 -/-/4-Bit, 5 MSPS Dual TxDAC+ Digital-to-Analog Converters FEATURES -/-/4-bit dual transmit digital-to-analog converters (DACs) 5 MSPS update rate Excellent SFDR to 5 MHz output: dbc Excellent gain and offset matching:.% Fully independent or single-resistor gain control Dual-port or interleaved data On-chip. V reference 5 V or 3.3 V operation Power dissipation: 3 5 V Power-down mode: 5 5 V 48-lead LQFP APPLICATIONS Communications Base stations Digital synthesis Quadrature modulation 3D ultrasound GENERAL DESCRIPTION The are dual-port, high speed, -channel, -/-/4-bit CMOS DACs. Each part integrates two high quality TxDAC+ cores, a voltage reference, and digital interface circuitry into a small 48-lead LQFP. The AD9763/ AD97/AD9767 offer exceptional ac and dc performance while supporting update rates of up to 5 MSPS. The have been optimized for processing I and Q data in communications applications. The digital interface consists of two double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent of one another. Separate clocks control the update rate of the DACs. A mode control pin allows the to interface to two separate data ports, or to a single interleaved high speed data port. In interleaving mode, the input data stream is demuxed into its original I and Q data and then latched. The I and Q data is then converted by the two DACs and updated at half the input data rate. The GAINCTRL pin allows two modes for setting the full-scale current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set independently using two external resistors, or IOUTFS for both DACs can be set by using a single external resistor. See the Gain Control Mode section for important date code information on this feature. PORT WRT/IQWRT WRT/IQSEL PORT FUNCTIONAL BLOCK DIAGRAM DVDD/ DVDD DCOM/ DCOM DIGITAL INTERFACE MODE AVDD LATCH AD9763/ AD97/ AD9767 LATCH Figure. ACOM CLK DAC REFERENCE BIAS GENERATOR DAC CLK/IQ RESET I OUTA I OUTB REFIO FSADJ FSADJ GAINCTRL SLEEP I OUTA I OUTB The DACs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and maximize dynamic accuracy. Each DAC provides differential current output, thus supporting single-ended or differential applications. Both DACs of the AD9763, AD97, or AD9767 can be simultaneously updated and can provide a nominal full-scale current of ma. The full-scale currents between each DAC are matched to within.%. The are manufactured on an advanced, low cost CMOS process. They operate from a single supply of 3.3 V to 5 V and consume 3 mw of power. PRODUCT HIGHLIGHTS. The are members of a pincompatible family of dual TxDACs providing 8-, -, -, and 4-bit resolution.. Dual -/-/4-Bit, 5 MSPS DACs. A pair of high performance DACs for each part is optimized for low distortion performance and provides flexible transmission of I and Q information. 3. Matching. Gain matching is typically.% of full scale, and offset error is better than.%. 4. Low Power. Complete CMOS dual DAC function operates on 3 mw from a 3.3 V to 5 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. On-Chip Voltage Reference. The each include a. V temperature-compensated band gap voltage reference. 6. Dual -/-/4-Bit Inputs. The each feature a flexible dual-port interface, allowing dual or interleaved input data. 67- Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagram... Product Highlights... Revision History... 3 Specifications... 5 DC Specifications... 5 Dynamic Specifications... 6 Digital Specifications... 7 Absolute Maximum Ratings... 8 Thermal Resistance... 8 ESD Caution... 8 Pin Configuration and Function Descriptions... 9 Typical Performance Characteristics... AD AD AD Terminology... Theory of Operation... Functional Description... Reference Operation... Gain Control Mode... Setting the Full-Scale Current... DAC Transfer Function... 3 Analog Outputs... 3 Digital Inputs... 4 DAC Timing... 4 Sleep Mode Operation... 6 Power Dissipation... 6 Applying the... 8 Output Configurations... 8 Differential Coupling Using a Transformer... 8 Differential Coupling Using an Op Amp... 8 Single-Ended, Unbuffered Voltage Output... 9 Single-Ended, Buffered Voltage Output Configuration... 9 Power and Grounding Considerations... 9 Applications... 3 VDSL Example Applications Using the AD97 and AD Quadrature Amplitude Modulation (QAM) Example Using the AD CDMA Evaluation Board General Description Schematics Evaluation Board Layout Outline Dimensions... 4 Ordering Guide... 4 Rev. E Page of 4

3 REVISION HISTORY Revision History: /8 Revision E: Initial Combined Version Revision History: AD9763 /8 Rev. D to Rev. E Combined with AD97 and AD9767 Data Sheets... Universal Changes to Figure... Changes to Applications Section... Changes to Timing Diagram Section...7 Added Figure 4 and Figure Changes to Table 6... Change to Typical Performance Characteristics Section Conditions Statement... Added Figure 3 to Figure Added Note to Figure Changes to Functional Description Section... Changes to Figure 59 and Figure... Changes to Gain Control Mode Section... Replaced Reference Control Amplifier Section with Setting the Full-Scale Current Section... Changes to DAC Transfer Section...3 Change to Analog Outputs Section...4 Changes to Dual-Port Mode Timing...4 Changes to Interleaved Mode Timing Section...5 Added Figure Change to Differential Coupling Using a Transformer Section...8 Changes to Power and Grounding Considerations Section...3 Added VDSL Example Applications Using the AD97 and AD9767 Section...3 Added Figure 79 to Figure Changes to Figure Changes to CDMA Section...33 Changes to Figure Caption...33 Changes to Figure Changes to Figure Changes to Ordering Guide...4 9/6 Rev. C to Rev. D Updated Format... Universal Renumbered Figures... Universal Changes to Specifications Section...3 Changes to Applications Section... Updated Outline Dimensions...3 Changes to Ordering Guide...3 / Rev. B to Rev. C Changes to Figure 9... / Rev. A to Rev. B /99 Rev. to Rev. A Revision History: AD97 /8 Rev. C to Rev. E Combined with AD9763 and AD9767 Data Sheets... Universal Changes to Figure... Changes to Applications Section... Changes to Timing Diagram Section...7 Change to Absolute Maximum Ratings...8 Added Figure 3 and Figure Changes to Table 6... Added Figure 6 to Figure... Added Figure 4 to Figure Added Note to Figure Changes to Functional Description Section... Changes to Reference Operation Section... Changes to Figure 59 and Figure... Changes to Gain Control Mode Section... Replaced Reference Control Amplifier Section with Setting the Full-Scale Current Section... Changes to DAC Transfer Section...3 Changes to Interleaved Mode Timing Section...5 Added Figure Changes to Power and Grounding Considerations Section...3 Added Figure and Figure Changes to Quadrature Amplitude Modulation (QAM) Example Using the AD9763 Section...3 Changes to Figure 83 and Figure Changes to CDMA Section...33 Changes to Figure Caption...33 Changes to Figure Changes to Figure Changes to Ordering Guide...4 9/6 Rev. B to Rev. C Updated Format... Universal Changes to Figure...5 Changes to Figure Changes to Functional Description Section... Changes to Figure 5 and Figure Changes to Figure 8 and Figure Changes to Power Dissipation Section...7 Changes to Power and Grounding Considerations Section...9 Changes to Figure Changes to Figure Changes to Evaluation Board Section...4 Changes to Figure Updated Outline Dimensions...3 Changes to Ordering Guide...3 / Rev. A to Rev. B /99 Rev. to Rev. A 8/99 Revision : Initial Version Rev. E Page 3 of 4

4 Revision History: AD9767 /8 Rev. C to Rev. E Combined with AD9763 and AD97 Data Sheets...Universal Changes to Figure... Changes to Features Section... Changes to Applications Section... Changes to Timing Diagram Section... 7 Change to Absolute Maximum Ratings... 8 Added Figure 3 and Figure Changes to Table 6... Added Figure 6 to Figure Added Note to Figure Changes to Functional Description Section... Changes to Reference Operation Section... Changes to Figure 59 and Figure... Changes to Gain Control Mode Section... Replaced Reference Control Amplifier Section with Setting the Full-Scale Current Section... Changes to DAC Transfer Section... 3 Changes to Dual-Port Mode Timing... 4 Changes to Interleaved Mode Timing Section... 5 Added Figure Change to Differential Coupling Using a Transformer Section...8 Changes to Power and Grounding Considerations Section...3 Added Figure 79 and Figure Added to Quadrature Amplitude Modulation (QAM) Example Using the AD9763 Section... 3 Added Figure 83 and Figure Changes to CDMA Section Changes to Figure Caption Changes to Figure Changes to Figure Changes to Ordering Guide... 4 /6 Rev. B to Rev. C Updated Format...Universal Changes to Figure...5 Changes to Figure Changes to Functional Description Section... Changes to Figure 5 and Figure Changes to Figure 8 and Figure Changes to Power Dissipation Section... 8 Changes to Figure Changes to Power and Grounding Considerations Section... 9 Changes to Figure Changes to Figure Updated Outline Dimensions... 8 Changes to Ordering Guide... 8 / Rev. A to Rev. B /99 Rev. to Rev. A 8/99 Revision : Initial Version Rev. E Page 4 of 4

5 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD = DVDD = 3.3 V or 5 V, IOUTFS = ma, unless otherwise noted. Table. AD9763 AD97 AD9767 Parameter Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 4 Bits DC ACCURACY Integral Linearity Error (INL) ±. + LSB TA = 5 C.5 ± ± LSB TMIN to TMAX LSB Differential Nonlinearity (DNL) LSB TA = 5 C.5 ± ± ±. +.5 LSB TMIN to TMAX LSB ANALOG OUTPUT Offset Error % of FSR Gain Error Without Internal Reference ±.5 + ±.5 + ±.5 + % of FSR Gain Error with Internal Reference 5 ± +5 5 ± +5 5 ± +5 % of FSR Gain Match.6 ± ± ±. +.6 % of FSR db Full-Scale Output Current ma Output Compliance Range V Output Resistance kω Output Capacitance pf REFERENCE OUTPUT Reference Voltage V Reference Output Current 3 na REFERENCE INPUT Input Compliance Range V Reference Input Resistance MΩ Small-Signal Bandwidth MHz TEMPERATURE COEFFICIENTS Offset Drift ppm of FSR/ C Gain Drift Without Internal Reference ±5 ±5 ±5 ppm of FSR/ C Gain Drift with Internal Reference ± ± ± ppm of FSR/ C Reference Voltage Drift ±5 ±5 ±5 ppm/ C POWER SUPPLY Supply Voltages AVDD V DVDD, DVDD V Analog Supply Current (IAVDD) ma Digital Supply Current (IDVDD) ma Digital Supply Current (IDVDD) ma Supply Current Sleep Mode (IAVDD) ma Power Dissipation 4 (5 V, IOUTFS = ma) mw Power Dissipation 5 (5 V, IOUTFS = ma) mw Power Dissipation 6 (5 V, IOUTFS = ma) mw Power Supply Rejection Ratio 7 AVDD % of FSR/V Power Supply Rejection Ratio 7 DVDD % of FSR/V OPERATING RANGE C Measured at IOUTA, driving a virtual ground. Nominal full-scale current, IOUTFS, is 3 times the IREF current. 3 An external buffer amplifier with input bias current < na should be used to drive any external load. 4 Measured at fclk = 5 MSPS and fout =. MHz. 5 Measured at fclk = MSPS and fout = MHz. 6 Measured as unbuffered voltage output with IOUTFS = ma and RLOAD = 5 Ω at IOUTA and IOUTB, B fclk = MSPS, and fout = 4 MHz. 7 ±% power supply variation. Rev. E Page 5 of 4

6 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD = DVDD = 3.3 V or 5 V, IOUTFS = ma, differential transformer-coupled output, 5 Ω doubly terminated, unless otherwise noted. Table. AD9763 AD97 AD9767 Parameter Min Typ Max Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate (fclk) MSPS Output Settling Time (tst) to.% ns Output Propagation Delay (tpd) ns Glitch Impulse pv-s Output Rise Time (% to 9%) ns Output Fall Time (9% to %) ns Output Noise (IOUTFS = ma) pa/ Hz Output Noise (IOUTFS = ma) pa/ Hz AC LINEARITY Spurious-Free Dynamic Range to Nyquist fclk = MSPS, fout =. MHz dbfs Output dbc 6 dbfs Output dbc dbfs Output dbc 8 dbfs Output 6 dbc fclk = MSPS, fout =. MHz dbc fclk = MSPS, fout =.5 MHz dbc fclk = MSPS, fout = 5. MHz dbc fclk = MSPS, fout = 4. MHz dbc fclk = MSPS, fout = 5 MHz dbc fclk = 5 MSPS, fout = 5 MHz dbc fclk = 5 MSPS, fout = 4 MHz dbc Spurious-Free Dynamic Range Within a Window fclk = MSPS, fout =. MHz; MHz Span dbc fclk = 5 MSPS, fout = 5. MHz; MHz Span dbc fclk = MSPS, fout = 5.3 MHz; MHz Span dbc fclk = 5 MSPS, fout = 5.4 MHz; MHz Span dbc Total Harmonic Distortion fclk = MSPS, fout =. MHz dbc fclk = 5 MSPS, fout =. MHz dbc fclk = 5 MSPS, fout = 4. MHz dbc fclk = 5 MSPS, fout =. MHz 7 dbc Multitone Power Ratio (Eight Tones at khz Spacing) fclk = MSPS, fout =. MHz to.99 MHz dbfs Output 76 dbc 6 dbfs Output dbc dbfs Output dbc 8 dbfs Output dbc Channel Isolation fclk = 5 MSPS, fout = MHz dbc fclk = 5 MSPS, fout = 4 MHz dbc Measured single-ended into 5 Ω load. Rev. E Page 6 of 4

7 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD = DVDD = 3.3 V or 5 V, IOUTFS = ma, unless otherwise noted. Table 3. Parameter Min Typ Max Unit DIGITAL INPUTS Logic DVDD = DVDD = 5 V V Logic DVDD = DVDD = 3.3 V. 3 V Logic DVDD = DVDD = 5 V.3 V Logic DVDD = DVDD = 3.3 V.9 V Logic Current + μa Logic Current + μa Input Capacitance 5 pf Input Setup Time (ts). ns Input Hold Time (th).5 ns Latch Pulse Width (tlpw, tcpw) 3.5 ns Timing Diagram See Table 3 and the DAC Timing section for more information about the timing specifications. t S t H DATA IN (WRT) (WRT/IQWRT) t LPW (CLK) (CLK/IQCLK) t CPW I OUTA OR I OUTB Figure. Timing Diagram for Dual and Interleaved Modes t PD 67- Rev. E Page 7 of 4

8 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter With Respect To Rating AVDD ACOM.3 V to +6.5 V DVDD, DVDD DCOM/DCOM.3 V to +6.5 V ACOM DCOM/DCOM.3 V to +.3 V AVDD DVDD/DVDD 6.5 V to +6.5 V MODE, CLK/IQCLK, CLK/IQRESET, WRT/IQWRT, WRT/IQSEL DCOM/DCOM.3 V to DVDD/ DVDD +.3 V Digital Inputs DCOM/DCOM.3 V to DVDD/ DVDD +.3 V IOUTA/IOUTA, ACOM. V to AVDD +.3 V IOUTB/IOUTB REFIO, FSADJ, ACOM.3 V to AVDD +.3 V FSADJ GAINCTRL, SLEEP ACOM.3 V to AVDD +.3 V Junction 5 C Temperature Storage C to +5 C Temperature Range Lead Temperature ( sec) 3 C THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type θja Unit 48-Lead LQFP 9 C/W ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. E Page 8 of 4

9 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS MODE AVDD I OUTA I OUTB FSADJ REFIO GAINCTRL FSADJ I OUTB I OUTA ACOM SLEEP DB9P (MSB) DB8P DB7P DB6P DB5P DB4P DB3P DBP DBP DBP (LSB) NC NC PIN AD9763 TOP VIEW (Not to Scale) 36 NC 35 NC 34 NC 33 NC 3 DBP (LSB) 3 DBP 3 DBP 9 DB3P 8 DB4P 7 DB5P 6 DB6P 5 DB7P NC = NO CONNECT NC NC DCOM DVDD WRT/IQWRT CLK/IQCLK CLK/IQRESET WRT/IQSEL DCOM DVDD DB9P (MSB) DB8P Figure 3. AD9763 Pin Configuration MODE AVDD I OUTA I OUTB FSADJ REFIO GAINCTRL FSADJ I OUTB I OUTA ACOM SLEEP MODE AVDD I OUTA I OUTB FSADJ REFIO GAINCTRL FSADJ I OUTB I OUTA ACOM SLEEP DB3P (MSB) DBP DBP DBP DB9P DB8P DB7P DB6P DB5P DB4P DB3P DBP PIN AD9767 TOP VIEW (Not to Scale) 36 DBP (LSB) 35 DBP 34 DBP 33 DB3P 3 DB4P 3 DB5P 3 DB6P 9 DB7P 8 DB8P 7 DB9P 6 DBP 5 DBP DBP DBP (LSB) DCOM DVDD WRT/IQWRT CLK/IQCLK CLK/IQRESET WRT/IQSEL DCOM DVDD DB3P (MSB) DBP Figure 5. AD9767 Pin Configuration DBP (MSB) DBP DB9P 3 PIN 36 NC 35 NC 34 DBP (LSB) DB8P 4 33 DBP DB7P DB6P DB5P DB4P AD97 TOP VIEW (Not to Scale) 3 DBP 3 DB3P 3 DB4P 9 DB5P DB3P 9 8 DB6P DBP 7 DB7P DBP 6 DB8P DBP (LSB) 5 DB9P NC = NO CONNECT NC NC DCOM DVDD WRT/IQWRT CLK/IQCLK CLK/IQRESET WRT/IQSEL DCOM DVDD DBP (MSB) DBP Figure 4. AD97 Pin Configuration 67-4 Rev. E Page 9 of 4

10 Table 6. Pin Function Descriptions Pin No. AD9763 AD97 AD9767 Mnemonic Description to to to 4 DBxP Data Bit Pins (Port ) to 4, 3, 4, N/A NC No Connect 33 to 36 35, 36 5, 5, 5, DCOM, DCOM Digital Common 6, 6, 6, DVDD, DVDD Digital Supply Voltage WRT/IQWRT Input Write Signal for PORT (IQWRT in Interleaving Mode) CLK/IQCLK Clock Input for DAC (IQCLK in Interleaving Mode) CLK/IQRESET Clock Input for DAC (IQRESET in Interleaving Mode) WRT/IQSEL Input Write Signal for PORT (IQSEL in Interleaving Mode) 3 to 3 3 to 34 3 to 36 DBxP Data Bit Pins (Port ) SLEEP Power-Down Control Input ACOM Analog Common 39, 4 39, 4 39, 4 IOUTA, IOUTB Port Differential DAC Current Outputs FSADJ Full-Scale Current Output Adjust for DAC GAINCTRL Master/Slave Resistor Control Mode REFIO Reference Input/Output FSADJ Full-Scale Current Output Adjust for DAC 45, 46 45, 46 45, 46 IOUTB, IOUTA Port Differential DAC Current Outputs AVDD Analog Supply Voltage MODE Mode Select ( = dual port, = interleaved) Rev. E Page of 4

11 TYPICAL PERFORMANCE CHARACTERISTICS AD9763 AVDD = 3.3 V or 5 V, DVDD = 3.3 V, IOUTFS = ma, 5 Ω doubly terminated load, differential output, TA = 5 C, SFDR up to Nyquist, unless otherwise noted. 9 dbfs f CLK = 5MSPS 6dBFS f CLK = 5MSPS dbfs f CLK = MSPS f CLK = 5MSPS 5 f OUT (MHz) f OUT (MHz) 67-9 Figure 6. SFDR vs. dbfs Figure 9. SFDR vs. MSPS dbfs dbfs 6dBFS dbfs 6dBFS dbfs f OUT (MHz) Figure 7. SFDR vs. 5 MSPS f OUT (MHz) Figure. SFDR vs. 5 MSPS 67- dbfs I OUTFS = ma dbfs 6dBFS I OUTFS = ma I OUTFS = 5mA f OUT (MHz) Figure 8. SFDR vs. 5 MSPS f OUT (MHz) Figure. SFDR vs. fout and MSPS and dbfs 67- Rev. E Page of 4

12 9kHz/MSPS.7MHz/5MSPS I OUTFS = ma 5.9MHz/MSPS.37MHz/5MSPS SINAD (dbc) I OUTFS = ma I OUTFS = 5mA A OUT (dbfs) Figure. Single-Tone SFDR vs. fout = fclk/ f CLK (MSPS) Figure 5. SINAD vs. fclk and fout = 5 MHz and dbfs MHz/5MSPS 5MHz/5MSPS..5 MHz/MSPS 3MHz/MSPS 5MHz/5MSPS INL (LSB) A OUT (dbfs) Figure 3. Single-Tone SFDR vs. fout = fclk/ CODE Figure 6. Typical INL MSPS MSPS.5. 5MSPS DNL (LSB) A OUT (dbfs) Figure 4. Dual-Tone SFDR vs. fout = fclk/ CODE Figure 7. Typical DNL 67-7 Rev. E Page of 4

13 f OUT = MHz f OUT = MHz f OUT = 5MHz f OUT = 4MHz SFDR (dbm) f OUT = MHz TEMPERATURE ( C) Figure 8. SFDR vs. fclk = 5 MSPS, dbfs FREQUENCY (MHz) Figure. Dual-Tone fclk = 5 MSPS OFFSET ERROR (%FS).3.3 OFFSET ERROR GAIN ERROR.5.5 GAIN ERROR (%FS) SFDR (dbm) TEMPERATURE ( C). Figure 9. Gain and Offset Error vs. fclk = 5 MSPS FREQUENCY (MHz) Figure. Four-Tone fclk = 5 MSPS SFDR (dbm) FREQUENCY (MHz) Figure. Single-Tone fclk = 5 MSPS 67- Rev. E Page 3 of 4

14 AD97 AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = ma, 5 Ω doubly terminated load, differential output, TA = 5 C, SFDR up to Nyquist, unless otherwise noted. 9 f CLK = 5MSPS f CLK = 5MSPS dbfs f CLK = 5MSPS dbfs 6dBFS f CLK = MSPS 5 f OUT (MHz) Figure 3. SFDR vs. dbfs f OUT (MHz) Figure 6. SFDR vs. MSPS dbfs dbfs 6dBFS dbfs 6dBFS dbfs f OUT (MHz) Figure 4. SFDR vs. 5 MSPS f OUT (MHz) Figure 7. SFDR vs. 5 MSPS dbfs I OUTFS = ma I OUTFS = ma 6dBFS dbfs I OUTFS = 5mA f OUT (MHz) Figure 5. SFDR vs. 5 MSPS f OUT (MHz) Figure 8. SFDR vs. fout and MSPS and dbfs 67-8 Rev. E Page 4 of 4

15 9.7MHz/5MSPS.9MHz/MSPS I OUTFS = ma I OUTFS = ma SINAD (dbc).37mhz/5msps I OUTFS = 5mA 5.9MHz/MSPS 5 5 A OUT (dbfs) Figure 9. Single-Tone SFDR vs. fout = fclk/ f CLK (MSPS) Figure 3. SINAD vs. fclk and fout = 5 MHz and dbfs MHz/5MSPS MHz/MSPS MHz/5MSPS MHz/MSPS INL (LSB)... 5MHz/5MSPS A OUT (dbfs) Figure 3. Single-Tone SFDR vs. fout = fclk/ CODE Figure 33. Typical INL MHz/3.36MHz@5MSPS.9MHz/.35MHz@7MSPS.5 6.MHz/7.5MHz@MSPS DNL (LSB) MHz/8.MHz@5MSPS A OUT (dbfs) Figure 3. Dual-Tone SFDR vs. fout = fclk/ CODE Figure 34. Typical DNL Rev. E Page 5 of 4

16 f OUT = MHz f OUT = MHz f OUT = 5MHz f OUT = 4MHz SFDR (dbm) f OUT = MHz TEMPERATURE ( C) Figure 35. SFDR vs. 5 MSPS, dbfs FREQUENCY (MHz) Figure 38. Dual-Tone fclk = 5 MSPS OFFSET ERROR (%FS).3.3 OFFSET ERROR GAIN ERROR.5.5 GAIN ERROR (%FS) SFDR (dbm) TEMPERATURE ( C) FREQUENCY (MHz) Figure 36. Gain and Offset Error vs. fclk = 5 MSPS Figure 39. Four-Tone fclk = 5 MSPS SFDR (dbm) FREQUENCY (MHz) Figure 37. Single-Tone fclk = 5 MSPS Rev. E Page 6 of 4

17 AD9767 AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = ma, 5 Ω doubly terminated load, differential output, TA = 5 C, SFDR up to Nyquist, unless otherwise noted. 9 f CLK = 5MSPS f CLK = 5MSPS dbfs f CLK = 5MSPS 6dBFS dbfs f CLK = MSPS 5 f OUT (MHz) Figure 4. SFDR vs. dbfs f OUT (MHz) Figure 43. SFDR vs. MSPS dbfs dbfs dbfs 6dBFS dbfs 6dBFS f OUT (MHz) Figure 4. SFDR vs. 5 MSPS f OUT (MHz) Figure 44. SFDR vs. 5 MSPS dbfs I OUTFS = 5mA dbfs I OUTFS = ma 6dBFS I OUTFS = ma f OUT (MHz) Figure 4. SFDR vs. 5 MSPS f OUT (MHz) Figure 45. SFDR vs. fout and MSPS and dbfs Rev. E Page 7 of 4

18 9 9kHz/MSPS.7MHz/5MSPS I OUTFS = ma SINAD (dbc) I OUTFS = ma I OUTFS = 5mA 5.9MHz/MSPS.37MHz/5MSPS 5 5 A OUT (dbfs) Figure 46. Single-Tone SFDR vs. fout = fclk/ f CLK (MSPS) Figure 49. SINAD vs. fclk and fout = 5 MHz and dbfs MHz/MSPS MHz/5MSPS MHz/5MSPS INL (LSB)..5 3MHz/MSPS 5MHz/5MSPS A OUT (dbfs) Figure 47. Single-Tone SFDR vs. fout = fclk/ CODE Figure 5. Typical INL MHz/.35MHz@7MSPS 3.38MHz/3.63MHz@5MSPS.4.. DNL (LSB) MHz/8.MHz@5MSPS 6.MHz/7.5MHz@MSPS A OUT (dbfs) Figure 48. Dual-Tone SFDR vs. fout = fclk/ CODE Figure 5. Typical DNL 67-5 Rev. E Page 8 of 4

19 f OUT = MHz f OUT = MHz f OUT = 5MHz f OUT = 4MHz SFDR (dbm) f OUT = MHz TEMPERATURE ( C) Figure 5. SFDR vs. 5 MSPS, dbfs FREQUENCY (MHz) Figure. Dual-Tone fclk = 5 MSPS OFFSET ERROR (%FS).3.3 OFFSET ERROR GAIN ERROR.5.5 GAIN ERROR (%FS) SFDR (dbm) TEMPERATURE ( C) Figure 53. Gain and Offset Error vs. fclk = 5 MSPS FREQUENCY (MHz) Figure 56. Four-Tone fclk = 5 MSPS SFDR (dbm) FREQUENCY (MHz) Figure 54. Single-Tone fclk = 5 MSPS Rev. E Page 9 of 4

20 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error Offset error is the deviation of the output current from the ideal of zero. For IOUTA, ma output is expected when the inputs are all s. For IOUTB, B ma output is expected when all inputs are set to s. Gain Error Gain error is the difference between the actual and ideal output spans. The actual span is determined by the output when all inputs are set to s minus the output when all inputs are set to s. Output Compliance Range The output compliance range is the range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (5 C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in part per million (ppm) of full-scale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius (ppm/ C). Power Supply Rejection (PSR) PSR is the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Settling Time Settling time is the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in picovolts per second (pv-s). Spurious-Free Dynamic Range (SFDR) The difference, in decibels (db), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (db). Rev. E Page of 4

21 B THEORY OF OPERATION 5V CLK/IQCLK CLK/IQRESET SLEEP R SET kω.µf R SET kω FSADJ REFIO FSADJ.V REF GAINCTRL AVDD PMOS CURRENT SOURCE ARRAY PMOS CURRENT SOURCE ARRAY WRT/ IQWRT AD9763/ AD97/ AD9767 CLK DIVIDER DAC LATCH CHANNEL LATCH DAC LATCH MULTIPLEXING LOGIC SEGMENTED SWITCHES FOR DAC SEGMENTED SWITCHES FOR DAC CHANNEL LATCH LSB SWITCH LSB SWITCH I OUTA I OUTB I OUTA I OUTB MODE DVDD/ DVDD DCOM/ DCOM ACOM 5Ω 5V Mini-Circuits T-T 5Ω TO HP3589A OR EQUIVALENT SPECTRUM/ NETWORK ANALYZER DVDD/DVDD DCOM/DCOM RETIMED CLOCK OUTPUT* LECROY 9 PULSE GENERATOR 5Ω PORT PORT DIGITAL DATA TEKTRONIX AWG w/option 4 WRT/ IQSEL *AWG CLOCK RETIMED SUCH THAT DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 5% DUTY CYCLE CLOCK. Figure 57. Basic AC Characterization Test Setup for, Testing Port in Dual-Port Mode, Using Independent GAINCTRL Resistors on FSADJ and FSADJ V CLK/IQCLK CLK/IQRESET I REF I REF R SET kω.µf R SET kω FSADJ REFIO FSADJ.V REF GAINCTRL AVDD PMOS CURRENT SOURCE ARRAY PMOS CURRENT SOURCE ARRAY AD9763/ AD97/ AD9767 CLK DIVIDER DAC LATCH CHANNEL LATCH DAC LATCH MULTIPLEXING LOGIC SEGMENTED SWITCHES FOR DAC SEGMENTED SWITCHES FOR DAC CHANNEL LATCH SLEEP ACOM LSB SWITCH LSB SWITCH DCOM/ DCOM I OUTA I OUTB I OUTA I OUTB MODE DVDD/ DVDD V OUT B 5V V DIFF = V OUT A V OUT B R L B 5Ω V OUT A R L A 5Ω V OUT B R L B 5Ω V OUT A R L A 5Ω WRT/ IQWRT PORT PORT DIGITAL DATA INPUTS WRT/ IQSEL NOTES. IN THIS CONFIGURATION, THE nf CAPACITOR AND 56Ω RESISTOR ARE NOT REQUIRED BECAUSE R SET = kω. Figure 58. Simplified Block Diagram FUNCTIONAL DESCRIPTION All of these current sources are switched to one of the two Figure 58 shows a simplified block diagram of the AD9763/ output nodes (that is, IOUTA or IOUTB) via the PMOS differential AD97/AD9767. The consist of current switches. The switches are based on a new architecture two DACs, each one with its own independent digital control that drastically improves distortion performance. This new logic and full-scale output current control. Each DAC contains switch architecture reduces various timing errors and provides a PMOS current source array capable of providing up to ma matching complementary drive signals to the inputs of the of full-scale current (IOUTFS). differential current switches. The array is divided into 3 equal currents that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 5 equal current sources whose value is /6th of an MSB current source. The remaining LSB is a binary weighted fraction of the middle bit current sources. Implementing the middle and lower bits with current sources, instead of an R-R ladder, enhances the dynamic performance for multitone or low amplitude signals and helps maintain the high output impedance of each DAC (that is, > kω). Rev. E Page of 4 The analog and digital sections of the have separate power supply inputs (that is, AVDD and DVDD/ DVDD) that can operate independently at 3.3 V or 5 V. The digital section, which is capable of operating up to a 5 MSPS clock rate, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a. V band gap voltage reference, and two reference control amplifiers.

22 The full-scale output current of each DAC is regulated by separate reference control amplifiers and can be set from ma to ma via an external network connected to the full scale adjust (FSADJ) pin. The external network, in combination with both the reference control amplifier and voltage reference (VREFIO) sets the reference current IREF, which is replicated to the segmented current sources with the proper scaling factor. The full-scale current (IOUTFS) is 3 IREF. REFERENCE OPERATION The contain an internal. V band gap reference. This can easily be overridden by a low noise external reference with no effect on performance. REFIO serves as either an input or output, depending on whether the internal or an external reference is used. To use the internal reference, simply decouple the REFIO pin to ACOM with a. μf capacitor. The internal reference voltage is present at REFIO. If the voltage at REFIO is used elsewhere in the circuit, an external buffer amplifier with an input bias current of less than na should be used. An example of the use of the internal reference is shown in Figure 59. ADDITIONAL EXTERNAL LOAD OPTIONAL EXTERNAL REFERENCE BUFFER.µF I REF R SET 56Ω nf GAINCTRL.V REF REFIO FSADJ/ FSADJ AD9763/ AD97/ AD9767 REFERENCE SECTION Figure 59. Internal Reference Configuration AVDD CURRENT SOURCE ARRAY ACOM An external reference can be applied to REFIO as shown in Figure. The external reference can provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. The. μf compensation capacitor is not required because the internal reference is overridden and the relatively high input impedance of REFIO minimizes any loading of the external reference. AVDD EXTERNAL REFERENCE I REF R SET 56Ω nf GAINCTRL.V REF REFIO FSADJ/ FSADJ AD9763/ AD97/ AD9767 REFERENCE SECTION AVDD CURRENT SOURCE ARRAY ACOM Figure. External Reference Configuration Gain Control Mode GAIN CONTROL MODE The allow the gain of each channel to be set independently by connecting one RSET resistor network to FSADJ and another RSET resistor network to FSADJ. To add flexibility and reduce system cost, a single RSET resistor can be used to set the gain of both channels simultaneously. If this RSET resistor is kω or less, the nf capacitor and 56 Ω resistor are not required on either FSADJ pin. When GAINCTRL is low (that is, connected to analog ground), the independent channel gain control mode using two resistors is enabled. In this mode, individual RSET resistor networks must be connected to FSADJ and FSADJ. When GAINCTRL is high (that is, connected to AVDD), the master/slave channel gain control mode using one network is enabled. In this mode, a single network is connected to FSADJ, and the FSADJ pin must be left unconnected. Note that only parts with a date code of 993 or later have the master/slave gain control function. For parts with a date code before 993, Pin 4 must be connected to AGND, and the part operates in the two-resistor, independent gain control mode. SETTING THE FULL-SCALE CURRENT Both of the DACs in the contain a control amplifier that is used to regulate the full-scale output current (IOUTFS). The control amplifier is configured as a V-I converter, as shown in Figure 59, so that its current output (IREF) is determined by the ratio of the VREFIO and an external resistor, RSET. VREFIO I REF = R SET The DAC full-scale current, IOUTFS, is an output current 3 times larger than the reference current, IREF. I OUTFS = 3 I REF The control amplifier allows a wide (:) adjustment span of IOUTFS from ma to ma by setting IREF between 6.5 μa and μa. The wide adjustment range of IOUTFS provides several benefits. The first relates directly to the power dissipation of the, which is proportional to IOUTFS (refer to the Power Dissipation section). The second relates to the db adjustment, which is useful for system gain control purposes. It should be noted that when the RSET resistors are kω or less, the nf capacitor and 56 Ω resistor shown in Figure 59 and Figure are not required and the reference current can be set by the RSET resistors alone. For RSET values greater than kω, the nf capacitor and 56 Ω resistor networks are required to ensure the stability of the reference control amplifier(s). Regardless of the value of RSET, however, if the RSET resistor is located more than ~ cm away from the pin, use of the nf capacitor and 56 Ω resistor is recommended. Rev. E Page of 4

23 B can at B B B DAC TRANSFER FUNCTION Both DACs in the provide complementary current outputs, IOUTA and IOUTB. B IOUTA provides a near full-scale current output (IOUTFS) when all bits are high (that is, DAC CODE = 4/495/6,384 for the AD9763/AD97/ AD9767, respectively), while IOUT B, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB B is a function of both the input code and IOUTFS. IOUTA for the AD9763, AD97, and AD9767, respectively, can be expressed as IOUTA = (DAC CODE/4) IOUTFS () IOUTA = (DAC CODE/496) IOUTFS IOUTA = (DAC CODE/6,384) IOUTFS IOUTB B for the AD9763, AD97, and AD9767, respectively, can be expressed as IOUTB = (3 DAC CODE/4) IOUTFS () IOUTB = (3 DAC CODE/496) IOUTFS IOUTB = (3 DAC CODE/6,384) IOUTFS where DAC CODE = to 4, to 495, or to 6,384 (decimal representation). IOUTFS is a function of the reference current (IREF). This is nominally set by a reference voltage (VREFIO) and an external resistor (RSET). It can be expressed as IOUTFS = 3 IREF (3) where IREF is set as discussed in the Setting the Full-Scale Current section. The two current outputs typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads (RLOAD) that are tied to the analog common (ACOM). Note that RLOAD can represent the equivalent load resistance seen by IOUTA or IOUTB, as is the case in a doubly terminated 5 Ω or Ω cable. The singleended voltage output appearing at the IOUTA and IOUTB B nodes is VOUTA = IOUTA RLOAD (5) VOUTB = IOUTB RLOAD (6) Note that the full-scale value of VOUTA and VOUTB must not exceed the specified output compliance range to maintain the specified distortion and linearity performance. VDIFF = (IOUTA IOUTB) RLOAD (7) Equation 7 highlights some of the advantages of operating the differentially. First, the differential operation helps cancel common-mode error sources associated with IOUTA and IOUTB such as noise, distortion, and dc offsets. Second, the differential code-dependent current and subsequent voltage, VDIFF, is twice the value of the single-ended voltage output (that is, VOUTA or VOUT B), thus providing twice the signal power to the load. The gain drift temperature performance for a single-ended (VOUTA and VOUTB) B or differential output (VDIFF) of the can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship. ANALOG OUTPUTS The complementary current outputs, IOUTA and IOUTB, in each DAC can be configured for single-ended or differential operation. IOUTA and IOUT B be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor (RLOAD) as described in Equation 5 through Equation 7. The differential voltage (VDIFF) existing between VOUTA and VOUTB can be converted to a single-ended voltage via a transformer or differential amplifier configuration. The ac performance of the is optimum and specified using a differential transformer-coupled output in which the voltage swing at IOUTA and IOUTB B is limited to ±.5 V. If a single-ended unipolar output is desired, select IOUTA. The distortion and noise performance of the AD9763/AD97/ AD9767 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases. This is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load, assuming no source termination. Because the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. A properly selected transformer allows the to provide the required power and voltage levels to different loads. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically kω in parallel with 5 pf. It is also slightly dependent on the output voltage (that is, VOUTA and VOUTB) due to the nature of a PMOS device. As a result, maintaining IOUTA and/or IOUT B a virtual ground via an I-V op amp configuration results in the optimum dc linearity. Note that the INL/DNL specifications for the are measured with IOUTA maintained at a virtual ground via an op amp. Rev. E Page 3 of 4

24 B IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of. V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the. The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. When IOUTFS is decreased from ma to ma, the positive output compliance range degrades slightly from its nominal.5 V to. V. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed.5 V. Applications requiring the AD9763/ AD97/AD9767 output (that is, VOUTA and/or VOUTB) to extend its output compliance range must size RLOAD accordingly. Operation beyond this compliance range adversely affects the linearity performance of the and subsequently degrades its distortion performance. DIGITAL INPUTS The digital inputs of the consist of two independent channels. For the dual-port mode, each DAC has its own dedicated -/-/4-bit data port: WRT line and CLK line. In the interleaved timing mode, the function of the digital control pins changes as described in the Interleaved Mode Timing section. The -/-/4-bit parallel data inputs follow straight binary coding, where the most significant bits (MSBs) are DB9P and DB9P for the AD9763, DBP and DBP for the AD97, and DB3P and DB3P for the AD9767, and the least significant bits (LSBs) are DBP and DBP for all three parts. IOUTA produces a full-scale output current when all data bits are at Logic. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of the input code. The digital interface is implemented using an edge-triggered master/slave latch. The DAC outputs are updated following either the rising edge or every other rising edge of the clock, depending on whether dual or interleaved mode is used. The DAC outputs are designed to support a clock rate as high as 5 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulse width. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge of a 5% duty cycle clock. DAC TIMING The can operate in two timing modes, dual and interleaved, which are described in the following sections. The block diagram in Figure 6 represents the latch architecture in the interleaved timing mode. INTERLEAVED DATA IN, PORT IQWRT IQSEL PORT INPUT LATCH PORT INPUT LATCH DAC LATCH DAC LATCH DAC IQCLK IQRESET DAC Figure 6. Latch Structure in Interleaved Mode DEINTERLEAVED DATA OUT Dual-Port Mode Timing When the MODE pin is at Logic, the operates in dual-port mode (refer to Figure 57). The AD9763/ AD97/AD9767 functions as two distinct DACs. Each DAC has its own completely independent digital input and control lines. The features a double-buffered data path. Data enters the device through the channel input latches. This data is then transferred to the DAC latch in each signal path. After the data is loaded into the DAC latch, the analog output settles to its new value. For general consideration, the WRT lines control the channel input latches, and the CLK lines control the DAC latches. Both sets of latches are updated on the rising edge of their respective control signals. The rising edge of CLK must occur before or simultaneously with the rising edge of WRT. If the rising edge of CLK occurs after the rising edge of WRT, a minimum delay of ns must be maintained from the rising edge of WRT to the rising edge of CLK. Timing specifications for dual-port mode are shown in Figure 6 and Figure 63. DATA IN WRT/WRT CLK/CLK I OUTA OR I OUTB DATA IN WRT/WRT CLK/CLK I OUTA OR I OUTB t S t PD t H Figure 6. Dual-Port Mode Timing t LPW t CPW D D D3 D4 D5 XX D D Figure 63. Dual-Port Mode Timing D3 D Rev. E Page 4 of 4

25 Interleaved Mode Timing When the MODE pin is at Logic, the operate in interleaved mode (refer to Figure 6). In addition, WRT functions as IQWRT, CLK functions as IQCLK, WRT functions as IQSEL, and CLK functions as IQRESET. Data enters the device on the rising edge of IQWRT. The logic level of IQSEL steers the data to either Channel Latch (IQSEL = ) or to Channel Latch (IQSEL = ). For proper operation, IQSEL must change state only when IQWRT and IQCLK are low. When IQRESET is high, IQCLK is disabled. When IQRESET goes low, the next rising edge on IQCLK updates both DAC latches with the data present at their inputs. In the interleaved mode, IQCLK is divided by internally. Following this first rising edge, the DAC latches are only updated on every other rising edge of IQCLK. In this way, IQRESET can be used to synchronize the routing of the data to the DACs. Similar to the order of CLK and WRT in dual-port mode, IQCLK must occur before or simultaneously with IQWRT. Timing specifications for interleaved mode are shown in Figure 64 and Figure 66. The digital inputs are CMOS compatible with logic thresholds, VTHRESHOLD, set to approximately half the digital positive supply (DVDDx), or VTHRESHOLD = DVDDx/(±%) t S t H DATA IN IQSEL IQWRT IQCLK I OUTA OR I OUTB *APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY. Figure. 5 V Only Interleaved Mode Timing INTERLEAVED DATA IQSEL IQWRT IQCLK IQRESET t H * t S t PD t H t LPW xx D D D3 D4 D5 67- DATA IN IQSEL IQWRT IQCLK I OUTA OR I OUTB t H * 5 ps 5 ps *APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY. Figure V or 3.3 V Interleaved Mode Timing t PD t LPW At 5 V it is permissible to drive IQWRT and IQCLK together as shown in Figure, but at 3.3 V the interleaved data transfer is not reliable DAC OUTPUT PORT DAC OUTPUT PORT xx xx D D Figure 66. Interleaved Mode Timing The internal digital circuitry of the is capable of operating at a digital supply of 3.3 V or 5 V. As a result, the digital inputs can also accommodate TTL levels when DVDD/DVDD is set to accommodate the maximum high level voltage (VOH(MAX)) of the TTL drivers. A DVDD/DVDD of 3.3 V typically ensures proper compatibility with bipolar TTL logic families. Figure 67 shows the equivalent digital input circuit for the data and clock inputs. The sleep mode input is similar, with the exception that it contains an active pull-down circuit, thus ensuring that the remains enabled if this input is left disconnected. DIGITAL INPUT DVDD Figure 67. Equivalent Digital Input D3 D Rev. E Page 5 of 4

26 Because the is capable of being clocked up to 5 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. Operating the with reduced logic swings and a corresponding digital supply (DVDD/DVDD) results in the lowest data feedthrough and on-chip digital noise. The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the as well as its required minimum and maximum input logic level thresholds. Digital signal paths should be kept short, and run lengths should be matched to avoid propagation delay mismatch. The insertion of a low value (that is, Ω to Ω) resistor network between the digital inputs and driver outputs can be helpful in reducing any overshooting and ringing at the digital inputs that contribute to digital feedthrough. For longer board traces and high data update rates, stripline techniques with proper impedance and termination resistors should be considered to maintain clean digital inputs. The external clock driver circuitry provides the AD9763/AD97/ AD9767 with a low-jitter clock input meeting the minimum and maximum logic levels while providing fast edges. Fast clock edges help minimize jitter manifesting itself as phase noise on a reconstructed waveform. Therefore, the clock input should be driven by the fastest logic family suitable for the application. Note that the clock input can also be driven via a sine wave, which is centered around the digital threshold (that is, DVDDx/) and meets the minimum and maximum logic threshold. This typically results in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. In addition, at higher sampling rates, the % tolerance of the digital logic threshold should be considered, because it affects the effective clock duty cycle and, subsequently, cuts into the required data setup and hold times. Input Clock and Data Timing Relationship SNR in a DAC is dependent on the relationship between the position of the clock edges and the point in time at which the input data changes. The are rising edge triggered and therefore exhibit SNR sensitivity when the data transition is close to this edge. The goal when applying the is to make the data transition close to the falling clock edge. This becomes more important as the sample rate increases. Figure 68 shows the relationship of SNR to clock placement with different sample rates. Note that at the lower sample rates, much more tolerance is allowed in clock placement; much more care must be taken at higher rates. SNR (dbc) AD9763 AD97 AD TIME OF DATA CHANGE RELATIVE TO RISING CLOCK EDGE (ns) Figure 68. SNR vs. Clock fout = MHz and fclk = 5 MSPS SLEEP MODE OPERATION The has a power-down function that turns off the output current and reduces the supply current to less than 8.5 ma over the specified supply range of 3.3 V to 5 V and over the full operating temperature range. This mode can be activated by applying a Logic Level to the SLEEP pin. The SLEEP pin logic threshold is equal to.5 AVDD. This digital input also contains an active pull-down circuit that ensures the remains enabled if this input is left disconnected. The require less than 5 ns to power down and approximately 5 μs to power back up. POWER DISSIPATION The power dissipation (PD) of the is dependent on several factors, including the power supply voltages (AVDD and DVDD/DVDD) the full-scale current output (IOUTFS) the update rate (fclk) the reconstructed digital input waveform The power dissipation is directly proportional to the analog supply current (IAVDD) and the digital supply current (IDVDD). IAVDD is directly proportional to IOUTFS, as shown in Figure 69, and is insensitive to fclk. Conversely, IDVDD is dependent on the digital input waveform, the fclk, and the digital supply (DVDD/DVDD). Figure and Figure 7 show IDVDD as a function of full-scale sine wave output ratios (fout/fclk) for various update rates with DVDD = DVDD = 5 V and DVDD = DVDD = 3.3 V, respectively. Note that IDVDD is reduced by more than a factor of when DVDD/DVDD is reduced from 5 V to 3.3 V Rev. E Page 6 of 4