Octal, 16-Bit DAC with 5 ppm/ C On-Chip Reference in 14-Lead TSSOP AD5668-EP

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1 Data Sheet Octal, -Bit with 5 ppm/ C On-Chip Reference in -Lead TSSOP FEATURES Enhanced product features Supports defense and aerospace applications (AQEC) Military temperature range ( 55 C to +5 C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request Low power, smallest pin-compatible octal : bits -lead TSSOP On-chip.5 V, 5 ppm/ C reference Power down to na at 5 V, na at 3 V.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale or midscale 3 power-down functions Hardware L and L override function CLR function to programmable code Rail-to-rail operation APPLICATIONS Process control Data acquisition systems Portable battery-powered instruments SCLK SYNC DIN FUNCTIONAL BLOCK DIAGRAM L INTERFACE LOGIC L CLR RU- PACKAGE ONLY V DD POWER-ON RESET Figure. V REFIN /V REFOUT A B C D E F G H.5V/.5V REF POWER-DOWN LOGIC GND V OUT A V OUT B V OUT C V OUT D V OUT E V OUT F V OUT G V OUT H 93- GENERAL DESCRIPTION The is a low power, octal, -bit, buffered voltageoutput digital-to-analog converter (). It operates from a single.7 V to 5.5 V supply and is guaranteed monotonic by design. The has an on-chip reference with an internal gain of. The has a.5 V, 5 ppm/ C reference, giving a full-scale output range of.5 V. The on-board reference is off at power-up, allowing the use of an external reference, and the internal reference is enabled via a software write. The part incorporates a power-on-reset circuit that ensures that the output powers up to V and remains powered up at this level until a valid write takes place. The part contains a powerdown feature that reduces the current consumption of the device to na at 5 V and provides software-selectable output loads while in power-down mode for any or all channels. The outputs of all s can be updated simultaneously using the L function, with the added functionality of user-selectable Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. channels to simultaneously update. There is also an asynchronous CLR that updates all s to a userprogrammable code zero scale, midscale, or full scale. The uses a versatile 3-wire serial interface that operates at clock rates up to 5 MHz and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards. Additional application and technical information can be found in the AD5 data sheet. PRODUCT HIGHLIGHTS. Octal, -bit.. On-chip.5 V/.5 V, 5 ppm/ C reference. 3. Available in -lead TSSOP.. Power-on reset to V or midscale. 5. Power-down capability. When powered down, the typically consumes na at 3 V and na at 5 V. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Product Highlights... Revision History... Specifications... 3 Data Sheet Timing Characteristics...5 Absolute Maximum Ratings... ESD Caution... Pin Configurations and Function Descriptions...7 Typical Performance Characteristics... Outline Dimensions... Ordering Guide... AC Characteristics... REVISION HISTORY /5 Rev. to Rev. A Changes to Ordering Guide... / Revision : Initial Version Rev. A Page of

3 Data Sheet SPECIFICATIONS VDD =.5 V to 5.5 V, RL = kω to GND, CL = pf to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Temperature range is 55 C to +5 C, typical at +5 C. Table. Parameter Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE Resolution Bits Relative Accuracy ± ± LSB See Figure Differential Nonlinearity ± LSB Guaranteed monotonic by design (see Figure 7) Zero-Code Error mv All s loaded to register (see Figure 9) Zero-Code Error Drift ± µv/ C Full-Scale Error. % FSR All s loaded to register (see Figure ) Gain Error ± % FSR Gain Temperature Coefficient ±.5 ppm Of FSR/ C Offset Error ± ± mv DC Power Supply Rejection Ratio db VDD ± % DC Crosstalk (External Reference) µv Due to full-scale output change, RL = kω to GND or VDD 5 µv/ma Due to load current change µv Due to powering down (per channel) DC Crosstalk (Internal Reference) 5 µv Due to full-scale output change, RL = kω to GND or VDD µv/ma Due to load current change OUTPUT CHARACTERISTICS Output Voltage Range VDD V Capacitive Load Stability nf RL = nf RL = kω DC Output Impedance.5 Ω Short-Circuit Current 3 ma VDD = 5 V Power-Up Time µs Coming out of power-down mode, VDD = 5 V REFERENCE S Reference Current 55 µa VREF = VDD = 5.5 V (per channel) Reference Input Range VDD V Reference Input Impedance. kω REFERENCE OUTPUT Output Voltage.7.53 V At ambient Reference Temperature Coefficient ±5 ppm/ C Reference Output Impedance 7.5 kω LOGIC S Input Current ±3 µa All digital inputs Input Low Voltage, VINL. V VDD = 5 V Input High Voltage, VINH V VDD = 5 V Pin Capacitance 3 pf POWER REQUIREMENTS VDD V All digital inputs at or VDD, active, excludes load current IDD (Normal Mode) 3 VIH = VDD and VIL = GND VDD =.5 V to 5.5 V.3. ma Internal reference off VDD =.5 V to 5.5 V. ma Internal reference on IDD (All Power-Down Modes) VDD =.5 V to 5.5 V. µa VIH = VDD and VIL = GND Linearity calculated using a reduced code range of AD5 (Code 5 to 5,). Output unloaded. Guaranteed by design and characterization; not production tested. 3 Interface inactive. All s active. outputs unloaded. All eight s powered down. Rev. A Page 3 of

4 Data Sheet AC CHARACTERISTICS VDD =.7 V to 5.5 V, RL = kω to GND, CL = pf to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Temperature range is 55 C to +5 C, typical at +5 C. Table. Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time µs ¼ to ¾ scale settling to ± LSB Slew Rate.5 V/µs Digital-to-Analog Glitch Impulse nv-sec LSB change around major carry (see Figure ) Digital Feedthrough. nv-sec Reference Feedthrough 9 db VREF = V ±. V p-p, frequency = Hz to MHz Digital Crosstalk.5 nv-sec Analog Crosstalk.5 nv-sec -to- Crosstalk 3 nv-sec Multiplying Bandwidth 3 khz VREF = V ±. V p-p Total Harmonic Distortion db VREF = V ±. V p-p, frequency = khz Output Noise Spectral Density nv/ Hz code = x, khz nv/ Hz code = x, khz Output Noise 5 μv p-p. Hz to Hz Guaranteed by design and characterization; not production tested. Rev. A Page of

5 Data Sheet TIMING CHARACTERISTICS All input signals are specified with tr = tf = ns/v (% to 9% of VDD) and timed from a voltage level of (VIL + VIH)/. See Figure. VDD =.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Limit at TMIN, TMAX Parameter VDD =.7 V to 5.5 V Unit Conditions/Comments t ns min SCLK cycle time t ns min SCLK high time t3 ns min SCLK low time t 3 ns min SYNC to SCLK falling edge set-up time t5 ns min Data setup time t ns min Data hold time t7 ns min SCLK falling edge to SYNC rising edge t 5 ns min Minimum SYNC high time t9 3 ns min SYNC rising edge to SCLK fall ignore t ns min SCLK falling edge to SYNC fall ignore t ns min L pulse width low t 5 ns min SCLK falling edge to L rising edge t3 5 ns min CLR pulse width low t ns min SCLK falling edge to L falling edge t5 3 ns typ CLR pulse activation time Maximum SCLK frequency is 5 MHz at VDD =.7 V to 5.5 V. Guaranteed by design and characterization; not production tested. t t t 9 SCLK t t t 3 t t 7 SYNC t 5 t DIN DB3 DB t t L t L CLR t 3 VOUT t 5 ASYNCHRONOUS L UPDATE MODE. SYNCHRONOUS L UPDATE MODE. 93- Figure. Serial Write Operation Rev. A Page 5 of

6 ABSOLUTE MAXIMUM RATINGS TA = 5 C, unless otherwise noted. Table. Parameter Rating VDD to GND.3 V to +7 V Digital Input Voltage to GND.3 V to VDD +.3 V VOUT to GND.3 V to VDD +.3 V VREFIN/VREFOUT to GND.3 V to VDD +.3 V Operating Temperature Range Industrial 55 C to +5 C Storage Temperature Range 5 C to +5 C Junction Temperature (TJ MAX) 5 C TSSOP Package Power Dissipation (TJ MAX TA)/θJA θja Thermal Impedance 5. C/W Reflow Soldering Peak Temperature SnPb C Pb Free C Data Sheet Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. A Page of

7 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS L SCLK SYNC 5 DIN V DD 3 GND V OUT A V OUT C 5 TOP VIEW (Not to Scale) 3 V OUT B V OUT D V OUT E V OUT F V OUT G 7 V OUT H V REFIN /V REFOUT 9 CLR 93-3 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin Number Mnemonic L SYNC 3 VDD VOUTA 5 VOUTC VOUTE 7 VOUTG VREFIN/VREFOUT 9 CLR VOUTH VOUTF VOUTD 3 VOUTB GND 5 DIN SCLK Rev. A Page 7 of

8 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS INL ERROR (LSB) V DD = V REF = 5V DNL ERROR (LSB) V DD = 3V V REFOUT =.5V 5k k 5k k 5k 3k 35k k 5k 5k 55k k 5k CODE Figure. INL External Reference CODE Figure 7. DNL V DD = 3V V REFOUT =.5V... INL ERROR (LSB) ERROR (% FSR).... FULL-SCALE ERROR GAIN ERROR CODE Figure 5. INL TEMPERATURE ( C) Figure. Gain Error and Full-Scale Error vs. Temperature V DD = V REF = 5V.5. DNL ERROR (LSB) ERROR (mv) ZERO-SCALE ERROR OFFSET ERROR. k k 3k k 5k k CODE Figure. DNL External Reference TEMPERATURE ( C) Figure 9. Zero-Scale Error and Offset Error vs. Temperature 93-9 Rev. A Page of

9 Data Sheet..5 V DD = 3.V V DD = 5.5V ERROR (% FSR).5. GAIN ERROR FULL-SCALE ERROR FREQUENCY V REFOUT =.5V V REFOUT =.5V V DD (V) Figure. Gain Error and Full-Scale Error vs. Supply Voltage I DD (ma) Figure 3. IDD Histogram with Internal Reference ZERO-SCALE ERROR.5..3 LOADED WITH FULL-SCALE SOURCING CURRENT LOADED WITH ZERO-SCALE SINKING CURRENT ERROR (mv).5..5 ERROR VOLTAGE (V).... V DD = 3V V REFOUT =.5V. OFFSET ERROR.3. V REFOUT =.5V V DD (V) Figure. Zero-Scale Error and Offset Error vs. Supply Voltage CURRENT (ma) Figure. Headroom at Rails vs. Source and Sink 93- V DD = 3.V V DD = 5.5V 5 V REFOUT =.5V 3/ SCALE FULL SCALE FREQUENCY V OUT (V) 3 MIDSCALE / SCALE ZERO SCALE I DD (ma) Figure. IDD Histogram with External Reference CURRENT (ma) Figure 5. Source and Sink Capability 93-5 Rev. A Page 9 of

10 Data Sheet.. V DD = V REF = 5V 7.. I DD (ma)..... V DD = V REF = 3V I DD (ma) CODE Figure. Supply Current vs. Code 93-7 V DD = 3V 3 5 V LOGIC (V) Figure 9. Supply Current vs. Logic Input Voltage 93-. V DD = V REFIN = 5.5V. I DD (ma).... V DD = V REFIN = 3.V V DD = V REF = 5V FULL-SCALE CODE CHANGE x TO xffff OUTPUT LOADED WITH kω AND pf TO GND.. V OUT = 99mV/DIV TEMPERATURE ( C) Figure 7. Supply Current vs. Temperature 93- TIME BASE = µs/div Figure. Full-Scale Settling Time, 5 V T A =5 C V DD = V REF = 5V.. I DD (ma).. V DD.. V OUT MAX(C)*.mV V DD (V) 93-9 CH.V CH 5mV Mµs 5MS/s A CH.V.ns/pt 93- Figure. Supply Current vs. Supply Voltage Figure. Power-On Reset to V Rev. A Page of

11 Data Sheet V DD = V REF = 5V V DD V OUT (V) V OUT CH.V CH.V Mµs 5MS/s A CH.V Figure. Power-On Reset to Midscale.ns/pt V REFOUT =.5V.95 ns/sample NUMBER SAMPLE Figure 5. Analog Crosstalk 93- SYNC.9 3 SLCK V OUT (V) CH 5.V CH3 5.V V OUT CH 5mV Mns A CH.V Figure 3. Exiting Power-Down to Midscale V REFOUT =.5V.55 ns/sample NUMBER SAMPLE Figure. -to- Crosstalk 93-7 V OUT (V) V REFOUT =.5V.5.5 ns/sample NUMBER.5 GLITCH IMPULSE = 3.55nV-s.99 LSB CHANGE AROUND.9 MIDSCALE (x TO x7fff) SAMPLE Figure. Digital-to-Analog Glitch Impulse (Negative) 93-5 µv/div V DD = V REF = 5V LOADED WITH MIDSCALE s/div Figure 7.. Hz to Hz Output Noise Plot, External Reference 93- Rev. A Page of

12 Data Sheet V REFOUT =.5V LOADED WITH MIDSCALE 3 LOADED WITH FULL SCALE V REF = V ±.3V p-p µv/div (db) s/DIV Figure.. Hz to Hz Output Noise Plot, Internal Reference V DD = 3V V REFOUT =.5V LOADED WITH MIDSCALE 93-9 V REF = V DD k k k k k FREQUENCY (Hz) Figure 3. Total Harmonic Distortion V DD = 3V µV/DIV TIME (µs) s/div Figure 9.. Hz to Hz Output Noise Plot, Internal Reference CAPACITANCE (nf) Figure 3. Settling Time vs. Capacitive Load MIDSCALE LOADED 3 CLR OUTPUT NOISE (nv/ Hz) 5 3 V REFOUT =.5V V OUT F V OUT B V DD = 3V V REFOUT =.5V k k k M FREQUENCY (Hz) Figure 3. Noise Spectral Density, Internal Reference 93-3 CH.V Mns A CH3.V CH3 5.V CH.V Figure 33. Hardware CLR 93-3 Rev. A Page of

13 Data Sheet 5 5 (db) k k M M FREQUENCY (Hz) Figure 3. Multiplying Bandwidth Rev. A Page 3 of

14 Data Sheet OUTLINE DIMENSIONS BSC.5.5 PIN.5 BSC.3.9 COPLANARITY.. MAX SEATING PLANE..5 COMPLIANT TO JEDEC STANDARDS MO-53-AB Figure 35. -Lead Thin Shrink Small Outline Package [TSSOP] (RU-) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Power-On Reset to Code Accuracy Internal Reference AD5SRU-EP- 55 C to +5 C -Lead TSSOP RU- Zero ± LSB INL.5 V AD5SRU-EP-RL7 55 C to +5 C -Lead TSSOP RU- Zero ± LSB INL.5 V 5 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D93--/5(A) Rev. A Page of

Octal, 12-/14-/16-Bit DAC with 5 ppm/ C On-Chip Reference in 14-Lead TSSOP AD5628/AD5648/AD5668

Octal, 12-/14-/16-Bit DAC with 5 ppm/ C On-Chip Reference in 14-Lead TSSOP AD5628/AD5648/AD5668 Octal, -/4-/6-Bit with 5 ppm/ C On-Chip Reference in 4-Lead TSSOP AD568/AD5648/AD5668 FEATURES Low power, smallest-pin-compatible octal s AD5668: 6 bits AD5648: 4 bits AD568: bits 4-lead/6-lead TSSOP On-chip.5