800 MHz, 4:1 Analog Multiplexer ADV3221/ADV3222

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1 8 MHz, : Analog Multiplexer ADV/ADV FEATURES Excellent ac performance db bandwidth 8 MHz ( mv p-p) 7 MHz ( V p-p) Slew rate: V/μs Low power: 7 mw, VS = ± V Excellent video performance MHz,. db gain flatness.% differential gain error/. differential phase error (RL = Ω) ADV is a pin-for-pin upgrade to the HA Gain = + (ADV) or gain = + (ADV) Low all hostile crosstalk of 8 MHz, and 8 MHz Latched control lines for synchronous switching High impedance output disable allows connection of multiple devices without loading the output bus 6-lead SOIC APPLICATIONS Routing of high speed signals including Video (NTSC, PAL, S, SECAM, YUV, RGB) Compressed video (MPEG, wavelet) -level digital video (HDB) Data communications Telecommunications GENERAL DESCRIPTION The ADV and ADV are high speed, high slew rate, buffered : analog multiplexers. They offer a db signal bandwidth greater than 8 MHz and channel switch times of less than ns with % settling. With lower than 8 db of crosstalk and 67 db isolation (at MHz), the ADV and ADV are useful in many high speed applications. The differential gain error of less than.% and differential phase error of less than., together with. db gain flatness out to MHz while driving a 7 Ω back terminated load, make the ADV and ADV ideal for all types of signal switching. The ADV/ADV include an output buffer that can be placed into a high impedance state. This allows multiple outputs CS A A CK CK FUNCTIONAL BLOCK DIAGRAM D Q LATCH D Q LATCH D Q LATCH kω D Q LATCH D Q LATCH D Q LATCH kω DECODE IN IN IN IN Figure. ENABLE G = + (G = +) OUT to be connected together for cascading stages without the off channels loading the output bus. The ADV has a gain of +, and the ADV has a gain of +; they both operate on ± V supplies while consuming less than 7. ma of idle current. The channel switching is performed via latched control lines, allowing synchronous updating in a multiple ADV/ADV environment. The ADV/ADV are offered in a 6-lead SOIC package and are available over the extended industrial temperature range of C to +8 C. 86- Rev. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 ADV/ADV TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Revision History... Specifications... Timing and Logic Characteristics... Absolute Maximum Ratings... 6 Thermal Resistance... 6 Power Dissipation... 6 ESD Caution... 6 Pin Configuration and Function Descriptions... 7 Typical Performance Characteristics...8 Circuit Diagrams... 6 Theory of Operation... 7 Applications Information... 8 CK/CK Operation... 8 Circuit Layout... 8 Termination... 8 Capacitive Load... 8 Outline Dimensions... 9 Ordering Guide... 9 REVISION HISTORY / Revision : Initial Version Rev. Page of

3 ADV/ADV SPECIFICATIONS VS = ± V, TA = C, RL = Ω, CL = pf, ADV at G = +, ADV at G = +, unless otherwise noted. Table. ADV ADV Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth mv p-p 8 MHz V p-p 7 7 MHz Gain Flatness. db, mv p-p MHz. db, V p-p MHz Propagation Delay V p-p 7 6 ps Settling Time %, V step ns Slew Rate V step, peak 7 V/μs NOISE/DISTORTION PERFORMANCE Differential Gain Error NTSC or PAL.. % Differential Phase Error NTSC or PAL.. Degrees Crosstalk, All Hostile f = MHz 87 8 db f = MHz 8 db Off Isolation, Input to Output f = MHz, one channel 67 7 db Input Second-Order Intercept (ADV Only) f = 7 MHz, RL = Ω dbm Input Third-Order Intercept (ADV Only) f = 7 MHz, RL = Ω 7 dbm Output db Compression Point (ADV Only) f = 7 MHz, RL = Ω 8. dbm Input Voltage Noise MHz to MHz 6 7 nv/ Hz DC PERFORMANCE Gain Error No load % RL = Ω.7.7 % Gain Matching Channel-to-channel, no load % OUTPUT CHARACTERISTICS Output Impedance DC, enabled.. Ω Disabled MΩ Output Disable Capacitance Disabled.8 pf Output Leakage Current Disabled μa Output Voltage Range No load ±.9 ± ±.9 ± V RL = Ω ±.8 ± ±.7 ± V Short-Circuit Current ma INPUT CHARACTERISTICS Input Offset Voltage Worst case (all configurations) ± ± ± ± mv Input Offset Voltage Drift ± ± μv/ C Input Voltage Range ± ±. V Input Capacitance Any switch configuration.8.8 pf Input Resistance Output enabled MΩ Input Bias Current Output enabled 6 μa SWITCHING CHARACTERISTICS Enable On Time ns Switching Time, V Step % A to % settling ns Switching Transient (Glitch) IN to IN switching 8 mv p-p Rev. Page of

4 ADV/ADV ADV ADV Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit POWER SUPPLIES Supply Current V+, output enabled, no load ma V+, output disabled (CS high) ma V, output enabled, no load ma V, output disabled (CS high) ma Supply Voltage Range ±. ±. ±. ±. V Power Supply Rejection (PSR) f = khz 7 6 db f = MHz 6 db TEMPERATURE Operating Temperature Range Still air C Junction-to-Ambient Thermal Impedance (θja) Operating (still air) 8 8 C/W TIMING AND LOGIC CHARACTERISTICS Table. Parameter Symbol Min Typ Max Unit A, A, CS Setup Time t ns CK Pulse Width t ns CK to CK Pulse Separation t ns CK Pulse Width t ns A, A, CS Hold Time t ns Table. Logic Levels VIH VIL IIH IIL IIH IIL A, A, CK, CK, CS A, A, CK, CK, CS A, A, CS A, A, CS CK, CK CK, CK +. V min +.8 V max ± μa max ± μa max +6 μa max + μa max Rev. Page of

5 ADV/ADV Timing and Programming Diagrams t t CK t CK t A, A, CS t Figure. Timing Diagram 86- CK CK A A CS OUTPUT XX IN IN HIGH-Z 86- Figure. Programming Example Rev. Page of

6 ADV/ADV ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage (V+ V ) V Analog Input Voltage V to V+ Digital Input Voltage V to V+ Output Voltage (Disabled Output) (V+ V) to (V + V) Output Short-Circuit Duration Momentary Output Short-Circuit Current ma Storage Temperature Range 6 C to + C Operating Temperature Range C to +8 C Lead Temperature (Soldering, sec) C Junction Temperature C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. POWER DISSIPATION The ADV/ADV are operated with ± V supplies and can drive loads down to Ω, resulting in a wide range of possible power dissipations. For this reason, extra care must be taken to adjust the operating conditions based on ambient temperature. Packaged in a 6-lead narrow-body SOIC, the ADV and ADV junction-to-ambient thermal impedance (θja) is 8 C/W. For long-term reliability, the maximum allowed junction temperature of the die, TJ, should not exceed C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in stresses exerted on the die by the package. Figure shows the range of the allowed internal die power dissipations that meet these conditions over the C to +8 C ambient temperature range. When using Figure, do not include the external load power in the maximum power calculation, but do include the load current through the die output transistors.. T J = C THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table. Thermal Resistance Package Type θja θjc Unit 6-Lead Narrow-Body SOIC 8 C/W MAXIMUM POWER (W) AMBIENT TEMPERATURE ( C) 86- Figure. Maximum Die Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. Page 6 of

7 ADV/ADV PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 6. Pin Function Descriptions IN GND IN ADV/ ADV 6 V+ A A GND CS IN TOP VIEW (Not to Scale) OUT GND 6 CK IN 7 CK GND 8 9 V Figure. Pin Configuration Pin No. Mnemonic Description IN Analog Input GND Ground IN Analog Input GND Ground IN Analog Input 6 GND Ground 7 IN Analog Input 8 GND Ground 9 V Negative Power Supply CK First Rank Clock CK Second Rank Clock OUT Analog Output CS Chip Select (Output Enable) A Select Address Most Significant Bit A Select Address Least Significant Bit 6 V+ Positive Power Supply Table 7. Truth Table CS A A CK CK Output IN IN IN IN X X High-Z X is don t care. 86- Rev. Page 7 of

8 ADV/ADV TYPICAL PERFORMANCE CHARACTERISTICS GAIN (db) pf pf.7pf pf k k Figure 6. ADV Small Signal Response vs. Capacitive Load, mv p-p 86- GAIN (db) pf pf.7pf pf k k Figure 9. ADV Small Signal Response vs. Capacitive Load, mv p-p 86- GAIN (db) pf pf.7pf pf k k Figure 7. ADV Large Signal Response vs. Capacitive Load, V p-p 86- GAIN (db) pf pf.7pf pf k k Figure. ADV Large Signal Response vs. Capacitive Load, V p-p pf pf.7pf pf.. pf pf.7pf pf... Figure 8. ADV Small Signal Pulse Response vs. Capacitive Load, mv p-p 86-. Figure. ADV Small Signal Pulse Response vs. Capacitive Load, mv p-p 86-7 Rev. Page 8 of

9 ADV/ADV pf pf.7pf pf pf pf.7pf pf Figure. ADV Large Signal Pulse Response vs. Capacitive Load, V p-p 86-8 Figure. ADV Large Signal Pulse Response vs. Capacitive Load, V p-p SLEW RATE (V/µs) dv/dt.. SLEW RATE (V/µs) dv/dt.. V OUT. V OUT.. Figure. ADV Large Signal Rising Slew Rate with pf Load, V p-p Figure 6. ADV Large Signal Rising Slew Rate with pf Load, V p-p V OUT. V OUT. SLEW RATE (V/µs) dv/dt.. SLEW RATE (V/µs) dv/dt..... Figure. ADV Large Signal Falling Slew Rate with pf Load, V p-p 86-. Figure 7. ADV Large Signal Falling Slew Rate with pf Load, V p-p 86- Rev. Page 9 of

10 ADV/ADV..... V OUT FALLING EDGE.9. V OUT FALLING EDGE A.. A (V) A.. A (V)..... V OUT RISING EDGE.9 V OUT RISING EDGE Figure 8. ADV Switching Time Figure. ADV Switching Time OUTPUT V OUT (mv) OUTPUT CS (V) V OUT (mv) CS (V) 6 8 CS 6 8 CS Figure 9. ADV Enable Glitch Figure. ADV Enable Glitch CS INPUT +V.7 CS INPUT +.V.7 INPUT V... CS (V) INPUT.V... CS (V) Figure. ADV Enable On Timing Figure. ADV Enable On Timing Rev. Page of

11 ADV/ADV INPUT +V.7. INPUT +.V.7 CS.. CS (V) CS.. CS (V). INPUT V.. INPUT.V Figure. ADV Disable Timing Figure 7. ADV Disable Timing A 8 6 A V OUT (mv) OUTPUT A (V) V OUT (mv) OUTPUT A (V) Figure. ADV Switching Glitch Rising Edge Figure 8. ADV Switching Glitch Rising Edge V OUT (mv) OUTPUT A (V) V OUT (mv) OUTPUT A (V) 6 8 A 6 8 A Figure 6. ADV Switching Glitch Falling Edge Figure 9. ADV Switching Glitch Falling Edge Rev. Page of

12 ADV/ADV INPUT.. OUTPUT...7 INPUT.7.. ERROR (%) OUTPUT ERROR... OUTPUT (V) ERROR (%) ERROR... OUTPUT (V) Figure. ADV Settling Time, V Step Figure. ADV Settling Time, V Step PSR (db) PSR (V ) PSR (V+) PSR (db) PSR (V ) PSR (V+) k k k k 86- Figure. ADV PSR Figure. ADV PSR NOISE (nv/ Hz) 8 NOISE (nv/ Hz) k k k M M M FREQUENCY (Hz) 86-8 k k k M M M FREQUENCY (Hz) 86- Figure. ADV Output Noise vs. Frequency Figure. ADV Output Noise vs. Frequency Rev. Page of

13 ADV/ADV CROSSTALK (db) CROSSTALK (db) k k 86- k k 86- Figure 6. ADV All Hostile Crosstalk Figure 9. ADV All Hostile Crosstalk CROSSTALK (db) CROSSTALK (db) k k 86- k k 86-6 Figure 7. ADV Crosstalk, Adjacent Channel Figure. ADV Crosstalk, Adjacent Channel FEEDTHROUGH (db) 6 7 FEEDTHROUGH (db) k k 86- k k 86-7 Figure 8. ADV Off Isolation Figure. ADV Off Isolation Rev. Page of

14 ADV/ADV M k INPUT IMPEDANCE (Ω) k k INPUT S (db). k Figure. ADV/ADV Input Impedance k k Figure. ADV/ADV S (Including Evaluation Board) 86- M M DISABLED OUTPUT IMPEDANCE (Ω) k k k DISABLED OUTPUT IMPEDANCE (Ω) k k k. k k 86- Figure. ADV Disabled Output Impedance Figure 6. ADV Disabled Output Impedance k k ENABLED OUTPUT IMPEDANCE (Ω) k. ENABLED OUTPUT IMPEDANCE (Ω) k... k k k k 86- Figure. ADV Enabled Output Impedance Figure 7. ADV Enabled Output Impedance Rev. Page of

15 ADV/ADV INPUT INPUT... OUTPUT VOLTAGE (V) OUTPUT INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT.... INPUT VOLTAGE (V) Figure 8. ADV Overdrive Recovery Figure. ADV Overdrive Recovery 7 HARMONIC DISTORTION (dbc) HD dbm HD dbm HD dbm HD dbm SECOND-ORDER INTERCEPT (dbm) 6 9 k INPUT Figure 9. ADV Harmonic Distortion, RL = Ω, CL = pf 86- k INPUT Figure. ADV Input Second-Order Intercept, RL = Ω, CL = pf THIRD-ORDER INTERCEPT (dbm) PdB GAIN COMPRESSION (dbm) k INPUT Figure. ADV Input Third-Order Intercept, RL = Ω, CL = pf 86-6 k Figure. ADV Output PdB, RL = Ω, CL = pf 86-9 Rev. Page of

16 ADV/ADV CIRCUIT DIAGRAMS V+ IN.8pF V Figure. ADV/ADV Analog Input 86-6 OUT.8pF (ADV).pF (ADV) Figure 7. ADV/ADV Disabled Output 86-9 V+ OUT Figure. ADV Enabled Analog Output 86-7 A, A, CS CK, CK kω (CK, CK ONLY) kω V GND Figure 8. ADV/ADV Logic Input 86- V+ OUT kω IN, OUT A, A, CK, CK, CS kω GND Figure 6. ADV Enabled Analog Output 86-8 V GND Figure 9. ADV/ADV ESD Schematic 86- Rev. Page 6 of

17 ADV/ADV THEORY OF OPERATION The ADV/ADV are dual-supply, high performance : analog multiplexers, optimized for switching between multiple video sources. High peak slew rates enable wide bandwidth operation for large input signals. Internal compensation provides for high phase margin, allowing low overshoot and fast settling for pulsed inputs. Low enabled and disabled power consumption make the ADV and ADV ideal for constructing larger arrays. The ADV/ADV are organized as four input transconductance stages tied in parallel with a single output transimpedance stage followed by a unity-gain buffer. Internal voltage feedback sets the gain. The ADV is configured as a gain of, while the ADV uses a resistive feedback network and ground buffer to realize gain-of-two operation (see Figure 6). IN V+ OUT When not in use, the output can be placed in a low power, high impedance disabled mode via the CS logic input. This is useful when paralleling multiple ADV/ADV devices in a system to create larger switching arrays. Switching between the inputs is controlled with the A, A, and CS logic inputs, which are latched through two stages of asynchronous latches. CK controls the first stage latch, and CK controls the second stage latch. The latch state is dependent on the level of the CK and CK signals, and it is not edge triggered. When using multiple ADV/ADV devices in a switch design, this double buffered logic allows the use of the CK signal to simultaneously update all ADV/ADV devices in a system. The A and A logic inputs select which input is connected to the output (A is the most significant bit, A is the least significant bit), and the CS logic input determines whether the output is enabled or disabled. IN V V+ V ( MORE INPUTS) kω GND V+ kω V Figure 6. Conceptual Diagram of ADV 86-6 Rev. Page 7 of

18 ADV/ADV APPLICATIONS INFORMATION The ADV and ADV are high speed multiplexers used to switch video or RF signals. The low output impedance of the ADV/ADV allows the output environment to be optimized for use in 7 Ω or Ω systems by choosing the appropriate series termination resistor. For composite video applications, the ADV (gain of +) is typically used to provide compensation for the loss of the output termination. CK/CK OPERATION The ADV/ADV provide a double latched architecture for the A, A (channel selection) and CS (output enable) logic. This allows for simultaneous update of multiple devices in bank switching applications or large multiplexer systems consisting of multiple devices connected to common output busses. Holding CK and CK low places the ADV/ADV in a transparent mode. In transparent mode, all logic changes to A, A, and CS immediately affects the input selection and output enable/disable. CIRCUIT LAYOUT Use of proper high speed design techniques is important to ensure optimum performance. Use a low inductance ground plane for power supply bypassing and to provide high quality return paths for the input and output signals. For best performance, it is recommended that power supplies be bypassed with. μf ceramic capacitors as close to the body of the device as possible. To provide stored energy for lower frequency, high current output driving, place μf tantalum capacitors farther from the device. The input and output signal paths should be stripline or microstrip controlled impedance. Video systems typically use 7 Ω characteristic impedance, whereas RF systems typically use Ω. Various calculators are available to calculate the trace geometry required to produce the proper characteristic impedance. TERMINATION For a controlled impedance situation, termination resistors are required at the inputs and output of the device. The input termination should be a shunt resistor to ground with a value matching the characteristic impedance of the input trace. To reduce reflections, place the input termination resistor as close to the device input pin as possible. To minimize the input-toinput crosstalk, it is important to utilize a low inductance shield between input traces to isolate each input. Consideration of ground current paths must be taken to minimize loop currents in the shields to prevent them from providing a coupling medium for crosstalk. For proper matching, the output series termination resistor should be the same value as the characteristic impedance of the output trace and placed as close to the output of the device as possible. This placement reduces the high frequency effect of series parasitic inductance, which can affect gain flatness and db bandwidth. CAPACITIVE LOAD A high frequency output can have difficulties when driving a large capacitive load, usually resulting in peaking in the frequency domain or overshoot in the time domain. If these effects become too large, oscillation can result. The response of the device under various capacitive loads is shown in Figure 6 through Figure, and in Figure. If a condition arises where excessive load capacitance is encountered and the overshoot is too great or the device oscillates, a small series resistor of a few tens of ohms can be used to improve the performance. Rev. Page 8 of

19 ADV/ADV OUTLINE DIMENSIONS. (.97) 9.8 (.88). (.7).8 (.96) (.).8 (.8). (.98). (.9).7 (.) BSC.7 (.689). (.) 8. (.97). (.98) COPLANARITY.. (.). (.) SEATING PLANE. (.98).7 (.67).7 (.). (.7) COMPLIANT TO JEDEC STANDARDS MS--AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 6. 6-Lead Standard Small Outline Package [SOIC_N] Narrow Body [R-6] Dimensions shown in millimeters and (inches) 666-A ORDERING GUIDE Model Temperature Range Package Description Package Option ADVARZ C to +8 C 6-Lead SOIC_N R-6 ADVARZ-RL C to +8 C 6-Lead SOIC_N, Reel R-6 ADVARZ-R7 C to +8 C 6-Lead SOIC_N, 7 Reel R-6 ADVARZ C to +8 C 6-Lead SOIC_N R-6 ADVARZ-RL C to +8 C 6-Lead SOIC_N, Reel R-6 ADVARZ-R7 C to +8 C 6-Lead SOIC_N, 7 Reel R-6 ADV-EVALZ Evaluation Board ADV-EVALZ Evaluation Board Z = RoHS Compliant Part. Rev. Page 9 of

20 ADV/ADV NOTES Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D86--/() Rev. Page of

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