10-/12-/14-Bit, 125 MSPS Dual TxDAC+ Digital-to-Analog Converters AD9763/AD9765/AD9767

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1 Data Sheet -/1-/14-Bit, 15 MSPS Dual TxDAC+ Digital-to-Analog Converters AD9763/AD97/AD9767 FEATURES -/1-/14-bit dual transmit digital-to-analog converters (DACs) 15 MSPS update rate Excellent SFDR to 5 MHz output: dbc Excellent gain and offset matching:.1% Fully independent or single-resistor gain control Dual-port or interleaved data On-chip 1. V reference 5 V or 3.3 V operation Power dissipation: 3 5 V Power-down mode: 5 5 V 48-lead LQFP APPLICATIONS Communications Base stations Digital synthesis Quadrature modulation 3D ultrasound GENERAL DESCRIPTION The AD9763/AD97/AD9767 are dual-port, high speed, -channel, -/1-/14-bit CMOS DACs. Each part integrates two high quality TxDAC+ cores, a voltage reference, and digital interface circuitry into a small 48-lead LQFP. The AD9763/ AD97/AD9767 offer exceptional ac and dc performance while supporting update rates of up to 15 MSPS. The AD9763/AD97/AD9767 have been optimized for processing I and Q data in communications applications. The digital interface consists of two double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent of one another. Separate clocks control the update rate of the DACs. A mode control pin allows the AD9763/AD97/AD9767 to interface to two separate data ports, or to a single interleaved high speed data port. In interleaving mode, the input data stream is demuxed into its original I and Q data and then latched. The I and Q data is then converted by the two DACs and updated at half the input data rate. The GAINCTRL pin allows two modes for setting the full-scale current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set independently using two external resistors, or IOUTFS for both DACs can be set by using a single external resistor. See the Gain Control Mode section for important date code information on this feature. PORT1 WRT1/IQWRT WRT/IQSEL PORT FUNCTIONAL BLOCK DIAGRAM DVDD1/ DVDD DCOM1/ DCOM DIGITAL INTERFACE MODE AVDD 1 LATCH AD9763/ AD97/ AD9767 LATCH Figure 1. ACOM CLK1 1 DAC REFERENCE BIAS GENERATOR DAC CLK/IQ RESET I OUTA1 I OUTB1 REFIO FSADJ1 FSADJ GAINCTRL SLEEP I OUTA I OUTB The DACs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and maximize dynamic accuracy. Each DAC provides differential current output, thus supporting single-ended or differential applications. Both DACs of the AD9763, AD97, or AD9767 can be simultaneously updated and can provide a nominal full-scale current of ma. The full-scale currents between each DAC are matched to within.1%. The AD9763/AD97/AD9767 are manufactured on an advanced, low cost CMOS process. They operate from a single supply of 3.3 V to 5 V and consume 3 mw of power. PRODUCT HIGHLIGHTS 1. The AD9763/AD97/AD9767 are members of a pincompatible family of dual TxDACs providing 8-, -, 1-, and 14-bit resolution.. Dual -/1-/14-Bit, 15 MSPS DACs. A pair of high performance DACs for each part is optimized for low distortion performance and provides flexible transmission of I and Q information. 3. Matching. Gain matching is typically.1% of full scale, and offset error is better than.%. 4. Low Power. Complete CMOS dual DAC function operates on 3 mw from a 3.3 V to 5 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. On-Chip Voltage Reference. The AD9763/AD97/AD9767 each include a 1. V temperature-compensated band gap voltage reference. 6. Dual -/1-/14-Bit Inputs. The AD9763/AD97/AD9767 each feature a flexible dual-port interface, allowing dual or interleaved input data Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 AD9763/AD97/AD9767 TABLE OF CONTENTS Features... 1 Applications... 1 General Description... 1 Functional Block Diagram... 1 Product Highlights... 1 Revision History... Specifications... 5 DC Specifications... 5 Dynamic Specifications... 6 Digital Specifications... 7 Absolute Maximum Ratings... 8 Thermal Resistance... 8 ESD Caution... 8 Pin Configuration and Function Descriptions... 9 Typical Performance Characteristics AD AD AD Terminology... Theory of Operation... 1 Functional Description... 1 Reference Operation... Gain Control Mode... Setting the Full-Scale Current... DAC Transfer Function... 3 Analog Outputs... 3 Data Sheet Digital Inputs... 4 DAC Timing... 4 Sleep Mode Operation... 6 Power Dissipation... 6 Applying the AD9763/AD97/AD Output Configurations... 8 Differential Coupling Using a Transformer... 8 Differential Coupling Using an Op Amp... 8 Single-Ended, Unbuffered Voltage Output... 9 Single-Ended, Buffered Voltage Output Configuration... 9 Power and Grounding Considerations... 9 Applications Information VDSL Example Applications Using the AD97 and AD Quadrature Amplitude Modulation (QAM) Example Using the AD CDMA Evaluation Board General Description Schematics Evaluation Board Layout... 4 Outline Dimensions... 4 Ordering Guide... 4 REVISION HISTORY Revision History: AD9763/AD97/AD9767 8/11 Rev. F to Rev. G Changes to Gain Control Mode Section and Setting the Full- Scale Current Section... Changes to DAC Transfer Function Section... 3 Changes to Power Supply Rejection Section /9 Rev. E to Rev. F Replaced Figure 86 to Figure 9 with Figure 86 to Figure 91, Deleted Original Figure 91 to Figure /8 Revision E: Initial Combined Version Revision History: AD9763 1/8 Rev. D to Rev. E Combined with AD97 and AD9767 Data Sheets...Universal Changes to Figure Changes to Applications Section...1 Changes to Timing Diagram Section...7 Added Figure 4 and Figure Changes to Table 6... Change to Typical Performance Characteristics Section Conditions Statement Added Figure 3 to Figure Added Note to Figure Changes to Functional Description Section... Changes to Figure 59 and Figure 6... Changes to Gain Control Mode Section... Rev. G Page of 44

3 Data Sheet Replaced Reference Control Amplifier Section with Setting the Full-Scale Current Section... Changes to DAC Transfer Section...3 Change to Analog Outputs Section...4 Changes to Dual-Port Mode Timing...4 Changes to Interleaved Mode Timing Section...5 Added Figure Change to Differential Coupling Using a Transformer Section...8 Changes to Power and Grounding Considerations Section...3 Added VDSL Example Applications Using the AD97 and AD9767 Section...31 Added Figure 79 to Figure Changes to Figure Changes to CDMA Section...33 Changes to Figure 85 Caption...33 Changes to Figure Changes to Figure Changes to Ordering Guide...4 9/6 Rev. C to Rev. D Updated Format... Universal Renumbered Figures... Universal Changes to Specifications Section...3 Changes to Applications Section...1 Updated Outline Dimensions...3 Changes to Ordering Guide...3 /1 Rev. B to Rev. C Changes to Figure / Rev. A to Rev. B 1/99 Rev. to Rev. A Revision History: AD97 1/8 Rev. C to Rev. E Combined with AD9763 and AD9767 Data Sheets... Universal Changes to Figure Changes to Applications Section...1 Changes to Timing Diagram Section...7 Change to Absolute Maximum Ratings...8 Added Figure 3 and Figure Changes to Table 6... Added Figure 6 to Figure...11 Added Figure 4 to Figure Added Note to Figure Changes to Functional Description Section... Changes to Reference Operation Section... Changes to Figure 59 and Figure 6... Changes to Gain Control Mode Section... Replaced Reference Control Amplifier Section with Setting the Full-Scale Current Section... Changes to DAC Transfer Section...3 AD9763/AD97/AD9767 Changes to Interleaved Mode Timing Section...5 Added Figure Changes to Power and Grounding Considerations Section...3 Added Figure and Figure Changes to Quadrature Amplitude Modulation (QAM) Example Using the AD9763 Section...3 Changes to Figure 83 and Figure Changes to CDMA Section...33 Changes to Figure 85 Caption...33 Changes to Figure Changes to Figure Changes to Ordering Guide...4 9/6 Rev. B to Rev. C Updated Format... Universal Changes to Figure...5 Changes to Figure Changes to Functional Description Section...1 Changes to Figure 5 and Figure Changes to Figure 8 and Figure Changes to Power Dissipation Section...17 Changes to Power and Grounding Considerations Section...19 Changes to Figure Changes to Figure Changes to Evaluation Board Section...4 Changes to Figure Updated Outline Dimensions...3 Changes to Ordering Guide...3 / Rev. A to Rev. B 1/99 Rev. to Rev. A 8/99 Revision : Initial Version Revision History: AD9767 1/8 Rev. C to Rev. E Combined with AD9763 and AD97 Data Sheets... Universal Changes to Figure Changes to Features Section...1 Changes to Applications Section...1 Changes to Timing Diagram Section...7 Change to Absolute Maximum Ratings...8 Added Figure 3 and Figure Changes to Table 6... Added Figure 6 to Figure Added Note to Figure Changes to Functional Description Section... Changes to Reference Operation Section... Changes to Figure 59 and Figure 6... Changes to Gain Control Mode Section... Replaced Reference Control Amplifier Section with Setting the Full-Scale Current Section... Changes to DAC Transfer Section...3 Rev. G Page 3 of 44

4 AD9763/AD97/AD9767 Changes to Dual-Port Mode Timing... 4 Changes to Interleaved Mode Timing Section... 5 Added Figure Change to Differential Coupling Using a Transformer Section...8 Changes to Power and Grounding Considerations Section...3 Added Figure 79 and Figure Added to Quadrature Amplitude Modulation (QAM) Example Using the AD9763 Section... 3 Added Figure 83 and Figure Changes to CDMA Section Changes to Figure 85 Caption Changes to Figure Changes to Figure Changes to Ordering Guide... 4 Data Sheet /6 Rev. B to Rev. C Updated Format...Universal Changes to Figure...5 Changes to Figure Changes to Functional Description Section... 1 Changes to Figure 5 and Figure Changes to Figure 8 and Figure Changes to Power Dissipation Section Changes to Figure Changes to Power and Grounding Considerations Section Changes to Figure Changes to Figure Updated Outline Dimensions... 8 Changes to Ordering Guide... 8 / Rev. A to Rev. B 1/99 Rev. to Rev. A 8/99 Revision : Initial Version Rev. G Page 4 of 44

5 Data Sheet AD9763/AD97/AD9767 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD = 3.3 V or 5 V, IOUTFS = ma, unless otherwise noted. Table 1. AD9763 AD97 AD9767 Parameter Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 1 14 Bits DC ACCURACY 1 Integral Linearity Error (INL) 1 ±.1 +1 LSB TA = 5 C 1.5 ± ± LSB TMIN to TMAX LSB Differential Nonlinearity (DNL) LSB TA = 5 C.5 ± ± ± LSB TMIN to TMAX LSB ANALOG OUTPUT Offset Error % of FSR Gain Error Without Internal Reference ±.5 + ±.5 + ±.5 + % of FSR Gain Error with Internal Reference 5 ± ± ±1 +5 % of FSR Gain Match 1.6 ± ± ± % of FSR db Full-Scale Output Current ma Output Compliance Range V Output Resistance kω Output Capacitance pf REFERENCE OUTPUT Reference Voltage V Reference Output Current 3 na REFERENCE INPUT Input Compliance Range V Reference Input Resistance MΩ Small-Signal Bandwidth MHz TEMPERATURE COEFFICIENTS Offset Drift ppm of FSR/ C Gain Drift Without Internal Reference ±5 ±5 ±5 ppm of FSR/ C Gain Drift with Internal Reference ± ± ± ppm of FSR/ C Reference Voltage Drift ±5 ±5 ±5 ppm/ C POWER SUPPLY Supply Voltages AVDD V DVDD1, DVDD V Analog Supply Current (IAVDD) ma Digital Supply Current (IDVDD) ma Digital Supply Current (IDVDD) ma Supply Current Sleep Mode (IAVDD) ma Power Dissipation 4 (5 V, IOUTFS = ma) mw Power Dissipation 5 (5 V, IOUTFS = ma) mw Power Dissipation 6 (5 V, IOUTFS = ma) mw Power Supply Rejection Ratio 7 AVDD % of FSR/V Power Supply Rejection Ratio 7 DVDD % of FSR/V OPERATING RANGE C 1 Measured at IOUTA, driving a virtual ground. Nominal full-scale current, IOUTFS, is 3 times the IREF current. 3 An external buffer amplifier with input bias current < na should be used to drive any external load. 4 Measured at fclk = 5 MSPS and fout = 1. MHz. 5 Measured at fclk = MSPS and fout = 1 MHz. 6 Measured as unbuffered voltage output with IOUTFS = ma and RLOAD = 5 Ω at IOUTA and IOUTB, fclk = MSPS, and fout = 4 MHz. 7 ±% power supply variation. Rev. G Page 5 of 44

6 AD9763/AD97/AD9767 Data Sheet DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD = 3.3 V or 5 V, IOUTFS = ma, differential transformer-coupled output, 5 Ω doubly terminated, unless otherwise noted. Table. AD9763 AD97 AD9767 Parameter Min Typ Max Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate (fclk) MSPS Output Settling Time (tst) to.1% ns Output Propagation Delay (tpd) ns Glitch Impulse pv-s Output Rise Time (% to 9%) ns Output Fall Time (9% to %) ns Output Noise (IOUTFS = ma) pa/ Hz Output Noise (IOUTFS = ma) pa/ Hz AC LINEARITY Spurious-Free Dynamic Range to Nyquist fclk = MSPS, fout = 1. MHz dbfs Output dbc 6 dbfs Output dbc 1 dbfs Output dbc 18 dbfs Output 61 dbc fclk = MSPS, fout = 1. MHz dbc fclk = MSPS, fout =.51 MHz dbc fclk = MSPS, fout = 5. MHz dbc fclk = MSPS, fout = 14. MHz dbc fclk = MSPS, fout = 5 MHz dbc fclk = 15 MSPS, fout = 5 MHz dbc fclk = 15 MSPS, fout = 4 MHz 6 6 dbc Spurious-Free Dynamic Range Within a Window fclk = MSPS, fout = 1. MHz; MHz Span dbc fclk = 5 MSPS, fout = 5. MHz; MHz Span dbc fclk = MSPS, fout = 5.3 MHz; MHz Span dbc fclk = 15 MSPS, fout = 5.4 MHz; MHz Span dbc Total Harmonic Distortion fclk = MSPS, fout = 1. MHz dbc fclk = 5 MSPS, fout =. MHz dbc fclk = 15 MSPS, fout = 4. MHz dbc fclk = 15 MSPS, fout =. MHz 7 dbc Multitone Power Ratio (Eight Tones at 1 khz Spacing) fclk = MSPS, fout =. MHz to.99 MHz dbfs Output 76 dbc 6 dbfs Output dbc 1 dbfs Output dbc 18 dbfs Output dbc Channel Isolation fclk = 15 MSPS, fout = MHz dbc fclk = 15 MSPS, fout = 4 MHz dbc 1 Measured single-ended into 5 Ω load. Rev. G Page 6 of 44

7 Data Sheet AD9763/AD97/AD9767 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD = 3.3 V or 5 V, IOUTFS = ma, unless otherwise noted. Table 3. Parameter Min Typ Max Unit DIGITAL INPUTS Logic 1 DVDD1 = DVDD = 5 V V Logic 1 DVDD1 = DVDD = 3.3 V.1 3 V Logic DVDD1 = DVDD = 5 V 1.3 V Logic DVDD1 = DVDD = 3.3 V.9 V Logic 1 Current + μa Logic Current + μa Input Capacitance 5 pf Input Setup Time (ts). ns Input Hold Time (th) 1.5 ns Latch Pulse Width (tlpw, tcpw) 3.5 ns Timing Diagram See Table 3 and the DAC Timing section for more information about the timing specifications. t S t H DATA IN (WRT) (WRT1/IQWRT) t LPW (CLK) (CLK1/IQCLK) t CPW I OUTA OR I OUTB Figure. Timing Diagram for Dual and Interleaved Modes t PD 617- Rev. G Page 7 of 44

8 AD9763/AD97/AD9767 ABSOLUTE MAXIMUM RATINGS Table 4. With Parameter Respect To Rating AVDD ACOM.3 V to +6.5 V DVDD1, DVDD DCOM1/DCOM.3 V to +6.5 V ACOM DCOM1/DCOM.3 V to +.3 V AVDD DVDD1/DVDD 6.5 V to +6.5 V MODE, CLK1/IQCLK, CLK/IQRESET, WRT1/IQWRT, WRT/IQSEL DCOM1/DCOM.3 V to DVDD1/ DVDD +.3 V Digital Inputs DCOM1/DCOM.3 V to DVDD1/ DVDD +.3 V IOUTA1/IOUTA, ACOM 1. V to AVDD +.3 V IOUTB1/IOUTB REFIO, FSADJ1, ACOM.3 V to AVDD +.3 V FSADJ GAINCTRL, SLEEP ACOM.3 V to AVDD +.3 V Junction 15 C Temperature Storage C to +15 C Temperature Range Lead Temperature ( sec) 3 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Data Sheet θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type θja Unit 48-Lead LQFP 91 C/W ESD CAUTION Rev. G Page 8 of 44

9 Data Sheet AD9763/AD97/AD9767 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS MODE AVDD I OUTA1 I OUTB1 FSADJ1 REFIO GAINCTRL FSADJ I OUTB I OUTA ACOM SLEEP DB9P1 (MSB) DB8P1 DB7P1 DB6P1 DB5P1 DB4P1 DB3P1 DBP1 DB1P1 DBP1 (LSB) NC NC PIN 1 AD9763 TOP VIEW (Not to Scale) 36 NC 35 NC 34 NC 33 NC 3 DBP (LSB) 31 DB1P 3 DBP 9 DB3P 8 DB4P 7 DB5P 6 DB6P 5 DB7P NC = NO CONNECT NC NC DCOM1 DVDD1 WRT1/IQWRT CLK1/IQCLK CLK/IQRESET WRT/IQSEL DCOM DVDD DB9P (MSB) DB8P Figure 3. AD9763 Pin Configuration MODE AVDD I OUTA1 I OUTB1 FSADJ1 REFIO GAINCTRL FSADJ I OUTB I OUTA ACOM SLEEP MODE AVDD I OUTA1 I OUTB1 FSADJ1 REFIO GAINCTRL FSADJ I OUTB I OUTA ACOM SLEEP DB13P1 (MSB) DB1P1 DB11P1 DBP1 DB9P1 DB8P1 DB7P1 DB6P1 DB5P1 DB4P1 DB3P1 DBP PIN 1 AD9767 TOP VIEW (Not to Scale) 36 DBP (LSB) 35 DB1P 34 DBP 33 DB3P 3 DB4P 31 DB5P 3 DB6P 9 DB7P 8 DB8P 7 DB9P 6 DBP 5 DB11P DB1P1 DBP1 (LSB) DCOM1 DVDD1 WRT1/IQWRT CLK1/IQCLK CLK/IQRESET WRT/IQSEL DCOM DVDD DB13P (MSB) DB1P Figure 5. AD9767 Pin Configuration DB11P1 (MSB) DBP1 DB9P1 1 3 PIN 1 36 NC 35 NC 34 DBP (LSB) DB8P DB1P DB7P1 DB6P1 DB5P1 DB4P AD97 TOP VIEW (Not to Scale) 3 DBP 31 DB3P 3 DB4P 9 DB5P DB3P1 9 8 DB6P DBP1 7 DB7P DB1P DB8P DBP1 (LSB) 1 5 DB9P NC = NO CONNECT NC NC DCOM1 DVDD1 WRT1/IQWRT CLK1/IQCLK CLK/IQRESET WRT/IQSEL DCOM DVDD DB11P (MSB) DBP Figure 4. AD97 Pin Configuration Rev. G Page 9 of 44

10 AD9763/AD97/AD9767 Data Sheet Table 6. Pin Function Descriptions Pin No. AD9763 AD97 AD9767 Mnemonic Description 1 to 1 to 1 1 to 14 DBxP1 Data Bit Pins (Port 1) 11 to 14, 13, 14, N/A NC No Connect 33 to 36 35, 36 15, 1 15, 1 15, 1 DCOM1, DCOM Digital Common 16, 16, 16, DVDD1, DVDD Digital Supply Voltage WRT1/IQWRT Input Write Signal for PORT 1 (IQWRT in Interleaving Mode) CLK1/IQCLK Clock Input for DAC1 (IQCLK in Interleaving Mode) CLK/IQRESET Clock Input for DAC (IQRESET in Interleaving Mode) WRT/IQSEL Input Write Signal for PORT (IQSEL in Interleaving Mode) 3 to 3 3 to 34 3 to 36 DBxP Data Bit Pins (Port ) SLEEP Power-Down Control Input ACOM Analog Common 39, 4 39, 4 39, 4 IOUTA, IOUTB Port Differential DAC Current Outputs FSADJ Full-Scale Current Output Adjust for DAC GAINCTRL Master/Slave Resistor Control Mode REFIO Reference Input/Output FSADJ1 Full-Scale Current Output Adjust for DAC1 45, 46 45, 46 45, 46 IOUTB1, IOUTA1 Port 1 Differential DAC Current Outputs AVDD Analog Supply Voltage MODE Mode Select (1 = dual port, = interleaved) Rev. G Page of 44

11 Data Sheet AD9763/AD97/AD9767 TYPICAL PERFORMANCE CHARACTERISTICS AD9763 AVDD = 3.3 V or 5 V, DVDD = 3.3 V, IOUTFS = ma, 5 Ω doubly terminated load, differential output, TA = 5 C, SFDR up to Nyquist, unless otherwise noted. 9 dbfs f CLK = 5MSPS 6dBFS f CLK = 5MSPS 1dBFS 6 f CLK = MSPS 6 55 f CLK = 15MSPS 5 1 f OUT (MHz) f OUT (MHz) Figure 6. SFDR vs. dbfs Figure 9. SFDR vs. MSPS dbfs dbfs 6dBFS 1dBFS 6dBFS 6 1dBFS f OUT (MHz) Figure 7. SFDR vs. 5 MSPS f OUT (MHz) Figure. SFDR vs. 15 MSPS 617- dbfs I OUTFS = ma 1dBFS 6dBFS I OUTFS = ma 6 55 I OUTFS = 5mA f OUT (MHz) f OUT (MHz) Figure 8. SFDR vs. 5 MSPS Figure 11. SFDR vs. fout and MSPS and dbfs Rev. G Page 11 of 44

12 AD9763/AD97/AD9767 Data Sheet 85.7MHz/5MSPS 9kHz/MSPS I OUTFS = ma 5.91MHz/MSPS 11.37MHz/15MSPS SINAD (dbc) 6 I OUTFS = ma 6 I OUTFS = 5mA A OUT (dbfs) Figure 1. Single-Tone SFDR vs. fout = fclk/ f CLK (MSPS) Figure 15. SINAD vs. fclk and fout = 5 MHz and dbfs MHz/5MSPS 5MHz/5MSPS MHz/MSPS 13MHz/MSPS 5MHz/15MSPS INL (LSB) A OUT (dbfs) Figure 13. Single-Tone SFDR vs. fout = fclk/ CODE Figure 16. Typical INL MSPS MSPS.5. 15MSPS DNL (LSB) A OUT (dbfs) Figure 14. Dual-Tone SFDR vs. fout = fclk/ CODE Figure 17. Typical DNL Rev. G Page 1 of 44

13 Data Sheet AD9763/AD97/AD f OUT = 1MHz f OUT = MHz f OUT = 5MHz f OUT = 4MHz SFDR (dbm) f OUT = 6MHz TEMPERATURE ( C) Figure 18. SFDR vs. fclk = 15 MSPS, dbfs FREQUENCY (MHz) Figure 1. Dual-Tone fclk = 15 MSPS OFFSET ERROR (%FS).3.3 OFFSET ERROR GAIN ERROR.5.5 GAIN ERROR (%FS) SFDR (dbm) TEMPERATURE ( C) 1. Figure 19. Gain and Offset Error vs. fclk = 15 MSPS FREQUENCY (MHz) Figure. Four-Tone fclk = 15 MSPS 617- SFDR (dbm) FREQUENCY (MHz) Figure. Single-Tone fclk = 15 MSPS 617- Rev. G Page 13 of 44

14 AD9763/AD97/AD9767 Data Sheet AD97 AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = ma, 5 Ω doubly terminated load, differential output, TA = 5 C, SFDR up to Nyquist, unless otherwise noted. 9 f CLK = 5MSPS 85 f CLK = 5MSPS dbfs f CLK = 15MSPS 1dBFS 6dBFS 6 6 f CLK = MSPS f OUT (MHz) Figure 3. SFDR vs. dbfs f OUT (MHz) Figure 6. SFDR vs. MSPS dbfs dbfs 85 6dBFS 1dBFS 6dBFS 6 1dBFS f OUT (MHz) Figure 4. SFDR vs. 5 MSPS f OUT (MHz) Figure 7. SFDR vs. 15 MSPS dbfs I OUTFS = ma I OUTFS = ma 6dBFS 1dBFS I OUTFS = 5mA f OUT (MHz) Figure 5. SFDR vs. 5 MSPS f OUT (MHz) Figure 8. SFDR vs. fout and MSPS and dbfs Rev. G Page 14 of 44

15 Data Sheet AD9763/AD97/AD MHz/5MSPS.91MHz/MSPS I OUTFS = ma I OUTFS = ma SINAD (dbc) 11.37MHz/15MSPS 6 I OUTFS = 5mA 5.91MHz/MSPS A OUT (dbfs) Figure 9. Single-Tone SFDR vs. fout = fclk/ f CLK (MSPS) Figure 3. SINAD vs. fclk and fout = 5 MHz and dbfs MHz/5MSPS MHz/MSPS 1MHz/5MSPS MHz/MSPS INL (LSB) MHz/15MSPS A OUT (dbfs) Figure 3. Single-Tone SFDR vs. fout = fclk/ CODE Figure 33. Typical INL MHz/3.36MHz@5MSPS.9MHz/1.35MHz@7MSPS.5 6.MHz/7.5MHz@MSPS DNL (LSB) MHz/18.1MHz@15MSPS A OUT (dbfs) Figure 31. Dual-Tone SFDR vs. fout = fclk/ CODE Figure 34. Typical DNL Rev. G Page 15 of 44

16 AD9763/AD97/AD9767 Data Sheet 85 f OUT = 1MHz f OUT = MHz 6 f OUT = 5MHz f OUT = 4MHz SFDR (dbm) f OUT = 6MHz TEMPERATURE ( C) Figure 35. SFDR vs. 15 MSPS, dbfs FREQUENCY (MHz) Figure 38. Dual-Tone fclk = 15 MSPS OFFSET ERROR (%FS).3.3 OFFSET ERROR GAIN ERROR.5.5 GAIN ERROR (%FS) SFDR (dbm) TEMPERATURE ( C) FREQUENCY (MHz) Figure 36. Gain and Offset Error vs. fclk = 15 MSPS Figure 39. Four-Tone fclk = 15 MSPS SFDR (dbm) FREQUENCY (MHz) Figure 37. Single-Tone fclk = 15 MSPS Rev. G Page 16 of 44

17 Data Sheet AD9763/AD97/AD9767 AD9767 AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = ma, 5 Ω doubly terminated load, differential output, TA = 5 C, SFDR up to Nyquist, unless otherwise noted f CLK = 5MSPS f CLK = 5MSPS dbfs f CLK = 15MSPS 6dBFS 1dBFS 6 6 f CLK = MSPS f OUT (MHz) Figure 4. SFDR vs. dbfs f OUT (MHz) Figure 43. SFDR vs. MSPS dbfs dbfs 1dBFS 6dBFS 6 1dBFS 6dBFS f OUT (MHz) Figure 41. SFDR vs. 5 MSPS f OUT (MHz) Figure 44. SFDR vs. 15 MSPS dbfs 85 I OUTFS = 5mA 1dBFS I OUTFS = ma 6dBFS 6 55 I OUTFS = ma f OUT (MHz) Figure 4. SFDR vs. 5 MSPS f OUT (MHz) Figure 45. SFDR vs. fout and MSPS and dbfs Rev. G Page 17 of 44

18 AD9763/AD97/AD9767 Data Sheet 9 9kHz/MSPS 85.7MHz/5MSPS I OUTFS = ma SINAD (dbc) I OUTFS = ma I OUTFS = 5mA 5.91MHz/MSPS 11.37MHz/15MSPS A OUT (dbfs) Figure 46. Single-Tone SFDR vs. fout = fclk/ f CLK (MSPS) Figure 49. SINAD vs. fclk and fout = 5 MHz and dbfs MHz/MSPS 1MHz/5MSPS MHz/5MSPS INL (LSB) MHz/MSPS 5MHz/15MSPS A OUT (dbfs) Figure 47. Single-Tone SFDR vs. fout = fclk/ CODE Figure 5. Typical INL MHz/1.35MHz@7MSPS 3.38MHz/3.63MHz@5MSPS.4.. DNL (LSB) MHz/18.1MHz@15MSPS 6.MHz/7.5MHz@MSPS A OUT (dbfs) Figure 48. Dual-Tone SFDR vs. fout = fclk/ CODE Figure 51. Typical DNL Rev. G Page 18 of 44

19 Data Sheet AD9763/AD97/AD f OUT = 1MHz f OUT = MHz 6 f OUT = 5MHz f OUT = 4MHz SFDR (dbm) f OUT = 6MHz TEMPERATURE ( C) Figure 5. SFDR vs. 15 MSPS, dbfs FREQUENCY (MHz) Figure 55. Dual-Tone fclk = 15 MSPS OFFSET ERROR (%FS).3.3 OFFSET ERROR GAIN ERROR.5.5 GAIN ERROR (%FS) SFDR (dbm) TEMPERATURE ( C) Figure 53. Gain and Offset Error vs. fclk = 15 MSPS FREQUENCY (MHz) Figure 56. Four-Tone fclk = 15 MSPS SFDR (dbm) FREQUENCY (MHz) Figure 54. Single-Tone fclk = 15 MSPS Rev. G Page 19 of 44

20 AD9763/AD97/AD9767 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error Offset error is the deviation of the output current from the ideal of zero. For IOUTA, ma output is expected when the inputs are all s. For IOUTB, ma output is expected when all inputs are set to 1s. Gain Error Gain error is the difference between the actual and ideal output spans. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to s. Output Compliance Range The output compliance range is the range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. Data Sheet Temperature Drift Temperature drift is specified as the maximum change from the ambient (5 C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in part per million (ppm) of full-scale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius (ppm/ C). Power Supply Rejection (PSR) PSR is the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Settling Time Settling time is the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in picovolts per second (pv-s). Spurious-Free Dynamic Range (SFDR) The difference, in decibels (db), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (db). Rev. G Page of 44

21 Data Sheet AD9763/AD97/AD9767 THEORY OF OPERATION 5V CLK1/IQCLK CLK/IQRESET SLEEP R SET 1 kω.1µf R SET kω FSADJ1 REFIO FSADJ 1.V REF GAINCTRL AVDD PMOS CURRENT SOURCE ARRAY PMOS CURRENT SOURCE ARRAY WRT1/ IQWRT AD9763/ AD97/ AD9767 CLK DIVIDER DAC1 LATCH CHANNEL 1 LATCH DAC LATCH MULTIPLEXING LOGIC SEGMENTED SWITCHES FOR DAC1 SEGMENTED SWITCHES FOR DAC CHANNEL LATCH LSB SWITCH LSB SWITCH I OUTA1 I OUTB1 I OUTA I OUTB MODE DVDD1/ DVDD DCOM1/ DCOM ACOM 5Ω 5V Mini-Circuits T1-1T 5Ω TO HP3589A OR EQUIVALENT SPECTRUM/ NETWORK ANALYZER DVDD1/DVDD DCOM1/DCOM RETIMED CLOCK OUTPUT* LECROY 9 PULSE GENERATOR 5Ω PORT 1 PORT DIGITAL DATA TEKTRONIX AWG1 w/option 4 WRT/ IQSEL *AWG1 CLOCK RETIMED SUCH THAT DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 5% DUTY CYCLE CLOCK. Figure 57. Basic AC Characterization Test Setup for AD9763/AD97/AD9767, Testing Port 1 in Dual-Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ V CLK1/IQCLK CLK/IQRESET I REF 1 I REF R SET 1 kω.1µf R SET kω FSADJ1 REFIO FSADJ 1.V REF GAINCTRL AVDD PMOS CURRENT SOURCE ARRAY PMOS CURRENT SOURCE ARRAY AD9763/ AD97/ AD9767 CLK DIVIDER DAC1 LATCH CHANNEL 1 LATCH DAC LATCH MULTIPLEXING LOGIC SEGMENTED SWITCHES FOR DAC1 SEGMENTED SWITCHES FOR DAC CHANNEL LATCH SLEEP ACOM LSB SWITCH LSB SWITCH DCOM1/ DCOM I OUTA1 I OUTB1 I OUTA I OUTB MODE DVDD1/ DVDD V OUT B 5V V DIFF = V OUT A V OUT B R L B 5Ω V OUT A R L A 5Ω V OUT 1B R L 1B 5Ω V OUT 1A R L 1A 5Ω WRT1/ IQWRT PORT 1 PORT DIGITAL DATA INPUTS WRT/ IQSEL NOTES 1. IN THIS CONFIGURATION, THE nf CAPACITOR AND 56Ω RESISTOR ARE NOT REQUIRED BECAUSE R SET = kω. FUNCTIONAL DESCRIPTION Figure 58 shows a simplified block diagram of the AD9763/ AD97/AD9767. The AD9763/AD97/AD9767 consist of two DACs, each one with its own independent digital control logic and full-scale output current control. Each DAC contains a PMOS current source array capable of providing up to ma of full-scale current (IOUTFS). The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an MSB current source. The remaining LSB is a binary weighted fraction of the middle bit current sources. Implementing the middle and lower bits with current sources, instead of an R-R ladder, enhances the dynamic performance for multitone or low amplitude signals and helps maintain the high output impedance of each DAC (that is, > kω). Figure 58. Simplified Block Diagram Rev. G Page 1 of 44 All of these current sources are switched to one of the two output nodes (that is, IOUTA or IOUTB) via the PMOS differential current switches. The switches are based on a new architecture that drastically improves distortion performance. This new switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. The analog and digital sections of the AD9763/AD97/AD9767 have separate power supply inputs (that is, AVDD and DVDD1/ DVDD) that can operate independently at 3.3 V or 5 V. The digital section, which is capable of operating up to a 15 MSPS clock rate, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1. V band gap voltage reference, and two reference control amplifiers.

22 AD9763/AD97/AD9767 The full-scale output current of each DAC is regulated by separate reference control amplifiers and can be set from ma to ma via an external network connected to the full scale adjust (FSADJ) pin. The external network, in combination with both the reference control amplifier and voltage reference (VREFIO) sets the reference current IREF, which is replicated to the segmented current sources with the proper scaling factor. The full-scale current (IOUTFS) is 3 IREF. REFERENCE OPERATION The AD9763/AD97/AD9767 contain an internal 1. V band gap reference. This can easily be overridden by a low noise external reference with no effect on performance. REFIO serves as either an input or output, depending on whether the internal or an external reference is used. To use the internal reference, simply decouple the REFIO pin to ACOM with a.1 μf capacitor. The internal reference voltage is present at REFIO. If the voltage at REFIO is used elsewhere in the circuit, an external buffer amplifier with an input bias current of less than na should be used. An example of the use of the internal reference is shown in Figure 59. ADDITIONAL EXTERNAL LOAD OPTIONAL EXTERNAL REFERENCE BUFFER.1µF I REF R SET 56Ω nf GAINCTRL 1.V REF REFIO FSADJ1/ FSADJ AVDD AD9763/ AD97/ AD9767 REFERENCE SECTION CURRENT SOURCE ARRAY Figure 59. Internal Reference Configuration ACOM An external reference can be applied to REFIO as shown in Figure 6. The external reference can provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. The.1 μf compensation capacitor is not required because the internal reference is overridden and the relatively high input impedance of REFIO minimizes any loading of the external reference. AVDD EXTERNAL REFERENCE I REF R SET 56Ω nf GAINCTRL 1.V REF REFIO FSADJ1/ FSADJ AD9763/ AD97/ AD9767 REFERENCE SECTION AVDD CURRENT SOURCE ARRAY ACOM Figure 6. External Reference Configuration Gain Control Mode Data Sheet GAIN CONTROL MODE The AD9763/AD97/AD9767 has two gain control modes, independent and master/slave. If the GAINCTRL terminal is low (connected to ground), the full-scale currents of DAC1 and DAC are set separately using two different RSET resistors. One resistor is connected to the FSADJ1 terminal, and the other resistor is connected to the FSADJ terminal. This is independent mode. If the GAINCTRL terminal is set high (connected to AVDD), the full-scale currents of DAC1 and DAC are set to the same value using one RSET resistor. In master/slave mode, full-scale current for both DAC1 and DAC is set via the FSADJ1 terminal. SETTING THE FULL-SCALE CURRENT Both of the DACs in the AD9763/AD97/AD9767 contain a control amplifier that is used to regulate the full-scale output current (IOUTFS). The control amplifier is configured as a V-I converter, as shown in Figure 59, so that its current output (IREF) is determined by the ratio of the VREFIO and an external resistor, RSET. IREF = VREFIO/RSET The DAC full-scale current, IOUTFS, is an output current 3 times larger than the reference current, IREF. IOUTFS = 3 IREF The control amplifier allows a wide (:1) adjustment span of IOUTFS from ma to ma by setting IREF between 6.5 μa and μa. The wide adjustment range of IOUTFS provides several benefits. The first relates directly to the power dissipation of the AD9763/AD97/AD9767, which is proportional to IOUTFS (refer to the Power Dissipation section). The second relates to the db adjustment, which is useful for system gain control purposes. To ensure that the AD9763/AD97/AD9767 performs properly, connect a nf capacitor and 56 Ω resistor network (shown in Figure 59 and Figure 6) from the FSADJ1 terminal to ground and from the FSADJ terminal to ground. Rev. G Page of 44

23 Data Sheet DAC TRANSFER FUNCTION Both DACs in the AD9763/AD97/AD9767 provide complementary current outputs, IOUTA and IOUTB. IOUTA provides a near full-scale current output (IOUTFS) when all bits are high (that is, DAC CODE = 4/495/16,384 for the AD9763/AD97/ AD9767, respectively), while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input code and IOUTFS. IOUTA for the AD9763, AD97, and AD9767, respectively, can be expressed as IOUTA = (DAC CODE/4) IOUTFS (1) IOUTA = (DAC CODE/496) IOUTFS IOUTA = (DAC CODE/16,384) IOUTFS IOUTB for the AD9763, AD97, and AD9767, respectively, can be expressed as IOUTB = ((3 DAC CODE)/4) IOUTFS () IOUTB = ((495 DAC CODE)/496) IOUTFS IOUTB = ((16,383 DAC CODE)/16,384) IOUTFS where DAC CODE = to 4, to 495, or to 16,384 (decimal representation). IOUTFS is a function of the reference current (IREF). This is nominally set by a reference voltage (VREFIO) and an external resistor (RSET). It can be expressed as IOUTFS = 3 IREF (3) where IREF is set as discussed in the Setting the Full-Scale Current section. The two current outputs typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads (RLOAD) that are tied to the analog common (ACOM). Note that RLOAD can represent the equivalent load resistance seen by IOUTA or IOUTB, as is the case in a doubly terminated 5 Ω or Ω cable. The singleended voltage output appearing at the IOUTA and IOUTB nodes is VOUTA = IOUTA RLOAD (5) VOUTB = IOUTB RLOAD (6) Note that the full-scale value of VOUTA and VOUTB must not exceed the specified output compliance range to maintain the specified distortion and linearity performance. VDIFF = (IOUTA IOUTB) RLOAD (7) Equation 7 highlights some of the advantages of operating the AD9763/AD97/AD9767 differentially. First, the differential operation helps cancel common-mode error sources associated with IOUTA and IOUTB such as noise, distortion, and dc offsets. Second, the differential code-dependent current and subsequent voltage, VDIFF, is twice the value of the single-ended voltage output (that is, VOUTA or VOUTB), thus providing twice the signal power to the load. AD9763/AD97/AD9767 The gain drift temperature performance for a single-ended (VOUTA and VOUTB) or differential output (VDIFF) of the AD9763/AD97/AD9767 can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship. ANALOG OUTPUTS The complementary current outputs, IOUTA and IOUTB, in each DAC can be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor (RLOAD) as described in Equation 5 through Equation 7. The differential voltage (VDIFF) existing between VOUTA and VOUTB can be converted to a single-ended voltage via a transformer or differential amplifier configuration. The ac performance of the AD9763/AD97/AD9767 is optimum and specified using a differential transformer-coupled output in which the voltage swing at IOUTA and IOUTB is limited to ±.5 V. If a single-ended unipolar output is desired, select IOUTA. The distortion and noise performance of the AD9763/AD97/ AD9767 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases. This is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load, assuming no source termination. Because the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. A properly selected transformer allows the AD9763/AD97/AD9767 to provide the required power and voltage levels to different loads. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically kω in parallel with 5 pf. It is also slightly dependent on the output voltage (that is, VOUTA and VOUTB) due to the nature of a PMOS device. As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration results in the optimum dc linearity. Note that the INL/DNL specifications for the AD9763/AD97/AD9767 are measured with IOUTA maintained at a virtual ground via an op amp. Rev. G Page 3 of 44

24 AD9763/AD97/AD9767 IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of 1. V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9763/AD97/AD9767. The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. When IOUTFS is decreased from ma to ma, the positive output compliance range degrades slightly from its nominal 1.5 V to 1. V. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed.5 V. Applications requiring the AD9763/ AD97/AD9767 output (that is, VOUTA and/or VOUTB) to extend its output compliance range must size RLOAD accordingly. Operation beyond this compliance range adversely affects the linearity performance of the AD9763/AD97/AD9767 and subsequently degrades its distortion performance. DIGITAL INPUTS The digital inputs of the AD9763/AD97/AD9767 consist of two independent channels. For the dual-port mode, each DAC has its own dedicated -/1-/14-bit data port: WRT line and CLK line. In the interleaved timing mode, the function of the digital control pins changes as described in the Interleaved Mode Timing section. The -/1-/14-bit parallel data inputs follow straight binary coding, where the most significant bits (MSBs) are DB9P1 and DB9P for the AD9763, DB11P1 and DB11P for the AD97, and DB13P1 and DB13P for the AD9767, and the least significant bits (LSBs) are DBP1 and DBP for all three parts. IOUTA produces a full-scale output current when all data bits are at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of the input code. The digital interface is implemented using an edge-triggered master/slave latch. The DAC outputs are updated following either the rising edge or every other rising edge of the clock, depending on whether dual or interleaved mode is used. The DAC outputs are designed to support a clock rate as high as 15 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulse width. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge of a 5% duty cycle clock. DAC TIMING The AD9763/AD97/AD9767 can operate in two timing modes, dual and interleaved, which are described in the following sections. The block diagram in Figure 61 represents the latch architecture in the interleaved timing mode. INTERLEAVED DATA IN, PORT 1 IQWRT IQSEL PORT 1 INPUT LATCH PORT INPUT LATCH DAC1 LATCH DAC LATCH DAC1 IQCLK IQRESET DAC Figure 61. Latch Structure in Interleaved Mode Data Sheet DEINTERLEAVED DATA OUT Dual-Port Mode Timing When the MODE pin is at Logic 1, the AD9763/AD97/AD9767 operates in dual-port mode (refer to Figure 57). The AD9763/ AD97/AD9767 functions as two distinct DACs. Each DAC has its own completely independent digital input and control lines. The AD9763/AD97/AD9767 features a double-buffered data path. Data enters the device through the channel input latches. This data is then transferred to the DAC latch in each signal path. After the data is loaded into the DAC latch, the analog output settles to its new value. For general consideration, the WRT lines control the channel input latches, and the CLK lines control the DAC latches. Both sets of latches are updated on the rising edge of their respective control signals. The rising edge of CLK must occur before or simultaneously with the rising edge of WRT. If the rising edge of CLK occurs after the rising edge of WRT, a minimum delay of ns must be maintained from the rising edge of WRT to the rising edge of CLK. Timing specifications for dual-port mode are shown in Figure 6 and Figure 63. DATA IN WRT1/WRT CLK1/CLK I OUTA OR I OUTB DATA IN WRT1/WRT CLK1/CLK I OUTA OR I OUTB t S t PD t H Figure 6. Dual-Port Mode Timing t LPW t CPW D1 D D3 D4 D5 XX D1 D Figure 63. Dual-Port Mode Timing D3 D Rev. G Page 4 of 44

25 Data Sheet Interleaved Mode Timing When the MODE pin is at Logic, the AD9763/AD97/AD9767 operate in interleaved mode (refer to Figure 61). In addition, WRT1 functions as IQWRT, CLK1 functions as IQCLK, WRT functions as IQSEL, and CLK functions as IQRESET. Data enters the device on the rising edge of IQWRT. The logic level of IQSEL steers the data to either Channel Latch 1 (IQSEL = 1) or to Channel Latch (IQSEL = ). For proper operation, IQSEL must change state only when IQWRT and IQCLK are low. When IQRESET is high, IQCLK is disabled. When IQRESET goes low, the next rising edge on IQCLK updates both DAC latches with the data present at their inputs. In the interleaved mode, IQCLK is divided by internally. Following this first rising edge, the DAC latches are only updated on every other rising edge of IQCLK. In this way, IQRESET can be used to synchronize the routing of the data to the DACs. Similar to the order of CLK and WRT in dual-port mode, IQCLK must occur before or simultaneously with IQWRT. Timing specifications for interleaved mode are shown in Figure 64 and Figure 66. The digital inputs are CMOS compatible with logic thresholds, VTHRESHOLD, set to approximately half the digital positive supply (DVDDx), or VTHRESHOLD = DVDDx/(±%) t S t H DATA IN IQSEL IQWRT IQCLK I OUTA OR I OUTB AD9763/AD97/AD9767 *APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY. Figure. 5 V Only Interleaved Mode Timing INTERLEAVED DATA IQSEL IQWRT IQCLK IQRESET t H * t S t PD t H t LPW xx D1 D D3 D4 D DATA IN IQSEL IQWRT IQCLK I OUTA OR I OUTB t H * 5 ps 5 ps *APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY. Figure V or 3.3 V Interleaved Mode Timing t PD t LPW At 5 V it is permissible to drive IQWRT and IQCLK together as shown in Figure, but at 3.3 V the interleaved data transfer is not reliable DAC OUTPUT PORT 1 DAC OUTPUT PORT xx xx D1 D Figure 66. Interleaved Mode Timing The internal digital circuitry of the AD9763/AD97/AD9767 is capable of operating at a digital supply of 3.3 V or 5 V. As a result, the digital inputs can also accommodate TTL levels when DVDD1/DVDD is set to accommodate the maximum high level voltage (VOH(MAX)) of the TTL drivers. A DVDD1/DVDD of 3.3 V typically ensures proper compatibility with bipolar TTL logic families. Figure 67 shows the equivalent digital input circuit for the data and clock inputs. The sleep mode input is similar, with the exception that it contains an active pull-down circuit, thus ensuring that the AD9763/AD97/AD9767 remains enabled if this input is left disconnected. DIGITAL INPUT DVDD1 Figure 67. Equivalent Digital Input D3 D Rev. G Page 5 of 44

26 AD9763/AD97/AD9767 Because the AD9763/AD97/AD9767 is capable of being clocked up to 15 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. Operating the AD9763/AD97/AD9767 with reduced logic swings and a corresponding digital supply (DVDD1/DVDD) results in the lowest data feedthrough and on-chip digital noise. The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the AD9763/AD97/AD9767 as well as its required minimum and maximum input logic level thresholds. Digital signal paths should be kept short, and run lengths should be matched to avoid propagation delay mismatch. The insertion of a low value (that is, Ω to Ω) resistor network between the AD9763/AD97/AD9767 digital inputs and driver outputs can be helpful in reducing any overshooting and ringing at the digital inputs that contribute to digital feedthrough. For longer board traces and high data update rates, stripline techniques with proper impedance and termination resistors should be considered to maintain clean digital inputs. The external clock driver circuitry provides the AD9763/AD97/ AD9767 with a low-jitter clock input meeting the minimum and maximum logic levels while providing fast edges. Fast clock edges help minimize jitter manifesting itself as phase noise on a reconstructed waveform. Therefore, the clock input should be driven by the fastest logic family suitable for the application. Note that the clock input can also be driven via a sine wave, which is centered around the digital threshold (that is, DVDDx/) and meets the minimum and maximum logic threshold. This typically results in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. In addition, at higher sampling rates, the % tolerance of the digital logic threshold should be considered, because it affects the effective clock duty cycle and, subsequently, cuts into the required data setup and hold times. Input Clock and Data Timing Relationship SNR in a DAC is dependent on the relationship between the position of the clock edges and the point in time at which the input data changes. The AD9763/AD97/AD9767 are rising edge triggered and therefore exhibit SNR sensitivity when the data transition is close to this edge. The goal when applying the AD9763/AD97/AD9767 is to make the data transition close to the falling clock edge. This becomes more important as the sample rate increases. Figure 68 shows the relationship of SNR to clock placement with different sample rates. Note that at the lower sample rates, much more tolerance is allowed in clock placement; much more care must be taken at higher rates. SNR (dbc) AD9763 AD97 AD9767 Data Sheet TIME OF DATA CHANGE RELATIVE TO RISING CLOCK EDGE (ns) Figure 68. SNR vs. Clock fout = MHz and fclk = 15 MSPS SLEEP MODE OPERATION The AD9763/AD97/AD9767 has a power-down function that turns off the output current and reduces the supply current to less than 8.5 ma over the specified supply range of 3.3 V to 5 V and over the full operating temperature range. This mode can be activated by applying a Logic Level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to.5 AVDD. This digital input also contains an active pull-down circuit that ensures the AD9763/AD97/AD9767 remains enabled if this input is left disconnected. The AD9763/AD97/AD9767 require less than 5 ns to power down and approximately 5 μs to power back up. POWER DISSIPATION The power dissipation (PD) of the AD9763/AD97/AD9767 is dependent on several factors, including the power supply voltages (AVDD and DVDD1/DVDD) the full-scale current output (IOUTFS) the update rate (fclk) the reconstructed digital input waveform The power dissipation is directly proportional to the analog supply current (IAVDD) and the digital supply current (IDVDD). IAVDD is directly proportional to IOUTFS, as shown in Figure 69, and is insensitive to fclk. Conversely, IDVDD is dependent on the digital input waveform, the fclk, and the digital supply (DVDD1/DVDD). Figure and Figure 71 show IDVDD as a function of full-scale sine wave output ratios (fout/fclk) for various update rates with DVDD1 = DVDD = 5 V and DVDD1 = DVDD = 3.3 V, respectively. Note that IDVDD is reduced by more than a factor of when DVDD1/DVDD is reduced from 5 V to 3.3 V Rev. G Page 6 of 44