+2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs

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1 9-565; Rev ; / to +5.5, Low-Power, Dual, Parallel General Description The MAX5 parallel-input, voltage-output, dual 8-bit digital-to-analog converter (DAC) operates from a single +.7 to +5.5 supply and comes in a space-saving 6-pin TSSOP package. Internal precision buffers swing Rail-to-Rail, and the reference input range includes both ground and the positive rail. Both DACs share a common reference input. The MAX5 has separate input latches for each of its DACs. Data is traferred to the input latches from a common 8-bit input port. The DACs are individually selected through address input A and are updated by bringing WR low. The MAX5 features a shutdown mode that reduces current to na, as well as a power-on reset mode that resets all registers to code hex on power-up. Features +.7 to +5.5 Single-Supply Operation Ultra-Low Supply Current.mA while Operating na in Shutdown Mode Ultra-Small 6-Pin TSSOP Package Ground to DD Reference Input Range Output Buffer Amplifiers Swing Rail-to-Rail Power-On Reset Sets All Registers to Zero Ordering Information MAX5 Applicatio PART TEMP. RANGE PIN-PACKAGE INL (LSB) Digital Gain and Offset Adjustment Programmable Attenuators MAX5AEUE MAX5BEUE -4 C to +85 C -4 C to +85 C 6 TSSOP 6 TSSOP ± ± Portable Itruments Power-Amp Bias Control Functional Diagram Pin Configuration TOP IEW INPUT LATCH A DAC A OUTA DD REF 6 5 OUTA OUTB D D7 SHDN 3 4 GND INPUT LATCH B DAC B OUTB WR D7 4 5 MAX5 3 A D D6 6 D A CONTROL LOGIC WR REF SHDN MAX5 D5 D4 7 8 TSSOP 9 D D3 Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. Maxim Integrated Products For free samples & the latest literature: or phone For small orders, phone

2 +.7 to +5.5, Low-Power, Dual, Parallel MAX5 ABSOLUTE MAXIMUM RATINGS DD to GND to +6 D_, A, WR, SHDN to GND to +6 REF to GND to ( DD +.3) OUT_ to GND to DD Maximum Current into Any Pin...±5mA Continuous Power Dissipation (T A = +7 C) 6-Pin TSSOP (derate 5.7mW/ C above +7 C)...457mW Operating Temperature Range MAX5_EUE...-4 C to +85 C Maximum Junction Temperature...+5 C Storage Temperature Range C to +5 C Lead Temperature (soldering, sec)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ( DD = REF = +.7 to +5.5, GND =, R L = kω, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values are at DD = REF = +3 and T A = +5 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY Resolution 8 Bits Integral Nonlinearity (Note ) INL MAX5A MAX5B ± ± LSB Differential Nonlinearity (Note ) DNL Guaranteed monotonic ± LSB Zero-Code Error ZCE Code = hex ± m Zero-Code-Error Supply Rejection Code = hex, DD =.7 to 5.5 m Zero-Code Temperature Coefficient Code = hex ± µ/ C Gain Error (Note ) Code = F hex ± % Gain-Error Temperature Coefficient Code = F hex ±. LSB/ C Power-Supply Rejection Code = FF hex Code = FF hex DD =.7 to 3.6, REF =.5 DD = 4.5 to 5.5, REF = 4.96 LSB REFERENCE INPUT Input oltage Range DD Input Resistance kω Input Capacitance 5 pf DAC OUTPUTS Output oltage Range R L = REF DIGITAL INPUTS Input High oltage IH DD =.7 to 3.6 DD = 3.6 to Input Low oltage IL.8 Input Current I IN IN = DD or GND ±. µa Input Capacitance C IN pf

3 +.7 to +5.5, Low-Power, Dual, Parallel ELECTRICAL CHARACTERISTICS (continued) ( DD = REF = +.7 to +5.5, GND =, R L = kω, C L = pf, T A = T MIN to T MAX, unless otherwise noted. Typical values are at DD = REF = +3 and T A = +5 C.) PARAMETER DYNAMIC PERFORMANCE Output oltage Slew Rate Output Settling Time (Note 3) Channel-to-Channel Isolation (Note 4) SYMBOL CONDITIONS From code to code F hex To /LSB, from code to code F hex Code to code FF hex MIN TYP MAX UNITS /µs µs MAX5 Digital Feedthrough (Note 5) Code to code FF hex.5 Digital-to-Analog Glitch Impulse Code 8 hex to code 7F hex 9 Signal-to-Noise plus Distortion Ratio SINAD REF =.5p-p at khz, REF(DC) =.5, DD = 3, code FF hex REF =.5p-p at khz, REF(DC) =.5, DD = 3, code FF hex 7 6 db Multiplying Bandwidth REF =.5p-p, REF(DC) =.5, DD = 3, -3dB bandwidth 65 khz Wideband Amplifier Noise 6 µ RMS Shutdown Recovery Time t SDR To ±/LSB of final value of OUT 3 µs Time to Shutdown t SDN I DD < 5µA µs POWER SUPPLIES Power-Supply oltage DD Supply Current (Note 6) I DD 9 36 µa Shutdown Current. µa DIGITAL TIMING (Figure ) (Note 7) Address to WR Setup t AS 5 Address to WR Hold t AH Data to WR Setup t DS 5 Data to WR Hold t DH WR Pulse Width t WR Note : Reduced digital code range (code hex to code F hex) due to swing limitatio when the output amplifier is loaded. Note : Gain error is: [ ( F,meas - ZCE - F,ideal ) / REF ]. Where F,meas is the DAC output voltage with input code F hex, and F,ideal is the ideal DAC output voltage with input code F hex (i.e., REF 4 / 56). Note 3: Output settling time is measured from the 5% point of the falling edge of WR to ±/LSB of OUT s final value. Note 4: Channel-to-channel isolation is defined as the glitch energy at a DAC output in respoe to a full-scale step change on any other DAC output. The measured channel has a fixed code of 8 hex. Note 5: Digital feedthrough is defined as the glitch energy at any DAC output in respoe to a full-scale step change on all eight data inputs with WR at DD. Note 6: R L =, digital inputs at GND or DD. Note 7: Timing measurement reference level is ( IH + IL ) /. 3

4 +.7 to +5.5, Low-Power, Dual, Parallel MAX5 ADDRESS WR t AS ADDRESS ALID t WR t DS- t AHt DH- DATA DATA ALID Figure. Timing Diagram Typical Operating Characteristics ( DD = REF = +3, R L = kω, C L = pf, code = FF hex, T A = +5 C, unless otherwise noted.) OUT () DAC ZERO-CODE OUTPUT OLTAGE vs. SINK CURRENT DD = REF = 3 DD = REF = 5 MAX5 toc OUT () DAC FULL-SCALE OUTPUT OLTAGE vs. SOURCE CURRENT DD = REF = 3 DD = REF = 5 MAX5 toc SUPPLY CURRENT (µa) SUPPLY CURRENT vs. TEMPERATURE DAC AT CODE OR F DAC AT CODE (R L = ) DD = 5; CODE = F HEX DD = 3; CODE = F HEX DD = 5; CODE = MAX5 toc SINK CURRENT (ma) SOURCE CURRENT (ma) DD = 3; CODE = DD = TEMPERATURE ( C) SUPPLY CURRENT (µa) SUPPLY CURRENT vs. REFERENCE OLTAGE DAC AT CODE OR F DAC AT CODE (R L = ) CODE = F HEX DD = 3. CODE = HEX REFERENCE OLTAGE () MAX5 toc4 SUPPLY CURRENT (µa) SUPPLY CURRENT vs. REFERENCE OLTAGE CODE = F HEX DD = 5. DAC AT CODE OR F DAC AT CODE. (R L = ) CODE = HEX REFERENCE OLTAGE () MAX5 toc5 THD + NOISE (db) TOTAL HARMONIC DISTORTION PLUS NOISE AT DAC OUTPUT vs. REFERENCE AMPLITUDE DAC CODE = FF HEX REF = SINE WAE CENTERED AT.5 8kHz FILTER khz REF SIGNAL khz REF SIGNAL khz REF SIGNAL REFERENCE AMPLITUDE ( p-p ) MAX5 toc6 4

5 +.7 to +5.5, Low-Power, Dual, Parallel THD + NOISE (db) TOTAL HARMONIC DISTORTION PLUS NOISE AT DAC OUTPUT vs. REFERENCE FREQUENCY DAC CODE = FF HEX REF = SINE WAE CENTERED AT.5 khz FREQUENCY 5kHz FILTER REF =.5 p-p REF = p-p REF = p-p FREQUENCY (khz) WORST-CASE LSB DIGITAL STEP CHANGE (POSITIE) MAX5 toc7 OUTPUT AMPLITUDE (db) Typical Operating Characteristics (continued) ( DD = REF = +3, R L = kω, C L = pf, code = FF hex, T A = +5 C, unless otherwise noted.) REFERENCE INPUT FREQUENCY RESPONSE CODE = FF HEX REF IS I p-p SIGNAL REF =.5.. FREQUENCY (MHz) DIGITAL FEEDTHROUGH GLITCH IMPULSE ( TO DIGITAL TRANSITION) MAX5 toc8 WORST-CASE LSB DIGITAL STEP CHANGE (NEGATIE) DAC CODE FROM 8 TO 7F HEX µs/div CH = WR, /div, CH = OUTA, 5m/div, AC-COUPLED DIGITAL FEEDTHROUGH GLITCH IMPULSE ( TO DIGITAL TRANSITION) MAX55 toc9 MAX5 DAC CODE FROM 7F TO 8 HEX MAX55 toc TO DIGITAL TRANSITION ON ALL DATA BITS (WITH WR HIGH) MAX55 toc TO DIGITAL TRANSITION ON ALL DATA BITS (WITH WR HIGH) MAX55 toc µs/div CH = WR, /div, CH = OUTA, 5m/div, AC-COUPLED /div CH = D7, /div, CH = OUTA, m/div /div CH = D7, /div, CH = OUTA, m/div POSITIE SETTLING TIME DAC CODE FROM TO F HEX MAX55 toc3 NEGATIE SETTLING TIME DAC CODE FROM F TO HEX MAX55 toc INTEGRAL AND DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE R L = MAX5 toc5 INL/DNL (LSB).. -. DNL INL -.4 µs/div µs/div CH = WR = /div, CH = OUTA = /div CH = WR, /div, CH = OUTA, /div DIGITAL CODE 5

6 +.7 to +5.5, Low-Power, Dual, Parallel MAX5 PIN 3 4 NAME DD REF SHDN WR FUNCTION Positive Supply oltage. Bypass DD to GND using a.µf capacitor. Reference oltage Input Shutdown. Connect SHDN to GND for normal operation. Write Input (active low). Use WR to load data into the DAC input latch selected by A. Pin Description 5 D7 D Data Inputs 3 A DAC Address Select Bit 4 GND Ground 5 OUTB DAC B oltage Output 6 OUTA DAC A oltage Output Detailed Description Digital-to-Analog Section The MAX5 uses a matrix decoding architecture for the DACs. The external reference voltage is divided down by a resistor string placed in a matrix fashion. Row and column decoders select the appropriate tab from the resistor string to provide the needed analog voltages. The resistor network converts the 8-bit digital input into an equivalent analog output voltage in proportion to the applied reference voltage input. The resistor string presents a codeindependent input impedance to the reference and guarantees a monotonic output. These devices can be used in multiplying applicatio. Their voltages are buffered by rail-to-rail op amps connected in a follower configuration to provide a rail-to-rail output (see Functional Diagram). Low-Power Shutdown Mode The MAX5 features a shutdown mode that reduces current coumption to na. A high voltage on the SHDN pin shuts down the DACs and the output amplifiers. In shutdown mode, the output amplifiers enter a high-impedance state. When bringing the device out of shutdown, allow 3µs for the output to stabilize. Output Buffer Amplifiers The DAC outputs are internally buffered by precision amplifiers with a typical slew rate of.6/µs. The typical settling time to ±/LSB at the output is 6µs when loaded with kω in parallel with pf. Reference Input The MAX5 provides a code-independent input impedance on the REF input. Input impedance is typically 46kΩ in parallel with 5pF, and the reference input voltage range is to DD. The reference input accepts positive DC signals, as well as AC signals with peak values between and DD. The voltage at REF sets the full-scale output voltage for the DAC. The output voltage ( OUT ) for any DAC is represented by a digitally programmable voltage source as follows: OUT = (N B REF ) / 56 where N B is the numeric value of the DAC binary input code. Digital Inputs and Interface Logic In the MAX5, address line A selects the DAC that receives data from D D7, as shown in Table. When WR is low, the addressed DAC s input latch is traparent. Data is latched when WR is high. The DAC outputs (OUTA, OUTB) represent the data held in the two 8-bit Table. MAX5 Addressing Table (partial list) WR A LATCH STATE H X Input data latched L L DAC A input latch traparent L H DAC B input latch traparent H = High state, L = Low state, X = Don t care 6

7 +.7 to +5.5, Low-Power, Dual, Parallel input latches. To avoid output glitches in the MAX5, eure that data is valid before WR goes low. When the device powers up (i.e., DD ramps up), all latches are internally preset with code hex. Applicatio Information External Reference The reference source resistance must be coiderably less than the reference input resistance. To keep within LSB error in an 8-bit system, R S must be less than R REF /56. Hence, maintain a value of R S < kω to eure 8-bit accuracy. If REF is DC only, bypass REF to GND with a.µf capacitor. alues greater than this improve noise rejection. Power Sequencing The voltage applied to REF should not exceed DD at any time. If proper power sequencing is not possible, connect an external Schottky diode between REF and DD to eure compliance with the absolute maximum ratings. Do not apply signals to the digital inputs before the device is fully powered up. Power-Supply Bypassing and Ground Management Digital or AC traient signals on GND can create noise at the analog output. Return GND to the highest-quality ground available. Bypass DD with a.µf capacitor, located as close to DD and GND as possible. Careful PC board ground layout minimizes crosstalk between the DAC outputs and digital inputs. Chip Information TRANSISTOR COUNT: 6848 MAX5 7

8 +.7 to +5.5, Low-Power, Dual, Parallel MAX5 Package Information TSSOP.EPS Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. 8 Maxim Integrated Products, San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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