270 MHz, 400 μa Current Feedback Amplifier AD8005

Transcription

1 Data Sheet 27 MHz, μa Current Feedback Amplifier AD85 FEATURES Ultralow power μa power supply current ( mw on ±5 VS) Specified for single supply operation High speed 27 MHz, 3 db bandwidth (G = +) 7 MHz, 3 db bandwidth () 28 V/μs slew rate () 28 ns settling time to.%, 2 V step () Low distortion/noise 63 dbc at MHz, VO = 2 V p-p 5 dbc at MHz, VO = 2 V p-p. nv/ Hz input voltage noise at MHz Good video specifications (RL = kω, ) Gain flatness. db to 3 MHz.% differential gain error. differential phase error APPLICATIONS Signal conditioning A/D buffer Power sensitive, high speed systems Battery powered equipment Loop/remote power systems Communication or video test systems Portable medical instruments GENERAL DESCRIPTION The AD85 is an ultralow power, high speed amplifier with a wide signal bandwidth of 7 MHz and slew rate of 28 V/μs. This performance is achieved while consuming only μa of quiescent supply current. These features increase the operating time of high speed battery powered systems without reducing dynamic performance. The current feedback design results in gain flatness of. db to 3 MHz while offering differential gain and phase errors of.% and.. Harmonic distortion is low over a wide bandwidth with THDs of 63 dbc at MHz and 5 dbc at MHz. Ideal features for a signal conditioning amplifier or buffer to a high speed A-to-D converter in portable video, medical or communication systems. The AD85 is characterized for +5 V and ±5 V supplies and operates over the industrial temperature range of C to +85 C. The amplifier is supplied in 8-lead PDIP, 8-lead SOIC_N, and 5-lead SOT-23 packages. NORMALIZED GAIN (db) DISTORTION (dbc) FUNCTIONAL BLOCK DIAGRAMS NC IN 2 +IN 3 V S AD85 8 NC 7 +V S 6 OUT 5 NC TOP VIEW (Not to Scale) NC = NO CONNECT Figure. 8-Lead PDIP and SOIC_N OUT V S 2 +IN 3 AD85 +V S TOP VIEW (Not to Scale) Figure 2. 5-Lead SOT Figure 3. Frequency Response; G = ±2, VS = +5 V or ±5 V V OUT = 2mV p-p V OUT = 2V p-p Figure. Distortion vs. Frequency; VS = ±5 V 5 IN 26-3 THIRD HARMONIC SECOND HARMONIC 26-2 V S = +5V Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 AD85 TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagrams... Revision History... 2 Specifications... 3 ±5 V Supplies V Supply... Absolute Maximum Ratings... 5 Thermal Resistance... 5 Maximum Power Dissipation... 5 Data Sheet ESD Caution...5 Typical Performance Characteristics...6 Applications... Driving Capacitive Loads... Single-Supply Level Shifter... Single-Ended-to-Differential Conversion... Layout Considerations... Increasing Feedback Resistors... Outline Dimensions... 2 Ordering Guide... 3 REVISION HISTORY 3/ Rev. A to Rev. B Updated Format... Universal Deleted Operating Temperature Range Parameter, Table... 3 Changes to Table Change to Figure... 6 Changes to Ordering Guide /99 Rev. to Rev. A Rev. B Page 2 of 6

3 Data Sheet AD85 SPECIFICATIONS ±5 V SUPPLIES At TA = +25 C, VS = ±5 V, RL = kω, unless otherwise noted. Table. Parameter Conditions Min Typ Max Units DYNAMIC PERFORMANCE RF = 3. kω for N-8 Package or RF = 2.9 kω for R-8 Package or RF = 2. kω for RJ-5 Package 3 db Small Signal Bandwidth G = +, VO =.2 V p-p MHz, VO =.2 V p-p 7 MHz Bandwidth for. db Flatness, VO =.2 V p-p 3 MHz Large Signal Bandwidth G = +, VO = V p-p, RF = 99 Ω MHz Slew Rate (Rising Edge), VO = V Step 28 V/µs G =, VO = V Step, RF =.5 kω 5 V/µs Settling Time to.%, VO = 2 V Step 28 ns DISTORTION/NOISE PERFORMANCE RF = 3. kω for N-8 Package or RF = 2.9 kω for R-8 Package or RF = 2. kω for RJ-5 Package Total Harmonic Distortion fc = MHz, VO = 2 V p-p, 63 dbc fc = MHz, VO = 2 V p-p, 5 dbc Differential Gain NTSC,. % Differential Phase NTSC,. Degrees Input Voltage Noise f = MHz. nv/ Hz Input Current Noise f = MHz, +IIN. pa/ Hz IIN 9. pa/ Hz DC PERFORMANCE Input Offset Voltage 5 3 ±mv TMIN to TMAX 5 ±mv Offset Drift µv/ C +Input Bias Current.5 ±µa TMIN to TMAX 2 ±µa Input Bias Current 5 ±µa TMIN to TMAX 2 ±µa Input Bias Current Drift (±) 6 na/ C Open-Loop Transimpedance kω INPUT CHARACTERISTICS Input Resistance +Input 9 MΩ Input 26 Ω Input Capacitance +Input.6 pf Input Common-Mode Voltage Range 3.8 ±V Common-Mode Rejection Ratio VCM = ±2.5 V 6 5 db OUTPUT CHARACTERISTICS Output Voltage Swing Positive V Negative V Output Current RL = 5 Ω ma Short Circuit Current 6 ma POWER SUPPLY Quiescent Current 75 µa TMIN to TMAX 56 µa Power Supply Rejection Ratio VS = ± V to ±6 V db Rev. B Page 3 of 6

4 AD85 Data Sheet +5 V SUPPLY At TA = +25 C, VS = +5 V, R L = kω to 2.5 V, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Units DYNAMIC PERFORMANCE RF = 3. kω for N-8 Package or RF = 2.9 kω for R-8 Package or RF = 2. kω for RJ-5 Package 3 db Small Signal Bandwidth G = +, VO =.2 V p-p MHz, VO =.2 V p-p 3 MHz Bandwidth for. db Flatness, VO =.2 V p-p 3 MHz Large Signal Bandwidth G = +, VO = V p-p, RF = 99 Ω 5 MHz Slew Rate (Rising Edge), VO = V Step 26 V/µs G =, VO = V Step, RF =.5 kω 775 V/µs Settling Time to.%, VO = 2 V Step 3 ns DISTORTION/NOISE PERFORMANCE RF = 3. kω for N-8 Package or RF = 2.9 kω for R-8 Package or RF = 2. kω for RJ-5 Package Total Harmonic Distortion fc = MHz, VO = 2 V p-p, 6 dbc fc = MHz, VO = 2 V p-p, 5 dbc Differential Gain NTSC,. % Differential Phase NTSC,.7 Degrees Input Voltage Noise f = MHz. nv/ Hz Input Current Noise f = MHz, +IIN. pa/ Hz IIN 9. pa/ Hz DC PERFORMANCE Input Offset Voltage 5 35 ±mv TMIN to TMAX 5 ±mv Offset Drift µv/ C +Input Bias Current.5 ±µa TMIN to TMAX 2 ±µa Input Bias Current 5 ±µa TMIN to TMAX ±µa Input Bias Current Drift (±) 8 na/ C Open-Loop Transimpedance 5 5 kω INPUT CHARACTERISTICS Input Resistance +Input 2 MΩ Input 3 Ω Input Capacitance +Input.6 pf Input Common-Mode Voltage Range.5 to 3.5 V Common-Mode Rejection Ratio VCM =.5 V to 3.5 V 8 5 db OUTPUT CHARACTERISTICS Output Voltage Swing. to to.5 V Output Current RL = 5 Ω ma Short Circuit Current 3 ma POWER SUPPLY Quiescent Current µa TMIN to TMAX 7 µa Power Supply Rejection Ratio VS = + V to +6 V db OPERATING TEMPERATURE RANGE +85 C Rev. B Page of 6

5 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Internal Power Dissipation PDIP Package (N-8) SOIC_N (R-8) SOT-23 Package (RJ-5) Input Voltage (Common Mode) Differential Input Voltage Output Short Circuit Duration Storage Temperature Range Operating Temperature Range Lead Temperature Range (Soldering sec) See Table. Rating 2.6 V.3 Watts.75 Watts.5 Watts ±VS ± V ±3.5 V Observe Power Derating Curves 65 C to +25 C C to +85 C +3 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for device in free air. Table. Thermal Resistance Package Type θja Unit 8-Lead PDIP Package 9 C/W 8-Lead SOIC_N Package 55 C/W 5-Lead SOT-23 Package 2 C/W AD85 MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD85 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +5 C. Exceeding this limit temporarily causes a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +75 C for an extended period can result in device failure. While the AD85 is internally short circuit protected, this is not sufficient to guarantee that the maximum junction temperature (+5 C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 5. MAXIMUM POWER DISSIPATION (W) AMBIENT TEMPERATURE ( C) Figure 5. Maximum Power Dissipation vs. Temperature ESD CAUTION 8-LEAD SOIC_N PACKAGES 5-LEAD SOT-23 PACKAGE 8-LEAD PDIP PACKAGE T J = 5 C 26-5 Rev. B Page 5 of 6

6 AD85 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 5 3 V OUT = 2mV p-p G = V OUT = 2mV p-p NORMALIZED GAIN (db) G = + R F = 99Ω NORMALIZED GAIN (db) G = R F = kω G = R F =.5kΩ Figure 6. Frequency Response; G = +, +2, +; VS = ±5 V Figure 9. Frequency Response; G =, ; VS = ±5 V V OUT = 2mV p-p 2 PHASE GAIN (db) GAIN (db) 8 6 GAIN PHASE (Degrees) k k k M M FREQUENCY (Hz) M 28 G 26- Figure 7. Gain Flatness; ; VS = ±5 V or +5 V Figure. Transimpedance Gain and Phase vs. Frequency GAIN (db) V OUT = V p-p V OUT = 2V p-p PEAK-TO-PEAK OUTPUT VOLTAGE; % THD (V) Figure 8. Large Signal Frequency Response;, RL = kω Figure. Output Swing vs. Frequency; VS = ±5 V Rev. B Page 6 of 6

7 Data Sheet AD85 5 V OUT = 2V p-p THIRD HARMONIC 5 V OUT = 2V p-p THIRD HARMONIC DISTORTION (dbc) SECOND HARMONIC DISTORTION (dbc) SECOND HARMONIC Figure 2. Distortion vs. Frequency; VS = ±5 V Figure 5. Distortion vs. Frequency VS = +5 V DIFFERENTIAL GAIN (%)..5.5 MIN =.6 MAX =.3 p-p/max =.9 DIFFERENTIAL GAIN (%)..5.5 MIN =.8 MAX =. p-p/max =.2 V S = +5V TO +.5V...6 MIN =. MAX =.39 p-p =.. MIN =. MAX =.7 p-p =.7 DIFFERENTIAL PHASE (Degrees) ST 2 ND 3 RD TH 5 TH 6 TH 7 TH 8 TH 9 TH TH TH MODULATING RAMP LEVEL (IRE) 26-3 DIFFERENTIAL PHASE (Degrees).5.5. ST 2 ND 3 RD TH 5 TH 6 TH 7 TH 8 TH 9 TH TH TH MODULATING RAMP LEVEL (IRE) V S = +5V TO +.5V 26-6 Figure 3. Differential Gain and Phase, VS = ±5 V Figure 6. Differential Gain and Phase, VS = +5 V SWING (V p-p) V S = +5V PEAK-TO-PEAK OUTPUT 5MHz;.5% THD (V) f = 5MHz k k LOAD RESISTANCE (Ω) TOTAL SUPPLY VOLTAGES (V) 26-7 Figure. Output Voltage Swing vs. Load Figure 7. Output Swing vs. Supply Rev. B Page 7 of 6

8 AD85 Data Sheet CMRR (db) V S = +5V OR ±5V INPUT VOLTAGE NOISE (nv/ Hz) k k k M FREQUENCY (Hz) M 26-2 Figure 8. CMRR vs. Frequency; VS = +5 V or ±5 V Figure 2. Noise vs. Frequency; VS = +5 V or ±5 V OUTPUT RESISTANCE (Ω) V S = +5V OR ±5V V S = +5V INPUT CURRENT NOISE (pa/ Hz) INVERTING CURRENT NONINVERTING CURRENT k k k M M FREQUENCY (Hz) Figure 9. Output Resistance vs. Frequency; VS = ±5 V and +5 V Figure 22. Noise vs. Frequency; VS = +5 V or ±5 V V S = +5V OR ±5V PSRR 2 +PSRR 9 V OUT V IN PSRR (db) 3 5 G = % V 2V 5ns Figure 2. PSRR vs. Frequency; VS = +5 V or ±5 V Figure 23. ±Overdrive Recovery, VS = ±5 V, VIN = 2 V Step Rev. B Page 8 of 6

9 Data Sheet AD85 R G R F C PROBE R L kω V OUT.5kΩ V IN 5.Ω.5kΩ C PROBE R L kω V OUT V IN 5Ω.µF µf +V S.µF µf +V S.µF µf.µf µf PROBE: TEK P637 C LOAD = pf NOMINAL V S 26-2 PROBE: TEK P637 C LOAD = pf NOMINAL V S Figure 2. Test Circuit; ; RF = RG = 3. kω for N-8 Package; RF = RG = 2.9 kω for R-8 and RJ-5 Packages Figure 27. Test Circuit; G =, RF = RG =.5 kω for N-8, R-8, and RJ-5 Packages 9 9 % % 5mV ns mV ns Figure mv Step Response;, VS = ±2.5 V or ±5 V Figure mv Step Response; G =, VS = ±2.5 V or ±5 V 9 9 % % V ns V ns Figure 26. Step Response;, VS = ±5 V Figure 29. Step Response; G =, VS = ±5 V Rev. B Page 9 of 6

10 AD85 APPLICATIONS DRIVING CAPACITIVE LOADS Capacitive loads interact with the output impedance of an op amp to create an extra delay in the feedback path. This reduces circuit stability and can cause unwanted ringing and oscillation. A given value of capacitance causes much less ringing when the amplifier is used with a higher noise gain. The capacitive load drive of the AD85 can be increased by adding a low valued resistor in series with the capacitive load. Introducing a series resistor tends to isolate the capacitive load from the feedback loop, thereby diminishing its influence. Figure 3 shows the effects of a series resistor on capacitive drive for varying voltage gains. As the closed-loop gain is increased, the larger phase margin allows for larger capacitive loads with less overshoot. Adding a series resistor at lower closed-loop gains accomplishes the same effect. For large capacitive loads, the frequency response of the amplifier is dominated by the roll-off of the series resistor and capacitive load. CAPACITIVE LOAD (pf) R G R F AD85 R S RL kω Figure 3. Driving Capacitive Loads 2V OUTPUT STEP WITH 3% OVERSHOOT R S = Ω R S = 5Ω R S = Ω CLOSED-LOOP GAIN (V/V) Figure 3. Capacitive Load Drive vs. Closed-Loop Gain SINGLE-SUPPLY LEVEL SHIFTER In addition to providing buffering, many systems require that an op amp provide level shifting. A common example is the level shifting required to move a bipolar signal into the unipolar range of many modern analog-to-digital converters (ADCs). In general, single supply ADCs have input ranges that are referenced neither to ground nor supply. Instead the reference level is some point in between, usually halfway between ground and supply (+2.5 V for a single supply 5 V ADC). Because high-speed ADCs typically have input voltage ranges of V to 2 V, the op amp driving it must be single supply but not necessarily rail-to-rail. C L V IN R.5kΩ V REF 5V R3 3.kΩ R kω.µf 5V AD85 R2.5kΩ.µF µf Figure 32. Bipolar to Unipolar Shift Lever Data Sheet V OUT Figure 32 shows a level shifter circuit that can move a bipolar signal into a unipolar range. A positive reference voltage, derived from the +5 V supply, sets a bias level of +.25 V at the noninverting terminal of the op amp. In ac applications, the accuracy of this voltage level is not important; however, noise is a serious consideration. A. mf capacitor provides useful decoupling of this noise. The bias level on the noninverting terminal sets the input commonmode voltage to +.25 V. Because the output is always positive, the op amp can be powered with a single +5 V power supply. The overall gain function is given by the equation: R R R V 2 OUT V IN 2 = + + VREF R R3 + R R In the above example, the equation simplifies to VOUT = VIN V SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION Many single supply ADCs have differential inputs. In such cases, the ideal common-mode operating point is usually halfway between supply and ground. Figure 33 shows how to convert a single-ended bipolar signal into a differential signal with a common-mode level of 2.5 V. BIPOLAR SIGNAL ±.5V 2.9kΩ.µF 2.9kΩ 2.9kΩ 2.9kΩ +5V +5V R IN kω.µf +5V.µF AD85 R G 69Ω R F 3.9kΩ +5V.µF AD85 R F 2.9kΩ Figure 33. Single-Ended-to-Differential Converter V OUT Rev. B Page of 6

11 Data Sheet Amp has its +input driven with the ac-coupled input signal while the +input of Amp 2 is connected to a bias level of +2.5 V. Thus the input of Amp 2 is driven to virtual +2.5 V by its output. Therefore, Amp is configured for a noninverting gain of five, ( + RF/RG), because RG is connected to the virtual +2.5 V of the input of Amp 2. When the +input of Amp is driven with a signal, the same signal appears at the input of Amp. This signal serves as an input to Amp 2 configured for a gain of 5, ( RF2/RG). Thus the two outputs move in opposite directions with the same gain and create a balanced differential signal. This circuit can be simplified to create a bipolar in/bipolar out single-ended to differential converter. Obviously, a single supply is no longer adequate and the VS pins must now be powered with 5 V. The +input to Amp 2 is tied to ground. The ac coupling on the +input of Amp is removed and the signal can be fed directly into Amp. LAYOUT CONSIDERATIONS In order to achieve the specified high-speed performance of the AD85, the user must be attentive to board layout and component selection. Proper RF design techniques and selection of components with low parasitics are necessary. The printed circuit board (PCB) must have a ground plane that covers all unused portions of the component side of the board. This provides a low impedance path for signals flowing to ground. Remove the ground plane from the area under and around the chip (leave about 2 mm between the pin contacts and the ground plane). This helps to reduce stray capacitance. If both signal tracks and the ground plane are on the same side of the PCB, also leave a 2 mm gap between ground plane and track. V IN R T R G R F R O V OUT AD85 one end of the capacitor is within /8 inch of each power pin with the other end connected to the ground plane. An additional large (.7 µf µf) tantalum electrolytic capacitor must also be connected in parallel. This capacitor supplies current for fast, large signal changes at the output. It must not necessarily be as close to the power pin as the smaller capacitor. Locate the feedback resistor close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance variations of less than.5 pf at the inverting input significantly affect high-speed performance. Use stripline design techniques for long signal traces (that is, greater than about inch). Striplines must have a characteristic impedance of either 5 Ω or 75 Ω. For the stripline to be effective, correct termination at both ends of the line is necessary. Table 5. Typical Bandwidth vs. Gain Setting Resistors Small Signal 3 db BW Gain RF RG RT (MHz), VS = ±5 V.9 kω.9 kω MHz kω Ω Ω 6 MHz kω 9.9 Ω 27 MHz kω 2.9 kω 9.9 Ω 7 MHz + 99 Ω 56.2 Ω 9.9 Ω MHz INCREASING FEEDBACK RESISTORS Unlike conventional voltage feedback op amps, the choice of feedback resistor has a direct impact on the closed-loop bandwidth and stability of a current feedback op amp circuit. Reducing the resistance below the recommended value makes the amplifier more unstable. Increasing the size of the feedback resistor reduces the closed-loop bandwidth. 562Ω 36µA (rms).99kω +5V V IN R G R T C.µF C2.µF C3 µf C µf INVERTING CONFIGURATION R F C.µF C2.µF C3 µf C µf Figure 3. Inverting and Nonconverting Configurations Chip capacitors have low parasitic resistance and inductance and are suitable for supply bypassing (see Figure 3). Make sure that R O NONINVERTING CONFIGURATION +V S V S V OUT +V S V S 26-3 V AD85 OUT 2V (rms) V IN.2V (rms) QUIESCENT CURRENT 75µA (MAX) 5V Figure 35. Saving Power by Increasing Feedback Resistor Network In power-critical applications where some bandwidth can be sacrificed, increasing the size of the feedback resistor yields significant power savings. A good example of this is the gain of + case. Operating from a bipolar supply (±5 V), the quiescent current is 75 µa (excluding the feedback network). The recommended feedback and gain resistors are 99 Ω and 56.2 Ω respectively. In order to drive an rms output voltage of 2 V, the output must deliver a current of 3.6 ma to the feedback network. Increasing the size of the resistor network by a factor of, as shown in Figure 35, reduces this current to 36 µa; however, the closed loop bandwidth decreases to 2 MHz Rev. B Page of 6

12 AD85 Data Sheet OUTLINE DIMENSIONS. (.6).365 (9.27).355 (9.2).2 (5.33) MAX.5 (3.8).3 (3.3).5 (2.92).22 (.56).8 (.6). (.36) 8. (2.5) BSC 5.28 (7.).25 (6.35).2 (6.).5 (.38) MIN SEATING PLANE.5 (.3) MIN.6 (.52) MAX.5 (.38) GAUGE PLANE.325 (8.26).3 (7.87).3 (7.62).3 (.92) MAX.95 (.95).3 (3.3).5 (2.92). (.36). (.25).8 (.2).7 (.78).6 (.52).5 (.) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 766-A 5. (.968).8 (.89). (.57) 3.8 (.97) (.2) 5.8 (.228).25 (.98). (.) COPLANARITY. SEATING PLANE.27 (.5) BSC.75 (.688).35 (.532).5 (.2).3 (.22) 8.25 (.98).7 (.67).5 (.96).25 (.99).27 (.5). (.57) 5 COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 27-A Rev. B Page 2 of 6

13 Data Sheet AD BSC.95 BSC MAX.5 MIN.5 MAX.35 MIN.5 MAX.95 MIN SEATING PLANE.2 MAX.8 MIN 5.6 BSC COMPLIANT TO JEDEC STANDARDS MO-78-AA --2-A Figure Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding Code AD85ANZ C to +85 C 8-Lead Plastic Dual In-Line Package [PDIP] N-8 AD85ARZ C to +85 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD85ARZ-REEL C to +85 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD85ARZ-REEL7 C to +85 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD85ARTZ-R2 C to +85 C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 H5 AD85ARTZ-REEL7 C to +85 C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 H5 AD85AR-EBZ Evaluation Board AD85ART-EBZ Evaluation Board Z = RoHS Compliant Part. Rev. B Page 3 of 6

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15 Data Sheet AD85 NOTES Rev. B Page 5 of 6

16 AD85 Data Sheet NOTES Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D26--3/(B) Rev. B Page 6 of 6