Dual 8-Bit, 60 MSPS A/D Converter AD9059

Transcription

1 Dual -Bit, 0 MSPS A/D Converter FEATURES Dual -Bit ADCs on a Single Chip Low Power: 00 mw Typical On-Chip. V Reference and Track-and-Hold V p-p Analog Input Range Single V Supply Operation V or V Logic Interface 0 MHz Analog Bandwidth Power-Down Mode: < mw APPLICATIONS Digital Communications (QAM Demodulators) RGB and YC/Composite Video Processing Digital Data Storage Read Channels Medical Imaging Digital Instrumentation FUNCTIONAL BLOCK DIAGRAM V D PWRDN V DD AINA T/H ADC A D7A D0A VREF ENCODE. AINB T/H ADC B D7B D0B GND PIN CONFIGURATION PRODUCT DESCRIPTION The is a dual -bit monolithic analog-to-digital converter optimized for low cost, low power, small size, and ease of use. With a 0 MSPS encode rate capability and full-power analog bandwidth of 0 MHz typical, the component is ideal for applications requiring multiple ADCs with excellent dynamic performance. To minimize system cost and power dissipation, the includes an internal. V reference and dual track-and-hold circuits. The ADC requires only a V power supply and an encode clock. No external reference or driver components are required for many applications. The s single encode input is TTL/CMOS compatible and simultaneously controls both internal ADC channels. The parallel -bit digital outputs can be operated from V or V supplies. A power-down function may be exercised to bring total consumption to < mw when ADC data is not required for lengthy periods of time. In power-down mode, the digital outputs are driven to a high impedance state. Fabricated on an advanced BiCMOS process, the is available in a space-saving -lead shrink small outline package (-lead SSOP) and is specified over the industrial temperature range ( 0 C to + C). Customers desiring single-channel digitization may consider the AD907, a single -bit, 0 MSPS monolithic based on the ADC core. The AD907 is available in a 0-lead shrink small outline package (0-lead SSOP) and is specified over the industrial temperature range. AINA VREF PWRDN V D GND V DD D7A (MSB) 7 DA DA 9 DA 0 DA DA DA D0A (LSB) TOP VIEW (Not to Scale) AINB 7 GND ENCODE V D GND V DD D7B (MSB) DB 0 DB 9 DB DB 7 DB DB D0B (LSB) Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 90, Norwood, MA 00-90, U.S.A. Tel: 7/ Fax: 7/ Analog Devices, Inc. All rights reserved.

2 SPECIFICATIONS ELECTRICAL CHARACTERISTICS (V D = V, V DD = V, external reference, ENCODE = 0 MSPS, unless otherwise noted.) BRS Parameter Temp Test Level Min Typ Max Unit RESOLUTION Bits DC ACCURACY Differential Nonlinearity C I LSB Full VI. LSB Integral Nonlinearity C I LSB Full VI. LSB No Missing Codes Full VI Guaranteed Gain Error C I. + % FS Full VI + % FS Gain Temperature Coefficient Full V ±70 ppm/ C ANALOG INPUT Input Voltage Range (Centered at. V) C V.0 V p-p Input Offset Voltage C I 0 + mv Full VI + mv Input Resistance C V 0 kω Input Capacitance C V pf Input Bias Current C I µa Analog Bandwidth C V 0 MHz CHANNEL MATCHING (A to B) Gain Delta C V ± % FS Input Offset Voltage Delta C V ± mv BAND GAP REFERENCE Output Voltage Full VI... V Temperature Coefficient Full V ±0 ppm/ C SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 0 MSPS Minimum Conversion Rate Full IV MSPS Aperture Delay (t A ) C V.7 ns Aperture Uncertainty (Jitter) C V ps, rms Output Valid Time (t V ) Full IV.0. ns Output Propagation Delay (t PD ) Full IV 9.. ns DYNAMIC PERFORMANCE Transient Response C V 9 ns Overvoltage Recovery Time C V 9 ns Signal-to-Noise Ratio (SINAD) (with Harmonics) f IN = 0. MHz C I 0. f IN = 7 MHz C V. Effective Number of Bits (ENOB) f IN = 0. MHz C I. 7. Bits f IN = 7 MHz C V.9 Bits Signal-to-Noise Ratio (SNR) (Without Harmonics) f IN = 0. MHz C I f IN = 7 MHz C V Second Harmonic Distortion f IN = 0. MHz C I 0 c f IN = 7 MHz C V c Third Harmonic Distortion f IN = 0. MHz C I 0 c f IN = 7 MHz C V c Two-Tone Intermodulation Distortion (IMD) C V c Channel Crosstalk Rejection C V 0 c Differential Phase C V 0. Degrees Differential Gain C V.0 %

3 SPECIFICATIONS (continued) BRS Parameter Temp Test Level Min Typ Max Unit DIGITAL INPUTS Logic Voltage Full VI.0 V Logic 0 Voltage Full VI 0. V Logic Current Full VI ± µa Logic 0 Current Full VI ± µa Input Capacitance C V. pf Encode Pulsewidth High (t EH ) C IV.7 ns Encode Pulsewidth Low (t EL ) C IV.7 ns DIGITAL OUTPUTS Logic Voltage (V DD = V) Full VI.9 V Logic Voltage (V DD = V) Full IV.9 V Logic 0 Voltage (V DD = V or V) Full VI 0.0 V Output Coding Offset Binary Code POWER SUPPLY V D Supply Current (V D = V) Full VI 7 9 ma V DD Supply Current (V DD = V) Full VI ma Power Dissipation, Full VI 00 0 mw Power-Down Dissipation Full VI mw Power Supply Rejection Ratio (PSRR) C I mv/v NOTES Gain error and gain temperature coefficient are based on the ADC only (with a fixed. V external reference). t V and t PD are measured from the. V level of the ENCODE to the 0%/90% levels of the digital output swing. The digital output load during test is not to exceed an ac load of 0 pf or a dc current of ± 0 µa. SNR/harmonics based on an analog input voltage of 0. FS referenced to a.0 V full-scale input range. Digital supply current based on V DD = V output drive with <0 pf loading under dynamic test conditions. Power dissipation is based on 0 MSPS encode and 0. MHz analog input dynamic test conditions (V D = V ± %, V DD = V ± %). Typical thermal impedance for the RS style (SSOP) -lead package: θ JC = 9 C/W, θ CA = 70 C/W, and θ JA = 09 C/W. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS Test Level I 00% production tested. II 00% production tested at + C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 00% production tested at + C; guaranteed by design and characterization testing for industrial temperature range. ABSOLUTE MAXIMUM RATINGS* V D, V DD V Analog Inputs V to V D + 0. V Digital Inputs V to V D + 0. V VREF Input V to V D + 0. V Digital Output Current ma Operating Temperature C to + C Storage Temperature C to +0 C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Option BRS 0 C to + C RS- /PCB C Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

4 AIN ENCODE DIGITAL OUTPUTS N N + N + N + N + N + t A t EH t EL t V N N N N N + N + t PD MIN TYP MAX t A APERTURE DELAY.7ns t EH PULSEWIDTH HIGH.7ns ns t EL PULSEWIDTH LOW.7ns ns t V OUTPUT VALID TIME.0ns.n t PD OUTPUT PROP DELAY 9.ns.ns Figure. Timing Diagram PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function, AINA, AINB Analog Inputs for ADC A and B. VREF Internal Voltage Reference (. V Typical); Bypass with 0. µf to Ground or Overdrive with External Voltage Reference. PWRDN Power-Down Function Select; Logic HIGH for Power-Down Mode (Digital Outputs Go to High- Impedance State)., V D Analog V Power Supply.,, 7 GND Ground., V DD Digital Output Power Supply. Nominally V to V. 7 D7A D0A Digital Outputs of ADC A. D7B D0B Digital Outputs of ADC B. ENCODE Encode Clock for ADCs A and B (ADCs Sample Simultaneously on the Rising Edge of ENCODE). AINA VREF PWRDN V D GND V DD D7A (MSB) 7 DA DA 9 DA 0 DA DA DA D0A (LSB) TOP VIEW (Not to Scale) AINB 7 GND ENCODE V D GND V DD D7B (MSB) DB 0 DB 9 DB DB 7 DB DB D0B (LSB) Table I. Digital Coding (VREF =. V) Analog Input (V) Voltage Level Digital Output.0 Positive Full Scale.0 Midscale + / LSB Midscale / LSB 0.0 Negative Full Scale

5 Typical Performance Characteristics ENCODE = 0MSPS ANALOG IN = 0.MHz, 0.FS SINAD =.9 ENOB = 7.0 BITS SNR =. 0 0 ENCODE = 0MSPS AIN = 0.FS SECOND HARMONIC 70 0 THIRD HARMONIC FREQUENCY (MHz) TPC. FFT Spectral Plot 0 MSPS, 0. MHz ANALOG INPUT FREQUENCY (MHz) TPC. Harmonic Distortion vs. AIN Frequency ENCODE = 0MSPS ANALOG IN = 7MHz, 0.FS SINAD =.0 ENOB =. BITS SNR = ENCODE = 0MSPS F IN = 7.0FS F IN = 7.0FS F - F =.0c F - F =.0c FREQUENCY (MHz) TPC. Spectral Plot 0 MSPS, 7 MHz FREQUENCY (MHz) TPC. Two-Tone IMD SNR AIN = 0.MHz, 0.FS SNR 0 SINAD SINAD ENCODE = 0MSPS AIN = 0.FS ANALOG INPUT FREQUENCY (MHz) TPC. SINAD/SNR vs. AIN Frequency ENCODE RATE (MSPS) TPC. SINAD/SNR vs. Encode Rate

6 00 0 AIN = 0.MHz, 0.FS 0 V DD = V POWER (mw) 0 00 V DD = t PD (ns) V DD = 00 V DD = V ENCODE RATE (MSPS) TPC 7. Power Dissipation vs. Encode Rate TEMPERATURE ( C) TPC 0. t PD vs. Temperature/Supply ( V/ V)..0 SNR.0. SNR..0 SINAD ENCODE = 0MSPS AIN = 0.MHz, 0.FS TEMPERATURE ( C) TPC. SINAD/SNR vs. Temperature ENCODE = 0MSPS AIN = 0.MHz, 0.FS SINAD ENCODE HIGH PULSEWIDTH (ns) TPC. SINAD/SNR vs. Encode Pulsewidth 0 0 GAIN ERROR (%) ADC GAIN () 7 ENCODE = 0MSPS AIN = 0.FS TEMPERATURE ( C) TPC 9. ADC Gain vs. Temperature (With External. V Reference) ANALOG FREQUENCY (MHz) TPC. ADC Frequency Response

7 THEORY OF OPERATION The combines Analog Devices proprietary MagAmp gray code conversion circuitry with flash converter technology to provide dual high performance -bit ADCs in a single low cost monolithic device. The design architecture ensures low power, high speed, and -bit accuracy. The provides two linked ADC channels that are clocked from a single ENCODE input (see Functional Block Diagram). The two ADC channels simultaneously sample the analog inputs (AINA and AINB) and provide noninterleaved parallel digital outputs (D0A D7A and D0B D7B). The voltage reference (VREF) is internally connected to both ADCs so channel gains and offsets will track if external reference control is desired. The analog input signal is buffered at the input of each ADC channel and applied to a high speed track-and-hold. The trackand-hold circuit holds the analog input value during the conversion process (beginning with the rising edge of the ENCODE command). The track-and-hold s output signal passes through the gray code and flash conversion stages to generate coarse and fine digital representations of the held analog input level. Decode logic combines the multistage data and aligns the -bit word for strobed outputs on the rising edge of the ENCODE command. The MagAmp/Flash architecture of the results in three pipeline delays for the output data. USING THE Analog Inputs The provides independent single-ended high impedance (0 kω) analog inputs for the dual ADCs. Each input requires a dc bias current of µa (typical) centered near. V (±0%). The dc bias may be provided by the user or may be derived from the ADC s internal voltage reference. Figure shows a low cost dc bias implementation that allows the user to capacitively couple ac signals directly into the ADC without additional active circuitry. For best dynamic performance, the VREF pin should be decoupled to ground with a 0. µf capacitor (to minimize modulation of the reference voltage), and the bias resistor should be approximately kω. VIN A (V p-p) EXTERNAL V REF (OPTIONAL) VIN B (V p-p) AINA VREF AINB Figure shows typical connections for high performance dc biasing using the ADC s internal voltage reference. All components may be powered from a single V supply (analog input signals are referenced to ground). VIN A VIN B ( 0. TO +0.) 0k + AD0 0k AD0 AINA VREF AINB + Figure. DC-Coupled (VIN Inverted) Voltage Reference A stable and accurate. V voltage reference is built into the (VREF). The reference output is used to set the ADC gain/offset and can provide dc bias for the analog input signals. The internal reference is tied to the ADC circuitry through an 00 Ω internal impedance and is capable of providing 00 µa external drive current (for dc biasing the analog input or other user circuitry). Some applications may require greater accuracy, improved temperature performance, or gain adjustments that cannot be obtained using the internal reference. An external voltage may be applied to the VREF pin to overdrive the internal voltage reference for gain adjustment of up to ±0% (the VREF pin is internally tied directly to the ADC circuitry). ADC gain and offset will vary simultaneously with external reference adjustment with a : ratio (a % or 0 mv adjustment to the. V reference varies ADC gain by % and ADC offset by 0 mv). Theoretical input voltage range versus reference input voltage may be calculated using the following equations. VRANGE ( p p) = VREF. VMIDSCALE = VREF VTOP OF RANGE = VREF + VRANGE V = VREF V BOTTOM OF RANGE RANGE The external reference should have a ma minimum sink/ source current capability to ensure complete overdrive of the internal voltage reference. Figure. Capacity Coupled 7

8 Digital Logic ( V/ V Systems) The digital inputs and outputs of the can easily be configured to interface directly with V or V logic systems. The encode and power-down (PWRDN) inputs are CMOS stages with TTL thresholds of. V, making the inputs compatible with TTL, V CMOS, and V CMOS logic families. As with all high speed data converters, the encode signal should be clean and jitter free to prevent degradation of ADC dynamic performance. The s digital outputs will also interface directly with V or V CMOS logic systems. The voltage supply pins (V DD ) for these CMOS stages are isolated from the analog V D voltage supply. By varying the voltage on these supply pins, the digital output high levels will change for V or V systems. The V DD pins are internally connected on the die. Care should be taken to isolate the V DD supply voltages from the V analog supply to minimize noise coupling into the ADCs. The provides high impedance digital output operation when the ADC is driven into power-down mode (PWRDN, logic high). A 00 ns (minimum) power-down time should be provided before a high impedance characteristic is required. A 00 ns power-up period should be provided to ensure accurate ADC output data after reactivation (valid output data is available three clock cycles after the 00 ns delay). Timing The is guaranteed to operate with conversion rates from MSPS to 0 MSPS. At 0 MSPS, the ADC is designed to operate with an encode duty cycle of 0%, but performance is insensitive to moderate variations. Pulsewidth variations of up to ±0% (allowing the encode signal to meet the minimum/ maximum high/low specifications) will cause no degradation in ADC performance (see Figure ). Due to the linked ENCODE architecture of the ADCs, the cannot be operated in a -channel ping-pong mode. Power Dissipation The power dissipation of the is specified to reflect a typical application setup under the following conditions: encode is 0 MSPS, analog input is 0. FS at 0. MHz, V D is V, V DD is V, and digital outputs are loaded with 7 pf typical (0 pf maximum). The actual dissipation will vary as these conditions are modified in user applications. TPC 7 shows typical power consumption for the versus ADC encode frequency and V DD supply voltage. A power-down function allows users to reduce power dissipation when ADC data is not required. A TTL/CMOS high signal (PWRDN) shuts down portions of the dual ADC and brings total power dissipation to less than 0 mw. The internal band gap voltage reference remains active during power-down mode to minimize ADC reactivation time. If the power-down function is not desired, Pin should be tied to ground. Both ADC channels are controlled simultaneously by the PWRDN pin; they cannot be shut down or turned on independently. Applications The wide analog bandwidth of the makes it attractive for a variety of high performance receiver and encoder applications. Figure shows the dual ADC in a typical low cost I and Q demodulator implementation for cable, satellite, or wireless LAN modem receivers. The excellent dynamic performance of the ADC at higher analog input frequencies and encode rates empowers users to employ direct IF sampling techniques (see TPC ). IF sampling eliminates or simplifies analog mixer and filter stages to reduce total system cost and power. IF IN 90 VCO BPF BPF ADC ADC VCO Figure. I and Q Digital Receiver The high sampling rate and analog bandwidth of the are ideal for computer RGB video digitizer applications. With a full-power analog bandwidth of the maximum sampling rate, the ADC provides sufficient pixel-to-pixel transient settling time to ensure accurate 0 MSPS video digitization. Figure shows a typical RGB video digitizer implementation for the. RED GREEN H-SYNC BLUE PLL ADC ADC ADC ADC PIXEL CLOCK Figure. RGB Video Encoder

9 +V D +V D +V DD V TO +V D. 00 k.k VREF ENCODE PWRDN D0 D7 AIN 00 VREF VOLTAGE REFERENCE DIGITAL INPUTS DIGITAL OUTPUTS Figure. Equivalent Circuits ANALOG INPUTS Evaluation Board The /PCB evaluation board provides an easy-to-use analog/digital interface for the dual -bit, 0 MSPS ADC. The board includes typical hardware configurations for a variety of high speed digitization evaluations. On-board components include the (in the -lead SSOP package), optional analog input buffer amplifiers, digital output latches, board timing drivers, and configurable jumpers for ac coupling, dc coupling, and powerdown function testing. The board is configured at shipment for dc coupling using the s internal reference. For dc-coupled analog input applications, amplifiers U and U are configured to operate as unity gain inverters with adjustable offset for the analog input signals. For full-scale ADC drive, each analog input signal should be V p-p into 0 Ω referenced to ground. Each amplifier offsets its analog signal by +VREF (. V typical) to center the voltage for proper ADC input drive. For dc-coupled operation, connect E7 to E9 (analog input A to R), E to E (amplifier output to analog input A of ), E to E (analog input B to R0), and E to E0 (amplifier output to analog input B of ) using the board jumper connectors. For ac-coupled analog input applications, amplifiers U and U are removed from the analog signal paths. The analog signals are coupled through Capacitors C and C, each terminated to the VREF voltage through separate kω resistors (providing bias current for the analog inputs, AINA and AINB). Analog input signals to the board should be V p-p into 0 Ω for full-scale ADC drive. For ac-coupled operation, connect E7 to E (analog input A to C feedthrough capacitor), E to E (C to R termination resistor for Channel A), E to E (analog input B to C feedthrough capacitor), and E0 to E (C to R termination resistor for Channel B) using the board jumper connectors. The on-board reference voltage may be used to drive the ADC or an external reference may be applied. The standard configuration employs the internal voltage reference without any external connection requirements. An external voltage reference may be applied at board connector input REF to overdrive the limited current output of the s internal voltage reference. The external voltage reference should be. V typical. The power-down function of the can be exercised through a board jumper connection. Connect E to E ( V to PWRDN) for power-down mode operation. For normal operation, connect E to E (ground to PWRDN). The encode signal source should be TTL/CMOS compatible and capable of driving a 0 Ω termination. The digital outputs of the are buffered through latches on the evaluation board (U and U) and are available for the user at connector Pins 0 7 and Pins 9. Latch timing is derived from the ADC ENCODE clock and a digital clocking signal is provided for the board user at connector Pins and. 9

10 CK OE U 7ACQ7 D 7D D D D D D D Q 7Q Q Q Q Q Q Q D0B DB DB DB DB DB DB D7B DB0 DB DB DB DB DB DB DB CK OE U 7ACQ7 D 7D D D D D D D Q 7Q Q Q Q Q Q Q D7A DA DA DA DA DA DA D0A DA7 DA DA DA DA DA DA DA0 U7 7AC00 R E0 E E C E E E PWRDN E E E R 0 R 7 DIS +V S NC NC V S U AD0Q R E R 0 BNC J ANALOG IN A P C7DRPF R7 BNC J0 ENCODE J, GND C C7 C C 0µF C C C C DECOUPLING CAPS J, V D E7 E9 U RS AINA VREF PWRDN GND V D V DD D7A DA DA DA DA DA DA D0A AINB GND ENC GND V D V DD D7B DB DB DB DB DB DB D0B D7B DB DB DB DB DB DB D0B C C 0µF J9, V DD C9 DB0 DB DB DB DB DB DB DB7 DA0 DA DA DA DA DA DA DA7 U7 7AC00 U7 7AC00 C0 C7 0µF R9 0k R 0k R J, REF D7A DA DA DA DA DA DA D0A R 0 7 DIS +V S NC NC V S U AD0Q R0 E R 0 BNC J ANALOG IN B R E E C Figure 7. Dual Evaluation Board Schematic

11 Figure. Evaluation Board Layout (Top) Figure 9. Evaluation Board Layout (Bottom)

12 OUTLINE DIMENSIONS -Lead Shrink Small Outline Package [SSOP] (RS-) Dimensions shown in millimeters C00 0 /0(A).00 MAX COPLANARITY 0.0 MIN 0. BSC SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-0AH Revision History Location Page /0 Data Sheet changed from REV. 0 to. Renumbered Figures and TPCs Universal Changes to SPECIFICATIONS Updated OUTLINE DIMENSIONS