9240LP LPTVREF. Memory DESCRIPTION: FEATURES: 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC. 9240LP Block Diagram 9240LP

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1 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC NC BIAS CAPB CAPT NC CML LPTref VinA VinB LPTAVDD LPTDVDD REFCOM Vref SENSE NC AVSS AVDD NC NC OTC BIT 1 BIT 2 BIT 3 BIT 4 BIT BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 BIT 13 LPTSTATUS LPTBIT AVDD DVDD DRVDD VINA VINB VREF CURRENT SENSE CROW BAR LPTAVDD LPTDVDD LPTVREF LPTDRVDD LPTVINA LPTVINB LPTVREF Bit A/D AVDD DVDD DRVDD VINA VINB VREF Data Outputs Control Signals FEATURES: DVSS AVSS DVDD AVDD NC DRVDD CLK LPTSTATUS LPTBIT NC BIT 14 DESCRIPTION: Block Diagram RAD-PAK radiation-hardened agait natural space radiation Low power dissipation: 28 mw Single V supply Integral nonlinearity error: 2. LSB Differential nonlinearity error: 0.6 LSB Input referred noise: 0.36 LSB Complete: On-chip sample-and-hold amplifier and voltage reference Signal-to-noise and distortion ration: 77. Spurious-free dynamic range: 90 Out-of-range indicator Straight binary output data Total dose hardened to 100 krads (Si), dependent on orbit and mission duration Single Event Latchup (SEL) protected Maxwell Technologies is a 14-bit analog to digital converter that operates at a 10 MSPS rate. Manufactured with a high speed CMOS process, this A/D, with latch-up protection, contai an onchip, high performance, low noise, sample-andhold amplifier and a programmable voltage reference. The offers single supply operation and dissipates only 480 mw with a volt supply. This device provides no missing codes and excellent temperature drift performance over the full operating temperature range. The utilizes Maxwell s LPT Latchup Protection Circuit. Maxwell Technologies' patented RAD-PAK packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides protection to 100 krad (Si) radiation dose tolerance. This product is available with screening up to Maxwell Technologies self-defined Class K flow Rev 8 All data sheets are subject to change without notice 1 (88) Fax: (88)

2 TABLE 1. PIN DESCRIPTION PIN NUMBER NAME DESCRIPTION 1 DVSS Digital Ground 2, 29 AVSS Analog Ground 3 DVDD V Digital Supply 4, 28 AVDD V Analog Supply NC No Connect 6 DRVDD Digital Output Driver Supply 7 CLK Clock Input Pin 8 LPTSTATUS A 0 to V square-wave is output during the decision time and protect time. Normally low. 9 LPTBIT The LPT circuit will crowbar the power supplies to the 9240 for as long as a logic high is applied. Used to verify operation of the LPT. Normally a logical low or ground is applied to this input. 10 NC No Connect 11 BIT 14 Least Significant Data Bit (LSB) BIT 13-BIT 2 Data Output Bits 24 BIT 1 Most Significant Data Bits (MSB) 2 OTR Out of Range 26, 27, 30 NC No Connect 31 SENSE Reference Select 32 VREF Reference I/O 33 REFCOM Reference Common 34, 38 NC No Connect 3 BIAS 1 Power/Speed Programming 36 CAPB Noise Reduction Pin 37 CAPT Noise Reduction Pin 39 CML Common-Mod Level (Midsupply) 40 LPTVREF Protected Reference I/O 41 VINA Analog Input Pin (+) 42 VINB Analog Input Pin (-) 43 LPTDVDD Protected V Digital Supply 44 LPTAVDD Protected V Analog Supply 1. See Speed/Power programmability section Rev 8 All data sheets are subject to change without notice 2

3 TABLE 2. ABSOLUTE MAXIMUM RATINGS 1 WITH RESPECT PARAMETER SYMBOL MIN TYP MAX UNIT TO AVDD AVSS V DVDD DVSS V AVSS DVSS V AVDD DVDD V DRVDD DRVSS V DRVSS AVSS V REFCOM AVSS V CLK AVSS 0 AVDD -0. V Digital Outputs DRVSS -0.3 DRVDD V VINA, VINB AVSS -0.3 AVDD V VREF AVSS -0.3 AVDD V SENSE AVSS -0.3 AVDD V CAPB, CAPT AVSS -0.3 AVDD V BIAS AVSS -0.3 AVDD V Junction Temperature T J 10 C Operating Temperature T A - 12 C Package Weight 10. Grams Thermal Resistance TJC 9.6 C/W Storage Temperature T STG C Lead Temperature (10 sec) T L 300 C 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification are not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. TABLE 3. DELTA TABLE PARAMETERS 1. PARAMETERS VARIATION IDVDD +/- 10 % IADVD +/- 10% 1. Parameters are measured and recorded as Deltas per MIL-STD-883 for Class K devices. Specified in Table Rev 8 All data sheets are subject to change without notice 3

4 TABLE 3. TABLE 4. DC SPECIFICATIONS (AVDD = V, DVDD = V, DRVDD = V, R BIAS = 2KΩ, V REF = 2.V, VINA=VINB = ±2.V DIFFERENTIAL INPUT CENTERED ON VREF(1.2V TO 3.7V ABSOLUTE) T A = - TO +12 C, UNLESS OTHERWISE SPECIFIED) PARAMETER SUBGROUPS MIN TYP 1 MAX UNIT RESOLUTION 1 14 Bits min MAX CONVERSION RATE 9, 10, MHz min MAX REFERRED NOISE 1 VREF= 1 V VREF = 2.V ACCURACY 2 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL 3 DNL 3 No Missing Codes Zero Error (@ 2 C) Gain Error (@ 2 C) 1,4 Gain Error (@ 2 C) TEMPERATURE DRIFT Zero Error Gain Error 4 Gain Error ±2. ±0.6 ±2. ± LSB rms LSB LSB LSB LSB Bits Guaranteed % FSR % FSR % FSR ppm/ C ppm/ C ppm/ C POWER SUPPLY REJECTION 0.1 % FSR ANALOG INPUT 1 Input Span (with VREF = 1.0 V) (with VREF = 2. V) Input (VINA OR VINB) Range Input Capacitance AVDD +.2 V p-p V p-p V pf INTERNAL VOLTAGE REFERENCE 1 Output Voltage (1V mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2. V Mode) Output Voltage Tolerance (2. V Mode) Load Regulation V REF Load Regulation LPTV 6,7 REF ±14 ± V mv V mv mv mv REFERENCE INPUT RESISTANCE kω Rev 8 All data sheets are subject to change without notice 4

5 TABLE 3. TABLE 4. DC SPECIFICATIONS (AVDD = V, DVDD = V, DRVDD = V, R BIAS = 2KΩ, V REF = 2.V, VINA=VINB = ±2.V DIFFERENTIAL INPUT CENTERED ON VREF(1.2V TO 3.7V ABSOLUTE) T A = - TO +12 C, UNLESS OTHERWISE SPECIFIED) PARAMETER SUBGROUPS MIN TYP 1 MAX UNIT LPT ASIC RDS ON - V REF - AVDD - DVDD - V IN A - V IN B LATCHUP PROTECTION - Decision Time - Protect Time - AVDD Trip Current - AVDD Trip Current Tolerance - DVDD Trip Current - DVDD Trip Current Tolerance POWER SUPPLIES Supply Voltages - AVDD - DVDD - DRVDD Supply Current - IAVDD - IDVDD ±1 28 ± Ω Ω Ω Ω 16 µs µs ma ma ma V (±% AVDD Operating) V (±% DVDD Operating) V (±% DRVDD Operating) POWER CONSUMPTION mw 1. Guaranteed by design 2. Tested using external V REF with servo control 3. V REF = 1V 4. Including internal reference. Excluding internal reference 6. Load regulkation with 1 ma load current 7. LPTV REF should not be capacitively loaded above 0.1uF ma ma 8. Calculated from I DD Rev 8 All data sheets are subject to change without notice

6 TABLE. AC SPECIFICATIONS (AVDD = V, DVDD = V, DRVDD = V, fsample = 10MSPS, BIAS = 2KΩ, V REF = 2.V, VINA = -0.FS, AC COUPLED/DIFFERENTIAL INPUT, T A = - TO +12 C, UNLESS OTHERWISE SPECIFIED) PARAMETER SUBGROUPS MIN TYP 1 MAX UNIT SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D) = 00 khz = 1.0 MHz =.0 MHz EFFECTIVE NUMBER OF BITS (ENOB) 2 = 00 khz = 1.0 MHz =.0 MHz Bits Bits Bits SIGNAL-TO-NOISE RATION (SNR) = 00 khz = 1.0 MHz =.0 MHz 4,, TOTAL HARMONIC DISTORTION (THD) = 00 khz = 1.0 MHz =.0 MHz SPURIOUS FREE DYNAMIC RANGE = 00 khz = 1.0 MHz =.0 MHz 4,, DYNAMIC PERFORMANCE 1 Full Power Bandwidth Small Signal Bandwidth Aperture Delay Aperture Jitter Acquisition to Full-Scale Step (0.002%) Overvoltage Recovery Time 1. Guaranteed by design MHz MHz ps rms 2. ENOB calculated from SNR TABLE 6. DIGITAL SPECIFICATIONS (AVDD = V, DVDD = V, T A = - TO +12 C, UNLESS OTHERWISE SPECIFIED) PARAMETER SUBGROUPS SYMBOL MIN TYP MAX UNIT CLOCK INPUT 1 High Level Input Voltage 2 Low Level Input Voltage High Level Input Current (V IN = DVDD) Low Level Input Current (V IN = 0V) Input Capacitance V IH V IL I IH IIL C IN ±10 ±10 V V µa µa pf Rev 8 All data sheets are subject to change without notice 6

7 TABLE 6. DIGITAL SPECIFICATIONS (AVDD = V, DVDD = V, T A = - TO +12 C, UNLESS OTHERWISE SPECIFIED) PARAMETER SUBGROUPS SYMBOL MIN TYP MAX UNIT LOGIC OUTPUTS (with DRVDD = V) High Level Output Voltage (I OH = 0 µa) High Level Output Voltage (I OH = 0. ma) Low Level Output Voltage (I OL = 1.6 ma) Low Level Output Voltage (I OL = 0 µa) Output Capacitance 1. Due to the voltage drop across the LPT circuiry the CLOCK signal must be no greater than AVDD - 0.V 2. Guaranteed by design V OH V OH V OL V OL C OUT V min V min V max V max pf typ TABLE 7. SWITCHING CHARACTERISTICS 1 (T A = - TO +12 C WITH AVDD = V, DVDD = V, DRVDD = V, R BIAS = 2 KW, C L = 20 PF) PARAMETER SYMBOL MIN TYP MAX UNITS Clock Period CLOCK Pulse width High CLOCK Pulse width Low Output Delay Pipeline Delay (Latency) 1. Guaranteed by design t C t CH t CL t OD Clock Cycles TYPICAL DIFFERENTIAL CHARACTERIZATION CURVES/PLOTS (AVDD = V, DVDD = V, DRVDD = V, f SAMPLE = 10 MSPS, R BIAS = 2 KW, T A = 2 C, DIFFERENTIAL INPUT) FIGURE 1. TIMING DIAGRAM Rev 8 All data sheets are subject to change without notice 7

8 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC FIGURE 2. SINAD VS. INPUT FREQUENCY (INPUT SPACE = 2V, VCM = 2.V) FIGURE 3. THD VS. INPUT FREQUENCY (INPUT SPAN = V, VCM = 2.V) Rev 8 All data sheets are subject to change without notice 8

9 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC FIGURE 4. TYPICAL FFT, f IN = 1.0 MHZ (INPUT SPACE = V, V CM = 2.V) FIGURE. SINAD VS. INPUT FREQUENCY (INPUT SPAN = 2V, VCM = 2.V) FIGURE 6. THD VS. INPUT FREQUENCY (INPUT SPAN = 2V, V CM = 2.V) Rev 8 All data sheets are subject to change without notice 9

10 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC FIGURE 7. TYPICAL FFT, f IN =.0 MHZ (INPUT SPAN = 2 V, V CM = 2. V) FIGURE 8. THD VS. SAMPLE RATE (f IN =.0 MHZ, A IN = -0. DBFS, V CM = 2. V) FIGURE 9. SINGLE TONE SFDR (f IN =.0 MHZ, V CM = 2. V) Rev 8 All data sheets are subject to change without notice10

11 FIGURE 10. DUAL TONE SFDR (F 1 = 0.9 MHZ, F 2 = 1.04 MHZ, V CM = 2. V) FIGURE 11. TYPICAL INL (INPUT SPAN = V) FIGURE 12. TYPICAL DNL (INPUT SPAN = V) Rev 8 All data sheets are subject to change without notice 11

12 FIGURE 13. GROUNDED-INPUT HISTOGRAM (INPUT SPAN = V) FIGURE 14. SINAD VS. INPUT FREQUENCY (INPUT SPAN = 2 V, V CM = 2.V) Rev 8 All data sheets are subject to change without notice12

13 FIGURE 1. THD VS. INPUT FREQUENCY (INPUT SPAN = V, V CM = 2. V) FIGURE 16. CMR VS. INPUT FREQUENCY (INPUT SPAN = 2 V, VCM = 2. V) Rev 8 All data sheets are subject to change without notice13

14 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC FIGURE 17. SINAD VS. INPUT FREQUENCY (INPUT SPAN = V, V CM = 2. V) FIGURE 18. THD VS. INPUT FREQUENCY (INPUT SPAN = V, V CM = 2. V) FIGURE 19. TYPICAL VOLTAGE REFERENCE ERROR VS. TEMPERATURE Rev 8 All data sheets are subject to change without notice14

15 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC FIGURE 20. SEL CROSS SECTION 44 PIN RAD-PAK QUAD FLAT PACKAGE SYMBOL DIMENSION MIN NOM MAX A b c D D1 0.0 BSC e 0.00 BSC S L Q N 44 Note: All dimeio in inches Rev 8 All data sheets are subject to change without notice1

16 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC Important Notice: These data sheets are created using the chip manufacturers published specificatio. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specificatio presented within these data sheets represent the latest and most accurate information available to date. However, these specificatio are subject to change without notice and Maxwell Technologies assumes no respoibility for the use of this information. Maxwell Technologies products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim agait Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies liability shall be limited to replacement of defective parts Rev 8 All data sheets are subject to change without notice16

17 Product Ordering Optio Model Number RP Q X Feature Option Details Screening Flow Multi Cjip Module 1 K= Maxwell Class K H= Maxwell Class H I = Industrial - C, +2 C, +12 C) E = Engineering +2 C) Package Q = Quad Flat Pack Radiation Feature RP = RAD-PAK package Base Product Nomenclature 14-Bit, 10MSPS A/D Converter with LPT ASIC 1) Products are manufacturered and screened to Maxwell Technologies self-defined CLASS H and CLASS K flows Rev 8 All data sheets are subject to change without notice17