Design of 12-bit 100-MHz Current-Steering DAC for SOC Applications

Transcription

1 Design of 12-bit 100-MHz Current-Steering DAC for SOC Applications Chun-Yueh Huang Tsung-Tien Hou, and Chi-Chieh Chuang Department of Electronic Engineering Kun Shan Universiv of Technology Yung-Kang, Tainan, Taiwan, R.O.C. Hung-Yu Wang Chip Implementation Center, National Applied Research Laboratories, Taiwun, R. 0. C. Abstract In this paper, we propose a 12-bit 100-MHz current-steering digital-to-analog converter (DAC) for system-on-a-chip (SOC) applications. We adapt the segmented architecture to design this DAC to obtain better perj?ormances of LVL, Glitch energy, and monotonicity. The segmented architecture includes 7- MSBs which are decoded into 127 equally weighted current sources and 5-LSBs which are corresponding to binary-weighted current sources. Based on the TSMC 0.35um 2p4m CMOS technology, we use HSPICE to simulate the proposed DAC. The simulation results show that the proposed DAC has the following characteristics: INL < B.4LSB, DNL< f 0.25LSB, and settling time less than 9ns. The proposed converter s spurious free dynamic ranges (SFDfi) for are larger than 80 db and 65 db at an update rate fc& loomhz and its output frequencies are I MHz and 49 MHz, respectively. The power consumption is 47 m W at the maximum conversion rate. 1. Introduction In the applications of HDTV, video and modern communication systems, high-speed and high-accuracy digital-to-analog converters are indispensable components. In the past years, many researchers have devoted to developing the high-speed and highaccuracy DACs [ While designing DACs for SOC applications, an important issue must be considered. We need to consider how to integrate analog circuits with memory and digital signal processing (DSP) circuits on the same chip, and use CMOS technology This work was supported by the MOE Program for Promoting Academic Excellence of Universities, under Grant EX-93-E-FA to fabricate the SOC. To design the high-speed and high-accuracy DACs to meet the requirement of SOC applications, a current-steering DAC architecture is particularly suitable for SOC applications, because it can be implemented by standard CMOS technology. In this paper, we design a 12-bit 100-MHz currentsteering DAC. In order to reduce glitch and to ensure monotonicity, the segmented architecture is used to design the DAC. The common-centroid layout approach is used to realize the layout of most significant bits (MSB) unary cells current source transistors to reduce the process graded error and symmetrical error. 2. Design of a current-steerign DAC Figure 1 shows the block diagram of the proposed segmented DAC architecture. In this DAC, the segmented architecture consists of 7-MSBs and 5- LSBs, which are thermometer coded and binary weighted coded, respectively. The segmented currentsteering topology is used to guarantee monotonicity for the MSBs and to improve the performance of DNL. The 7-MSB digits (bll * b5) are decoded by a thermometer decoder into 127 thermometer codes, and the 5-LSB binary digits (b4 - bo) are directly fed to the second D-latch array. Two D-latch array and clock driver are used to synchronize the DAC and to reduce glitch energy. In the current source array, there are 127 unary current cells and 5 binary weighted current cells. According to the digital inputs, the outputs of the second D-latch array from the 127 thermometer codes and 5 binary codes are used to determine the DAC output value by switching the currents of unary current source array and binary current source array into the output load (50 n), respectively /05 $ IEEE 117

2 For ease of understanding the design methodology, the basic components of the current-steering DAC are discussed in detail as follows. 0 CLK Do 1 $j-m2 1 NOT3 NOT4 Figure 2. The circuit diagram of D-latch Figure 1. The block diagram of the proposed currentsteering DAC A. D-latch Master r-tw-c The circuit diagram of D-latch is shown in Fig. 2. The D-Latch, which is the simplest digital storage element, is a samplehold circuit and can be used to keep the synchronization of control signals in the DAC. Basically, in the D-Latch, two cross-coupled inverters (NOTl and NOT2) are acted as a storage unit and two inverters (NOT3 and NOT4) as buffers. When CLK is high, transistors M2 and M3 are turned on, and the input signal D through transistors M2 and M3 are transmitted to latch output Q. The signal of Q is dependent on the value of input D. When CLK is low, transistors M2 and M3 are turned off, and the Q of the D-latch will be dependent on the input value of D just before CLK is turned low. Considering the circuit implementation, when CLK is high, the input signal through transistors M2 and M3 must dominate over the positive feedback through NOTl. In order to meet the above requirement, the widths of the transistors of NOTl must be designed as small as possible, i.e., at their minimum widths. With this condition, the input signal can correctly change the state of the D-latch. B. Clock driver In order to reduce the global clock timing skew, we need to develop a good clock distribution approach to align the switching signal with the D-latch array. In the DAC, the clock tree structure as shown in Fig.3 is used to improve buffering and equal clock delay to the D- latch array and to optimize the speed and clock edge I ".. +. Figure 3. The clock tree structure... i thermometer encoder thermometer encoder.... I.".... s," s1, sz,... s,"., s,"+,, s,",,,... SF'4 Figure 4. Iterative implementation of a thermometer decoder C. Thermometer decoder Basically, a binary code consisting of k bits is converted into a thermometer code of 2k-1 bits. Based on the iterative approach, a (k+l)-to- (2'+' -1) binary-to-thermometer decoder can be constructed by using a (&to- (2k -1) decoder as shown in Fig. 4, where there are (2' -1) AND gates and (2' -1) OR gates. In the proposed DAC, the input binary codes of 7-MSBs are converted into 127 bits thermometer codes. The total delay through the thermometer decoder is the propagation delay of six gates with inverter buffers at the output, The difference in the delay is small enough to guarantee over 100 MHz operation. All the decoded data are latched at the second D-latch array before driving the current switches. 118

3 D. Current cell In the DAC, the current source cannot be completely turned off and therefore the switching signals have to be properly matched to improve the glitch performance. A proper switching scheme for the PMOS differential current switch is implemented by transistors M3 and M5 as shown in Fig.5. Two transistors M4 and M6 with self-bias are used to increase the output impedance of the current cell. The output impedance of the current cell has a great influence on the specifications of INL (integral nonlinearity) and SFDR [9,10]. The relationship between the impedance and the achievable INL specification is given by [ 101 T R AT2 where RL is the load resistor, runit is the LSB current, and N is the total number of unit current sources. Considering the frequency dependency of the output impedance, the relation between the SFDR specification is given by [9] NRL R,, =- 4s where S is the ratio between the fundamental signal and the second harmonic component caused by the output impedance effect. According to Eq. (2), for a 12-bit current steering DAC, the ratio has to be at least equal to 72 db. If the load resistor is a 50!2 double terminated cable and N is equal to 4095, the value for required output impedance Rout has to be at least loom!2 in the Nyquist frequency range. In order to make the output impedance of the current cell large enough, and to satisfy the specification of INL and SFDR, the cascade current source configuration and the cascade switching transistors as shown in Fig. 5 are used to design the current cell. Figure 5. The circuit diagram of a current cell In Fig. 5, the output impedance of the current cell Rout is approximately calculated as Rout gm4gm3gm2ro4ro3ro2rol (3) In the current cell, the device dimensions of the channel width W and the channel length L for M1-M2 and M3-M6 are 6.Y2.5 and 3/0.35 pm, respectively. Next, when we implement the DAC layout, we have to think of some questions. For instance, the current cell will exist transistor matching errors, i.e., size errors, threshold voltage variations, supply and bias voltage variations, oxide thickness variations, output voltage variations, etc. In order to improve transistor matching errors, in the current source array, we use basic unit current sources from different positions to construct this array by means of common-centroid technique as shown in Fig. 6. This approach can reduce the problem of process graded and systematic errors, but it will increase the wire resistance and capacitance as well. The shaded area is the dummy cells for avoiding over etching of process. Figure 6. The floor plan common-centroid technique of current source E. Bias circuit In Fig.5, the cascade current mirror in the current cell can be used to reduce short-channel effects and increase the output impedance, but it will limit the signal swings. In order to reduce this limitation, a wide-swing cascade current mirror bias scheme as shown in Fig. 7 is used to provide the accurate bias voltages for the current cells. In the bias circuit, the diode-connected transistors M1, M2, M3 and M8, M9, M10 provide a bias to transistor M4 and M12, respectively. The transistors M4 and M12 are used to increase the gate-source voltages of transistor M5 and M11 and control the drain-source voltages of transistor M5 and M11 in edge of saturation. 119

4 0.25 LSB and 0.4 LSB, respectively, as shown in Fig. 9 andfig. 10. For the SFDR simulation, the converter is simulated at the condition of the update rate for a full-scale input signal with a fkequency of 1 MHz sine wave. Fig. 11 shows that the SFDR remains above 80 db at the update rate of 100 MS/s. Furthermore, Fig. 12 shows that the SFDR is above 65dE3, for Nyquist fi-equency range simulation, in the condition of a full-scale input signal with a frequency of 49 MHz under the sampling rate of 100 MHz. The settling time of the DAC is less than 911s.The power consumption is 47 mw at the maximum conversion rate. The summary of the performance of the proposed DAC is shown in Table 1. The above approach can reduce the variations in the drain-source voltage of M5 and M7 with changes in VDD,and hence can make the bias current rout more accurately equal to the reference current Im~. The reference current IREF depends on external resistor R and the device dimensions of the transistor M5.The can be derived as follows value of IREF DLI = REF + G S5 (4) where K = O.S,uu,C,W I L, V,, and VT are the transconductance parameter, the gate-to-source voltage, and the threshold voltage, respectively. Then, the gateto-source voltage of V,,, can be rewritten as Finally, we can use Eq. (4) and Eq. (6) to determine the reference current based on the resistor R and W/L of transistor M5. M1 M2 M3 Figure 8. The layout diagram of DAC Figure 7. The biasing scheme of the current cells 3. Simulation results The layout of the proposed 12-bit loomhz currentsteering DAC has been finished as shown in Fig. 8. This circuit is simulated by HSPICE based on TSMC standard 0.35um 2p4m CMOS process [ll]. The power supply is 3.3 Volts and the output load resistor is 50 SZ. The current of LSB is designed as 3 pa.the post layout simulation results show that the static performances of DAC in DNL and INL are less than Figure 9. Post layout simulation for DNL of DAC ,., I I..

5 Table 1. Summary of the DAC performance,. *. 4. Conclusion., " ~. ~ In this paper, a 12-bit 100-MHz current-mode digital-to-analog converter (DAC) for system-on-achip (SOC) applications is presented. The SFDR is larger than 65dB for a Nyquist fimdamental signal. Based on the TSMC 0.35um 2p4m CMOS technology, the proposed DAC is simulated by HSPICE. The post layout simulation results show that the proposed DAC has the following characteristics: INL,< ko.4lsb, DNL<3.25LSB, and settling time less than 9ns. The power consumption is 47mW at the maximum rate. The chip area is 6.9mm2. In the near hture, the chip will be fabricated. After finishing the chip fabrication and testing the chip's function, we will develop the corresponding Verilog-A model of DAC in SOC applications..^ Figure 1 1. The SFDR for a 1MHz signal at a 1OOMHz update rate ^ *. " 5. References * [l] J. Vandenbussche, G. Van der Plas, et al., "Systematic Design of High-Accuracy Current-Stecring D/A Converter Macrocells for integrated VLSI System", IEEE Trans. Circuit and Syst. II, vol. 48 NO. 3, March [2] A. Torralba, R. G. Carvajal, J. Ramirez - Angulo and F. Munoz, "Output stage for low supply voltage, highperformance CMOS current mirrors," Electron. Lett. vol. 38 NO. 24 November [31 A. Van den Bosch, M. Borremans et al., "A 12-bit 2OOMHz low glitch CMOS D/A converter," IEEE 1998 Custom Integrated Circuits Con$ (CICC), May 1998, pp. Figure 12. The SFDR for a 49MHz signal at a IOOMHz update rate

6 [4] B. J. Tesch and J. C. Garcia, A Low Glitch 14-b loomhz DIA Converter, IEEE J. Solid-state Circuit, Vol. 32, pp [5] M. Gustavsson, J. J. Wilner and N. N. Tan, CMOS Data Converters For Communications. Boston, Kluwer Academic Publishers, [6] C. H. Lin and K. Bult, A lob 250Msmapleh CMOS DAC in lmm2, in Proc Int. Solid-state Circuit Con$ (ISSCC), pp , Feb [7] C. H. Lin and K. Bult A 10-b, 500-Msampleh CMOS DAC in 0.6 m2, IEEE J. Solid-state Circuits, Vol. 33, No. 12, Dec [8] A. Van den Bosch et al., A 10-bit 1-Gsamplesls nyquist current-steering CMOS DIA converter, IEEE J. Solid-state Circuits, ~01.36, pp , Mar [9] A. Van den Bosch, M. Steyaert and W. Sansen SFDRbandwidth limitations for high speed high resolution current steering cmos d/a converter, in Proc. IEEE Int. Con$ Electronics, Circuit and System (TCECS), Sept. 1999, pp [lo] B. Razavi, Principles of Data Conversion System Design, IEEE Press, ISBN [l 11 R. Gregorian, An Introduction to Mixed-,Signal IC Test and Measurement. New York, Oxford, 2001.