DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS

Transcription

1 DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS

2 DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS by Yves Geerts Alcatel Microelectronics, Belgium Michiel Steyaert KU Leuven, Belgium and Willy Sansen KU Leuven, Belgium KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

3 ebook ISBN: Print ISBN: Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print 2002 Kluwer Academic Publishers Dordrecht All rights reserved No part of this ebook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's ebookstore at:

4 Abstract Over the last decade, a vast evolution of communication systems was observed. The enormous popularity and expansion of the internet was a driving force for the development of broadband internet access in every home to cope with the increasing bandwidth requirements for multimedia applications. At the same time, wireless communication evolved from an analog network with large devices, to small and cheap handsets which are based on digital communication standards. The core of all these complex electronic systems consists of digital circuits which have a huge computational power and are implemented in CMOS technologies. The development of ever faster and more powerful digital cores opens the way to more complex systems with increasing demands for the analog part which has to provide an interfacing layer to the outside world. One of the crucial building blocks in the analog part is the Analog to Digital converter. The goal of this work is to present an architecture study of AD converters and to provide insight into a wide range of analog circuit imperfections which can limit the performance. The emphasis is put on high-speed high-resolution converters in CMOS, although the material can also be applied for other specification goals and technologies. The first part of this work takes a closer look at various architectures of AD converters. These range from single-loop to cascaded and various multi-bit topologies. The operation and several stability issues of the converters are discussed. The various topologies are optimized to obtain stable converters with a high accuracy and a clear overview is provided of the maximum achievable performance of each topology. Finally, the linearity problem of the DA converter in the feedback loop of multi-bit converters is discussed, together with possible solutions. The second part studies several design aspects of converters, with a special focus on multi-bit implementations. Various models are provided for a wide range of linear and non-linear circuit non-idealities which can degrade the performance of the converter. These models allow the designer to determine the required specifications for the different building blocks. A power estimation is presented and used to derive several design considerations. The last part discusses the systematic design and measurement results of two implementations. The first is a cascaded converter, implemented in a 3.3V standard CMOS technology. It achieves a dynamic range of 92dB for a Nyquist-rate of 2.2MHz. The second converter is a multi-bit third-order topology with Dynamic Element Matching to relax the linearity requirements for the DAC. It is implemented in a standard CMOS technology, achieves a dynamic range of 97dB and a Nyquist-rate of 2.5MHz.

5 List of Symbols and Abbreviations Abbreviations AD ADC ADSL BiCMOS bidwa C21 C211 C22 CAD CLA CMOS DA DAC DC DDS DEM DMT DR DWA DWA O2 DWArand ENOB FDM FFT FM FSM HPF IC ILA Analog-to-Digital Analog-to-Digital Converter Asymmetric Digital Subscriber Line Bipolar Complementary Metal Oxide Semiconductor Bi-Directional Data Weighted Averaging Cascaded Topology 2-1 Cascaded Topology Cascaded Topology 2-2 Computer Aided Design Clocked Averaging Complementary Metal Oxide Semiconductor Digital-to-Analog Digital-to-Analog Converter Direct Current Data Directed Scrambling Dynamic Element Matching Discrete Multi Tone Dynamic Range Input Dynamic Range Output Dynamic Range Data Weighted Averaging Second-Order Data Weighted Averaging Randomized Data Weighted Averaging Effective Number Of Bits Frequency Division Multiplexing Fast Fourier Transform Figure of Merit Finite State Machine High-Pass Filter Integrated Circuit Individual Level Averaging

6 IV ISI LPF LSB MSB MTPR NMOS NRZ OL OTA pdf PDWA PMOS POTS PROM psd QAM RZ SDR SFDR SNR SNDR SR VLSI VGA Inter Symbol Interference Low-Pass Filter Least Significant Bit Most Significant Bit Multi Tone Power Ratio n-channel MOSFET Non-Return-to-Zero code Overload level Operational Transconductance Amplifier Probability Density Function Partitioned Data Weighted Averaging p-channel MOSFET Plain Old Telephony System Programmable Read Only Memory Power Spectral Density Quadrature Amplitude Modulation Return-to-Zero code Signal-to-Distortion Ratio Spurious Free Dynamic Range Signal-to-Noise Ratio Peak Signal-to-Noise Ratio Signal-to-Noise-and-Distortion Ratio Peak Signal-to-Noise-and-Distortion Ratio Slew Rate Very Large Scale of Integration Variable Gain Amplifier List of Symbols and Abbreviations Symbols Physical q T Boltzmann's constant Elementary charge Absolute temperature Definitions Quantizer step size Settling error during the sampling or integration phase Excess noise factor phase of a two phase non overlapping clocking scheme

7 V Static error of an integrator during sampling or integration phase Standard deviation of the clock-jitter Time available to settle during sampling or integration phase Gain of the OTA Amplitude of the input signal Nominal OTA gain Current factor and threshold voltage mismatch parameters Number of bits in the quantizer Equivalent closed-loop load capacitance of the OTA during sampling or integration phase Equivalent open-loop load capacitance of the OTA during sampling or integration phase Sampling and integration capacitance Parasitic input capacitance of the OTA Load capacitance of the OTA Duty-cycle of the feedback pulse in a continuous-time converter Quantization noise error in the time domain Quantization noise error of stage r in a cascaded topology Signal bandwidth and Nyquist rate (i.e. twice the signal bandwidth) Dominant closed-loop pole of the OTA during the integration phase in Hz Capacitive feedback factors during sampling and integration phase Frequency of the input signal Sampling frequency Transistor or amplifier transconductance and output conductance Loop filter of the converter Second and third-order harmonic distortions Noise and signal transfer functions Quantizer gain Transconductance parameter of NMOS and PMOS transistor Channel length of a MOS transistor Order of the converter Number of unit capacitances connected to and respectively Quantization noise power Total number of unit capacitances Power consumption Dominant closed-loop pole of the OTA during sampling or integration phase Oversampling Ratio of a modulator Resistance in the signal path during sampling or integration phase Resistance of nmos, pmos and transmission gate Ratio of the signal to the harmonic distortion component Signal-to-Noise Ratio for a relative input signal of 0.25 Drain, gate and source voltage Drain to bulk, drain to source and gate to source voltages

8 VI List of Symbols and Abbreviations Gate-source overdrive voltage, i.e. Reference voltage of a converter Threshold voltage of nmos and pmos Channel width of a MOS transistor

9 Contents Abstract List of Symbols and Abbreviations 1 Introduction 1.1 Motivation and Applications Asymmetric Digital Subscriber Line (ADSL) Wideband Receiver 1.2 The Presented Work 2 Architecture Study of Delta-Sigma Converters Introduction Operation Principle of Delta-Sigma Converters Nyquist-Rate ADC Oversampled ADC Oversampling Combined with Noise-Shaping: a Definition of Performance Metrics for a ADC Ideal Performance of a ADC 2.3 Optimal Coefficients for Converters Single-Loop Topologies First-Order Converters Second-Order Converters Third-order Converters Fourth and Higher-Order Converters Other Single-Loop Topologies Cascaded Topologies 2.4 Performance Comparison of Topologies 2.5 Continuous-Time Implementations 2.6 Linearity Issues of Multi-Bit Converters Trimming and Analog Calibration Techniques Digital Calibration Techniques Dual-Quantization Techniques Leslie-Singh Architecture ADC I III

10 VIII Conclusion Single-Loop Dual-Quantization Architecture Cascaded Dual-Quantization Architecture Dynamic Element Matching Techniques Randomization Clocked Averaging (CLA) Individual Level Averaging (ILA) Data Weighted Averaging (DWA) Bi-directional Data Weighted Averaging (bidwa) Partitioned Data Weighted Averaging (PDWA) Data Directed Scrambling (DDS) Second-Order Data Weighted Averaging (DWA 02) Vector-Quantizer Structures Noise-Shaped DEM with Tree-Structures Comparison CONTENTS Design Considerations for Multi-Bit Introduction Clock-Jitter Nyquist-Rate AD Converters Discrete-Time Continuous-Time Converters converters Comparison Discrete-Time versus Continuous-Time Converters System Level Considerations Single Ended versus Differential Implementations Non-Ideal Switched-Capacitor Integrator Other Non-Idealities in a Switched-Capacitor Integrator Clock Feedthrough and Charge Injection Coefficient Mismatch Non-Linear Capacitances Non-Linear OTA Gain Non-Linear Switch Resistance Non-Idealities of the DAC and the Quantizer Non-Idealities of the DAC Converters Implementations of Integrators with Single-Bit and Multi-Bit Feedback Signal Swings Finite Gain of the OTA Dominant Closed-Loop Pole of the OTA Switch Resistance and Dominant Closed-Loop Pole of the OTA Slew-Rate and Dominant Closed-Loop Pole of the OTA Full Model Including Switch Resistance, Slew-Rate and Dominant Closed-Loop Pole

11 CONTENTS IX Non-Idealities of the Quantizer Noise Analysis Noise Contribution of the Different Integrators Equivalent Input Noise of a Switched-Capacitor Integrator Power Estimation and Design Considerations Conclusion Implementations Introduction A 15-bit 2.2MS/s 3.3V Cascaded converter Topology Selection and System Level Design Circuit Level Design Design of the Integrator Design of the Quantizer Design of the Clock Generator Layout and Measurement Results Converter Topology Selection and System Level Design A 16-bit 2.5 MS/s 5V Multi-Bit Circuit Level Design Implementation of the Data Weighted Averaging Algorithm Design of the Quantizer Design of the DAC and the Integrator Layout and Measurement Results Performance Comparison Conclusion A Conclusions A Switched-Capacitor Integrator Including Slew-Rate Effects A.1 Charges on the Capacitors A.2 Calculations for the Sampling Phase A.3 A.4 A.2.1 A.2.2 A.2.3 Linear Settling Slewing during an Entire Clock Phase Slewing followed by Linear Settling Calculations for the Integration Phase A.3.1 Linear Settling A.3.2 Slewing during an Entire Clock Phase A.3.3 Slewing followed by Linear Settling Conclusion Bibliography Index