Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology

Transcription

1 Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology

2 OUTLINE Understanding Fabrication Imperfections Layout of MOS Transistor Matching Theory and Mismatches Device Matching, Interdigitation and Common Centroid Layouts Interconnections, Noise and Shielding System Layout, Floor planning, Clock Design

3 Digital and Analog Transistors Digital Speed Load Driving Capability Area Optimization Analog Accurate Aspect Ratio Matching Noise Minimize Stray and Gate Resistances

4 Layout and Real Chip is Different W S W 1 S 1

5 Possible Problems Related with Fabrication Mask Production / Misalignment Lateral Diffusion Over Etching / Undercut Boundary Conditions Non Uniformity 3 D Effects

6 Mask Misalignment

7 Mask Misalignment

8 Lateral Diffusion

9 Over Etching / Undercut Effect Boundary Dependent Etching

10 Etching Variations due to Different Contact Resistance

11 3 Dimensional Effects

12 Difference between drawn and physical values

13 Outline Understanding Fabrication Imperfections Layout of MOS Transistor Matching Theory and Mismatches Device Matching, Interdigitation and Common Centroid Layouts Interconnections, Noise and Shielding System Layout, Floor planning, Clock Design

14 Forming NMOS and PMOS Transistors Ptap and Ntap is necessary to isolate transistors

15 Shallow Trench Isolation (STI)

16 Proper NTAP and PTAP Connection

17 Proper NTAP and PTAP Connection

18 Source Drain Connection

19 Multiple or Single Contact Spiking

20 Analog Devices may have large W/L ratio Drain and source resistance are reduced with contacts Gate resistance is still high Drain Bulk and Source Bulk capacitance is still high Gate capacitance is still high Transistor Folding (Parallelization)

21 Parasitic Capacitances

22 Parasitic Resistances

23 Transistor Folding (Parallelization)

24 Transistor Folding (Parallelization) Gate Resistance Drain Bulk & Drain Source Capacitance

25 Outline Understanding Fabrication Imperfections Layout of MOS Transistor Matching Theory and Mismatches Device Matching, Interdigitation and Common Centroid Layouts Interconnections, Noise and Shielding System Layout, Floor planning, Clock Design

26 Mismatch Electrical properties of two devices are generally not same even they have the same layouts This is called as Mismatch Matching two devices is very important for some analog circuits such as, differential pair devices like opamp, and etc. Some kind of mismatches can not be modeled with simulation tools Designer should be aware of this during layout design

27 Effects of Mismatch on Performance Basic operation of some circuits directly depends on matching Common mode rejection is limited Eg. Current mirrors, Analog Digital Converter In differential pairs Supply noise rejection is limited In fully differential circuits Amplifier offset and/or load mismatch degrade the performance of some circuits which contain amplifier In digital circuits Eg. band gap, LDO Clock and signal skew and memory cell matchings

28 Mismatch M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid State Circuits, vol. 24, pp , October Suppose two matched devices have parameters P1 and P2 Mismatched between these two devices is ΔP Mismatch has a Gaussian distribution, which has mean and standard deviation

29 Mismatch Systematic Mismatch Random Mismatch Mean µ(δp) Standard deviation σ(δp) Due to process variation Due to imperfect balancing in circuit and gradients Can not be eliminated totally but can be reduce significantly Can be minimized or even completely eliminated

30 Systematic Mismatch / Gradients Certain physical parameters such as temperature, process biases, mechanical stress, oxide thickness, poly silicon etch etc. may vary gradually across an IC. Since these variations can be computed mathematically, they are called as gradients. These variations can cause to systematic mismatches. Another reason of systematic mismatch is inadequate layout. Systematic mismatch can be very large and dominant. In some cases,a good way of testing systematic mismatch is power supply rejection simulation on the post layout netlist

31 Random Mismatch/Dopant Fluctuations Potential distribution of dopants in a 35nm MOSFET B.Cheng et al., The impact of random doping effects on CMOS SRAM cell, Proc. ESSCIRC, 2004, p B. Hoeneisen and C. A. Mead, Current voltage characteristics of small size MOS transistors, IEEE Trans. Electron Devices, vol. ED 19, pp , 1972

32 Random Mismatch/Pelgrom s Rule : : : : : 1 Place two devices closely 2 Apply Area Rule, increase WL

33 Random Mismatch / Some Analysis Big Transistors match better Jose Pineda de Gyvez and Hans P, Tuinhout, "Threshold Voltage Mismatch and Intra Die Leakage Current in Digital CMOS Circuits", JSSC, Vol. 39, no. I, pp , Jan Area Rule Brad Minch, 1999

34 Random Mismatch / Some Analysis

35 Why Matching?

36 Orientation Si and transistors are not perfectly isotropic Keep direction of current flow same

37 Exercise; Which layout?

38 Exercise; Which layout?

39 Exercise; Which layout? Dummy Device is added

40 Distance Effect Remember Pelgrom s Theorem, Place matched devices in close proximity

41 Over Etching/ Under cut Effect / Boundary Effect Use large W and L to reduce the effect of under cut Use dummy devices to provide same environment

42 Stress Effect There is also stress caused by metallization. Therefore do not route metal across active area, if routing is unavoidable add dummy metals so that each device sees same amount of metal

43 Oxide Thickness Devices with thinner oxide usually exhibit better matching Use minimum tox devices for best matching if the process offers a choice

44 Contacts Contacts in active gate region may cause variation in Vt. Gate contacts must be outside the active region to reduce dopant effects, stress, work function etc. Because of reliability issues use multiple contacts with exactly same number in the matched devices One contact resistance is around several ohms. Use multiple contacts reduce resistance.

45 Temperature effect Temperature gradients affect accuracy Devices need to be placed symmetrical with respect to power devices

46 Bias Effect Mismatch in the drain currents is bias dependent Vt mismatch has a larger effect at low bias levels. High Vgs V t is good for current matching. Try to keep Vds same. β mismatch dominates at high current M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid State Circuits, vol. 24, pp , October um CMOS technology

47 Current Matching / / /2 Mismatch in the (W/L) values increase W/L Mismatch in the threshold values increase overdrive voltage

48 Voltage Matching 2 / / Threshold voltage mismatch can be reduced by careful layout Second component scaled with overdrive voltage, mismatch in the load and W/L Reduce overdrive voltage Increase W/L and RL

49 Current and Voltage Matching MOS transistors can be optimized either for voltage matching or for current matching, but not for both! For current matching keep overdrive voltage large (Current mirrors) For voltage matching keep overdrive voltage smaller (Differential pair devices) Route current a long way, not voltages. IR drops can cause big mismatches

50 Check List for Matching Place the transistors in close proximity Orient transistors in the same direction Place transistor s segments in the area of low stress gradients Place transistors away from the power devices Make current or voltage matching Use dummy devices if necessary Use multiple contacts Keep the layout of transistor compact Use Common Centroid layouts for critical devices

51 Corner Simulation Some of the manufacturing limitations (some systematic mismatches) are captured in the spice transistor models For example, two of the main parameters are DL and DW which show the differences between drawn and effective length and width of transistor, respectively. Manufacturing process tolerances of these parameters are emulated in the corner case simulations Narrower L and wider W Fast corner Wider L and smaller W Slow corner

52 Corner Simulation Some companies also provide models with fast NMOS and slow PMOS FS or with slow NMOS and fast PMOS SF Some companies want that the circuit work within 3 sigma spread is applied to typical corners FF3, SS um and smaller technologies requires models for leakage. Faster process, maximum supply voltage and maximum temperature ML Maximum Leakage Typical process, typical supply voltage and typical temperature TL Typical Leakage Monte Carlo Simulation can be run to center the design.

53 Tradeoffs Increased channel length Increased circuit area Increased power dissipation Reduced speed Determine required level of matching Minimal : 3σ 10mV, 3σ 2% Unit elements, matched orientation, compact layout Moderate : 3σ 2mV,3σ Apply most of layout rules Precise : Self calibration 0.1%

54 References A. Hastings, The Art of Analog Layout, 2nd Ed. Prentice Hall, Lee Eng Han, et. Al., CMOS Transistor Layout Kung Fu, utilities.com B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid State Circuits, vol. 24, pp , October B.Cheng et al., The impact of random doping effects on CMOS SRAM cel1, Proc. ESSCIRC, 2004, p B. Hoeneisen and C. A. Mead, Current voltage characteristics of small size MOS transistors, IEEE Trans. Electron Devices, vol. ED 19, pp , 1972 Jose Pineda de Gyvez and Hans P, Tuinhout, "Threshold Voltage Mismatch and Intra Die Leakage Current in Digital CMOS Circuits", JSSC, Vol. 39, no. I, pp , Jan M. F. Lan et. al., Current Mirror Layout Strategies for Enhancing Matching Performance, Kluwer AICSP, July D. Clein, CMOS IC Layout Concepts, Methodologies, and Tools, Boston, 1999.D. Clein, CMOS IC Layout Concepts, Methodologies, and Tools, Boston, J. Franca and Y. Tsividis, editors, Design of Analog Digital VLSI Circuits For Telecommunications and Signal Processing, 2nd Ed., Prentice Hall, 1994.

55 References M. Ismail and T. Fiez editors, Analog VLSI Signal and Information Processing, McGraw Hill, M. F. Lan et. al., Current Mirror Layout Strategies for Enhancing Matching Performance, Kluwer AICSP, July F. Maloberti, Analog Design for CMOS VLSI Systems, Springer US S. Palermo, Analog VLSI Circuit Design Course Slides S. Hu, Clock Network Synthesis Course Slides Delbruck, Indiveri, Liu, Transistor Mismatch and Layout Techniques Mai, alon, Labonte, Analog Layout H. Luong, Analog Layout Techniques B. Boser, Device Matching Mechanisms F. Yuan, Analog CMOS Integrated Circuits Course, MOS Device Layout Techniques Slides J. Ghosh, Advanced VLSI Design Lab, Layout of Analog Circuits Slides H. Aboushady, CMOS Process Technology Course Slides G. Wang, Layout for Analog Circuits