Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o.

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1 Layout of a Inverter Topic 3 CMOS Fabrication Process V DD Q p Peter Cheung Department of Electrical & Electronic Engineering Imperial College London v i v o Q n URL: p.cheung@ic.ac.uk GND Lecture 3-1 Lecture 3-2 The CMOS Process - photolithography (1) The CMOS Process - photolithography (2) (a) Bare silicon wafer (d) Expose resist to UV light through a MASK (f) Etch away oxide (b) Grow Oxide layer ~ 1µm (g) Remove remaining resist (c) Spin on photoresist photoresist (e) Remove unexposed resist Lecture 3-3 Lecture 3-4

2 Mask 1: N-well Diffusion Mask 2: Define Active Regions is etched using Mask 1. Phosphorous Diffusion Mask 2 creates the active regions where the MOSFETs will be placed Phosphorous is diffused into the unmasked regions of silicon creating an n- well for the fabrication of p-channel devices The thick oxide regions provides isolation between the MOSFETs A thick field oxide is grown using a contruction technique called Local Oxidation Of Silicon (LOCOS). Lecture 3-5 Lecture 3-6 Mask 3: Polysilicon Gate Mask 4: n+ Diffusion A high quality thin oxide is grown in the active area (~100A->300A) Mask 3 is used to deposit the polysilicon gate (most critical step) Thin Oxide The polysilicon layer is usually arsenic doped (n-type). The photolithography in this step is the most demanding since it requires the finest resolution to create the narrow MOS channels. Mask 4 is used to control a heavy arsenic implant and create the source and drain of the n-channel devices. This is a self-aligned structure. Arsenic Implant The polysilicon gate acts like a barrier for this implant to protect the channel region. n + n + n + Lecture 3-7 Lecture 3-8

3 Mask 5: p+ Diffusion Mask 6: Contact Holes Mask 5 is used to control a heavy Boron implant and create the source and drain of the n-channel devices. This is a self-aligned structure. Boron Implant A thin layer of oxide is deposited over the entire wafer Mask 6 is used to pattern the contact holes Etching opens the holes. oxide The polysilicon gate acts like a barrier for this implant to protect the channel region. Etched contact holes p + n + n + Lecture 3-9 Lecture 3-10 Mask 7: Metalization Cross section of a CMOS Inverter A thin layer of aluminum is evaporated or sputtered onto the wafer. Mask 7 is used to pattern the interconnection. v i v o V DD Aluminum Interconnection p + n + n + Source-Body Connection Q n p + p + Q p n + Source-Body Connection Lecture 3-11 Lecture 3-12

4 Physical Layout of an Inverter Dimension of transistors PMOS active region VDD L Qp NMOS active region n+ W n+ diffusion p+ diffusion vo vi Lecture 3-13 Photo cross-section of a transistor W p+ p+ Poly Drain Source Drain n-channel MOSFET GND n+ Gate Qn Contact Hole Poly Source Poly 1 (poly-si gate) Metal 1 L Gate p-channel MOSFET Lecture 3-14 Advanced metalization with polishing Lecture 3-15 Lecture 3-16

5 Latch-up problem (1) Latch-up (con t)! As shown above, the p+ region of the p-transistor, the and the p- substrate form a parasitic pnp transistor T1.! The n- well, the p- substrate and the p+ source of the n-transistor forms another parasitic npn transistor T2.! There exists two resistors Rw and Rs due to the resistive drop in the well area and the substrate area.! T1 and T2 form a thyristor circuit.! If Rw and/or Rs are not 0, and for some reason (power-up, current spike etc), T1 or T2 are forced to conduct, Vdd will be shorted to Gnd through the small resistances and the transistors.! Once the circuit is 'fired', both transistors will remain conducting due to the voltage drop across Rw and Rs. The only way to get out of this mode is to turn the power off.! This condition is known as latch-up.! To avoid latch-up, substrate-taps (tied to Gnd) and well-taps (tied to Vdd) are inserted as frequently as possible. This has the effect of shorting out Rw and Rs. Lecture 3-17 Lecture 3-18