FinFET-based Design for Robust Nanoscale SRAM
|
|
- Jewel Spencer
- 5 years ago
- Views:
Transcription
1 FinFET-based Design for Robust Nanoscale SRAM Prof. Tsu-Jae King Liu Dept. of Electrical Engineering and Computer Sciences University of California at Berkeley Acknowledgements Prof. Bora Nikoli Zheng Guo, Sriram Balasubramanian, Andrew Carlson, Radu Zlatanovici 1 Outline Background / Motivation FinFET-based SRAM cell designs 6-T SRAM write-ability considerations Summary 2 1
2 Challenges for Bulk-Si MOSFET Scaling The traditional approach to transistor scaling is reaching fundamental limits oxide scaling Source Shallow junctions Channel engineering L g Halo Doping Drain Issues for scaling L g to below 20 nm: Leakage SiO 2 Incommensurate gains in I ON V T variation Source Drain A. Brown et al., IEEE Trans. Nanotechnology, p. 195, Thin-Body MOSFET Structures Short-channel effects are suppressed with thin body Channel can be lightly doped higher carrier mobility T OX scaling is not needed reliability issues are assuaged Double-gate structure is most scalable (to L g <10nm) L g Source Drain T Si Buried Oxide Substrate Ultra-Thin Body (UTB) Source Drain Double- (DG) T Si 4 2
3 Circuit-Level Benefits of Thin-Body MOSFETs Steep sub-threshold swing High drive current Low parasitic capacitances negligible C junc and C depl Better intrinsic delay FO4 Inverter Delay [ps] 10 1 Bulk UTB DG 45% faster I off = 200nA/ m L gate =35nm 53% faster I off = 2nA/ m Benefits are enhanced for low-power applications 5 Double- FinFET L g Drain L g Drain T Si Source Drain Source Source Planar Double- FET (90 o rotation) Fin Height H FIN = W/2 Fin Width = T Si FinFET D. Hisamoto et al., IEDM, 1998 N. Lindert et al., IEEE Electron Device Letters, p.487, 2001 Rotation allows for self-aligned gate electrodes FinFET layout is similar to that of a planar FET 6 3
4 Bulk-Si FinFETs C.-H. Lee et al., Symp. VLSI Technology Digest, pp , 2004 FinFETs can be made on bulk-si wafers lower cost improved thermal conduction to mitigate self-heating effects integration with planar bulk-si MOSFETs is possible 7 FinFETs for Digital ICs Significant barriers to adoption of FinFET technology for general purpose logic exist: V T tuning (gate work function engineering?) lack of a standard model and design libraries but these are not issues for SRAM, which faces severe challenges for scaling beyond the hp45nm node V T variability standby power 8 4
5 Outline Background / Motivation FinFET-based SRAM cell designs Z. Guo et al., Int l Symposium on Low Power Electronics and Design, T cells 4-T cells 6-T SRAM write-ability considerations Summary 9 6-FinFET SRAM Cell Access Cell Layout NPD Load FinFET PARAMETER GATE LENGTH WL GATE-OX. THICKNESS V DD FIN WIDTH VALUE Load 22nm 11Å 15nm FIN HEIGHT BODY DOPING 30nm Access 1E16cm nm GATE WORKFUNCTION NPD BL V DD 4.75eV 1.0V BL 755 nm 1-Fin NPD: 0.36 m 2, 175mV SNM 2-Fin NPD: 0.42 m 2, 240mV SNM (36% SNM improvement w/ 17% area penalty) 10 5
6 6-T SRAM Design: bulk-si vs. FinFET Bulk-Si: cell area = 0.46 m 2 FinFET: cell area = 0.36 m 2 Read/Write Margin (mv) Read/Write Margin (mv) Cell Beta Ratio # Fins on NPD Write Margin Read Margin Write Margin Read Margin 11 Independent Operation The front and back gate electrodes can be isolated by a masked etch, to allow for separate biasing 1 is used for switching 2 is used for V T control Back-d FET: Drain 1 2 Source 12 6
7 SRAM Cell w/ Dynamic Feedback Circuit Schematic SNM is increased Soft-error immunity is enhanced! Word-line capacitance is reduced; I READ is unaffected 13 Selective Separation SEM picture of 6-FinFET SRAM cell after timed gate separation etch Access Connected s NPD Load Separated s Access Access transistor gates are selectively separated dynamic feedback 14 7
8 SRAM Cell w/ Dynamic Feedback (cont d) Cell Layout No area penalty is incurred to implement feedback Read vs. write margin trade-off is adjusted by M 15 4-T SRAM Design: bulk-si vs. FinFET 16 8
9 4-FinFET SRAM Cell SEM picture of 4-FinFET SRAM cell after gate patterning T Si = 30 nm, L g = 70 nm Access gate layer NPD fin / active layer NPD Access 17 Impact of Process Variations Comparison of SRAM SNM Distributions Mixed-mode & MC simulations: FinFET variations are due to parameter variations 3 Lg = 3 TSi = 10%L g Bulk-Si MOSFET variations are due to random dopant fluctuations only FinFET-based SRAM designs shows less variability 18 9
10 Systematic vs. Random Variations FinFET SRAM 6-T DG 1-Fin M =4.65eV Systematic variations have less impact than random variations SNM variation due to random mismatch in L g and T Si is ~1.8x more than that due to systematic variations 19 Outline Background / Motivation FinFET-based SRAM cell designs 6-T SRAM write-ability considerations A. Carlson et al., IEEE SOI Conference, 2006 Impact of dynamic feedback Improvement via separate write word line Summary 20 10
11 Measuring Write-ability C. Wann et al., IEEE VLSI-TSA, pp , 2005 Write functionality is increasingly important Scaling reduces NMOS/PMOS drive strength ratio Write-ability is more sensitive than SNM to V DD When biased as shown, the minimum current I W is a measure of write-ability I W 0 cannot write a zero 21 Dynamic Feedback Better Write-ability Nominal Iw (ua) M=4.65eV Vch (V) I W is increased at low V DD with dynamic feedback (Note: M values were selected so that SNM = V DD =0.7V) 20 VDD (V) Ich (ua) M=4.82eV Iw 22 11
12 Pull-Up (Load) Write Gating Connect one gate of each load transistor to a write wordline to assist with write Impact is complementary to that of dynamic feedback 3 CH 5 6 WWL 1 2 CL 4 Nominal Iw (ua) Ich (ua) 20 Improved lower V 0 DD Vch (V) PUWG + PGFB PUWG Conv VDD (V) No area penalty! 23 Dynamic feedback + PUWG can improve yield SNM Cell Sigma PUWG+PGFB PUWG PGFB Conv V DD (V) Iw Cell Sigma PUWG+PGFB PUWG PGFB Conv V DD (V) Projected yield is greatest when dynamic feedback and PUWG designs are combined Enables 6-sigma design at low V DD 24 12
13 Outline Background / Motivation FinFET-based SRAM cell designs 6-T SRAM write-ability considerations Summary 25 Summary The FinFET structure offers improved I ON vs. I OFF and immunity to statistical dopant fluctuations FinFETs can be fabricated alongside planar bulk-si MOSFETs with minimal added process complexity attractive for embedded SRAM application The FinFET s capability for back-gated operation can be leveraged to improve cell stability and write-ability, to enable 6-T SRAM technology scaling well beyond the hp45nm node 26 13
14 This document was created with Win2PDF available at The unregistered version of Win2PDF is for evaluation or non-commercial use only.
Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018
Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018 ECE 658 Sp 2018 Semiconductor Materials and Device Characterizations OUTLINE Background FinFET Future Roadmap Keeping up w/ Moore s Law
More informationDG-FINFET LOGIC DESIGN USING 32NM TECHNOLOGY
International Journal of Knowledge Management & e-learning Volume 3 Number 1 January-June 2011 pp. 1-5 DG-FINFET LOGIC DESIGN USING 32NM TECHNOLOGY K. Nagarjuna Reddy 1, K. V. Ramanaiah 2 & K. Sudheer
More informationFINFET BASED SRAM DESIGN FOR LOW POWER APPLICATIONS
FINFET BASED SRAM DESIGN FOR LOW POWER APPLICATIONS SHRUTI OZA BVU College of Engineering, Pune-43 E-mail: Shruti.oza11@gmail.com Abstract- Industry demands Low-Power and High- Performance devices now-a-days.
More informationSemiconductor Memory: DRAM and SRAM. Department of Electrical and Computer Engineering, National University of Singapore
Semiconductor Memory: DRAM and SRAM Outline Introduction Random Access Memory (RAM) DRAM SRAM Non-volatile memory UV EPROM EEPROM Flash memory SONOS memory QD memory Introduction Slow memories Magnetic
More informationLow Transistor Variability The Key to Energy Efficient ICs
Low Transistor Variability The Key to Energy Efficient ICs 2 nd Berkeley Symposium on Energy Efficient Electronic Systems 11/3/11 Robert Rogenmoser, PhD 1 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc.
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 11/6/2007 MOSFETs Lecture 6 BJTs- Lecture 1 Reading Assignment: Chapter 10 More Scalable Device Structures Vertical Scaling is important. For example,
More informationFinFET Devices and Technologies
FinFET Devices and Technologies Jack C. Lee The University of Texas at Austin NCCAVS PAG Seminar 9/25/14 Material Opportunities for Semiconductors 1 Why FinFETs? Planar MOSFETs cannot scale beyond 22nm
More informationSession 3: Solid State Devices. Silicon on Insulator
Session 3: Solid State Devices Silicon on Insulator 1 Outline A B C D E F G H I J 2 Outline Ref: Taurand Ning 3 SOI Technology SOl materials: SIMOX, BESOl, and Smart Cut SIMOX : Synthesis by IMplanted
More informationLecture 27 ANNOUNCEMENTS. Regular office hours will end on Monday 12/10 Special office hours will be posted on the EE105 website
Lecture 27 ANNOUNCEMENTS Regular office hours will end on Monday 12/10 Special office hours will be posted on the EE105 website Final Exam Review Session: Friday 12/14, 3PM, HP Auditorium Video will be
More informationFinFET-Based SRAM Design
FinFET-Based SRAM Design Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King, Borivoje Nikolić Department of Electrical Engineering and Computer Sciences, University of California, Berkeley,
More informationLecture #29. Moore s Law
Lecture #29 ANNOUNCEMENTS HW#15 will be for extra credit Quiz #6 (Thursday 5/8) will include MOSFET C-V No late Projects will be accepted after Thursday 5/8 The last Coffee Hour will be held this Thursday
More informationADVANCED MATERIALS AND PROCESSES FOR NANOMETER-SCALE FINFETS
ADVANCED MATERIALS AND PROCESSES FOR NANOMETER-SCALE FINFETS Tsu-Jae King, Yang-Kyu Choi, Pushkar Ranade^ and Leland Chang Electrical Engineering and Computer Sciences Dept., ^Materials Science and Engineering
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 11/01/2007 MOSFETs Lecture 5 Announcements HW7 set is due now HW8 is assigned, but will not be collected/graded. MOSFET Technology Scaling Technology
More information45nm Bulk CMOS Within-Die Variations. Courtesy of C. Spanos (UC Berkeley) Lecture 11. Process-induced Variability I: Random
45nm Bulk CMOS Within-Die Variations. Courtesy of C. Spanos (UC Berkeley) Lecture 11 Process-induced Variability I: Random Random Variability Sources and Characterization Comparisons of Different MOSFET
More informationLow-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering
Low-Power VLSI Seong-Ook Jung 2013. 5. 27. sjung@yonsei.ac.kr VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Contents 1. Introduction 2. Power classification & Power performance
More informationA BRIEF STUDY ON CHALLENGES OF MOSFET AND EVOLUTION OF FINFETS
A BRIEF STUDY ON CHALLENGES OF MOSFET AND EVOLUTION OF FINFETS ABSTRACT J.Shailaja 1, Y.Priya 2 1 ECE Department, Sphoorthy Engineering College (India) 2 ECE,Sphoorthy Engineering College, (India) The
More informationAdvanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm
EE241 - Spring 20 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends and Features of Modern Technologies Announcements No office hour next Monday Extra office hour Tuesday 2-3pm 2 1 Outline
More informationPerformance Comparison of CMOS and Finfet Based Circuits At 45nm Technology Using SPICE
RESEARCH ARTICLE OPEN ACCESS Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology Using SPICE Mugdha Sathe*, Dr. Nisha Sarwade** *(Department of Electrical Engineering, VJTI, Mumbai-19)
More informationDesign of Nano-Electro Mechanical (NEM) Relay Based Nano Transistor for Power Efficient VLSI Circuits
Design of Nano-Electro Mechanical (NEM) Relay Based Nano Transistor for Power Efficient VLSI Circuits Arul C 1 and Dr. Omkumar S 2 1 Research Scholar, SCSVMV University, Kancheepuram, India. 2 Associate
More informationAnalysis and Simulation of a Low-Leakage 6T FinFET SRAM Cell Using MTCMOS Technique at 45 nm Technology
Analysis and Simulation of a Low-Leakage 6T FinFET SRAM Cell Using MTCMOS Technique at 45 nm Technology Shyam Sundar Sharma 1, Ravi Shrivastava 2, Nikhil Saxenna 3 1Research Scholar Dept. of ECE, ITM,
More informationFinFET vs. FD-SOI Key Advantages & Disadvantages
FinFET vs. FD-SOI Key Advantages & Disadvantages Amiad Conley Technical Marketing Manager Process Diagnostics & Control, Applied Materials ChipEx-2014, Apr 2014 1 Moore s Law The number of transistors
More informationDesign and analysis of 6T SRAM cell using FINFET at Nanometer Regime Monali S. Mhaske 1, Prof. S. A. Shaikh 2
Design and analysis of 6T SRAM cell using FINFET at Nanometer Regime Monali S. Mhaske 1, Prof. S. A. Shaikh 2 1 ME, Dept. Of Electronics And Telecommunication,PREC, Maharashtra, India 2 Associate Professor,
More informationThe 3 D Tri Gate transistor is a variant of the FinFET developed at UC Berkeley, and is being used in Intel s 22nmgeneration. microprocessors.
On May 4, 2011, Intel Corporation announced what it called the most radical shift in semiconductor technology in 50 years. A new 3 dimensional transistor design will enable the production of integrated
More informationParameter Optimization Of GAA Nano Wire FET Using Taguchi Method
Parameter Optimization Of GAA Nano Wire FET Using Taguchi Method S.P. Venu Madhava Rao E.V.L.N Rangacharyulu K.Lal Kishore Professor, SNIST Professor, PSMCET Registrar, JNTUH Abstract As the process technology
More informationITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations
Workshop on Frontiers of Extreme Computing Santa Cruz, CA October 24, 2005 ITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations Peter M. Zeitzoff Outline Introduction MOSFET scaling and
More informationUltra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM
[ 2007 International Conference on VLSI Design ] Jan. 9, 2007 Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, *Akira
More informationLecture 33 - The Short Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 30, 2007
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 33-1 Lecture 33 - The Short Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 30, 2007 Contents: 1. MOSFET scaling
More informationFinal Exam Topics. IC Technology Advancement. Microelectronics Technology in the 21 st Century. Intel s 90 nm CMOS Technology. 14 nm CMOS Transistors
ANNOUNCEMENTS Final Exam: When: Wednesday 12/10 12:30-3:30PM Where: 10 Evans (last names beginning A-R) 60 Evans (last names beginning S-Z) Comprehensive coverage of course material Closed book; 3 sheets
More informationAtomic-layer deposition of ultrathin gate dielectrics and Si new functional devices
Atomic-layer deposition of ultrathin gate dielectrics and Si new functional devices Anri Nakajima Research Center for Nanodevices and Systems, Hiroshima University 1-4-2 Kagamiyama, Higashi-Hiroshima,
More informationECE 340 Lecture 37 : Metal- Insulator-Semiconductor FET Class Outline:
ECE 340 Lecture 37 : Metal- Insulator-Semiconductor FET Class Outline: Metal-Semiconductor Junctions MOSFET Basic Operation MOS Capacitor Things you should know when you leave Key Questions What is the
More informationImproving CMOS Speed and Switching Energy with Vacuum-Gap Structures
Improving CMOS Speed and Switching Energy with Vacuum-Gap Structures Chenming Hu and Je Min Park Univ. of California, Berkeley -1- Outline Introduction Background and Motivation MOSFETs with Vacuum-Spacer
More informationA Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura System LSI Research Center Kyushu
More informationAnalysis of Low Power-High Speed Sense Amplifier in Submicron Technology
Voltage IJSRD - International Journal for Scientific Research & Development Vol. 2, Issue 02, 2014 ISSN (online): 2321-0613 Analysis of Low Power-High Speed Sense Amplifier in Submicron Technology Sunil
More informationSession 10: Solid State Physics MOSFET
Session 10: Solid State Physics MOSFET 1 Outline A B C D E F G H I J 2 MOSCap MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor: Al (metal) SiO2 (oxide) High k ~0.1 ~5 A SiO2 A n+ n+ p-type Si (bulk)
More informationDrain. Drain. [Intel: bulk-si MOSFETs]
1 Introduction For more than 40 years, the evolution and growth of very-large-scale integration (VLSI) silicon-based integrated circuits (ICs) have followed from the continual shrinking, or scaling, of
More informationDesign of Optimized Digital Logic Circuits Using FinFET
Design of Optimized Digital Logic Circuits Using FinFET M. MUTHUSELVI muthuselvi.m93@gmail.com J. MENICK JERLINE jerlin30@gmail.com, R. MARIAAMUTHA maria.amutha@gmail.com I. BLESSING MESHACH DASON blessingmeshach@gmail.com.
More informationInternational Journal of Scientific & Engineering Research, Volume 6, Issue 2, February-2015 ISSN
Performance Evaluation and Comparison of Ultra-thin Bulk (UTB), Partially Depleted and Fully Depleted SOI MOSFET using Silvaco TCAD Tool Seema Verma1, Pooja Srivastava2, Juhi Dave3, Mukta Jain4, Priya
More information3-D Modelling of the Novel Nanoscale Screen-Grid Field Effect Transistor (SGFET)
3-D Modelling of the Novel Nanoscale Screen-Grid Field Effect Transistor (SGFET) Pei W. Ding, Kristel Fobelets Department of Electrical Engineering, Imperial College London, U.K. J. E. Velazquez-Perez
More informationBody-Biased Complementary Logic Implemented Using AlN Piezoelectric MEMS Switches
University of Pennsylvania From the SelectedWorks of Nipun Sinha 29 Body-Biased Complementary Logic Implemented Using AlN Piezoelectric MEMS Switches Nipun Sinha, University of Pennsylvania Timothy S.
More informationEnabling Breakthroughs In Technology
Enabling Breakthroughs In Technology Mike Mayberry Director of Components Research VP, Technology and Manufacturing Group Intel Corporation June 2011 Defined To be defined Enabling a Steady Technology
More informationDepletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET
Ch. 13 MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor : I D D-mode E-mode V g The gate oxide is made of dielectric SiO 2 with e = 3.9 Depletion-mode operation ( 공핍형 ): Using an input gate voltage
More informationDouble-Gate SOI Devices for Low-Power and High-Performance Applications
Double-Gate SOI Devices for Low-Power and High-Performance Applications Kaushik Roy*, Hamid Mahmoodi**, Saibal Mukhopadhyay*, Hari Ananthan*, Aditya Bansal*, and Tamer Cakici* *Dept. of Electrical and
More informationINTERNATIONAL JOURNAL OF APPLIED ENGINEERING RESEARCH, DINDIGUL Volume 1, No 3, 2010
Low Power CMOS Inverter design at different Technologies Vijay Kumar Sharma 1, Surender Soni 2 1 Department of Electronics & Communication, College of Engineering, Teerthanker Mahaveer University, Moradabad
More informationDESIGN & OPTIMIZATION OF FINFET BASED DOMINO LOGIC CIRCUIT Akshay Angaria 1 *, Umesh Dutta 2, Sneha Arora 3 1,3
DESIGN & OPTIMIZATION OF FINFET BASED DOMINO LOGIC CIRCUIT Akshay Angaria 1 *, Umesh Dutta 2, Sneha Arora 3 1,3 M.tech Scholar VLSI Design & Embedded System, 2 Assistant Professor & Deputy Director MRIIC,
More informationEE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 23 p. 1/16 EE 42/100 Lecture 23: CMOS Transistors and Logic Gates ELECTRONICS Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad University
More informationECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices
ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor
More informationRecord I on (0.50 ma/μm at V DD = 0.5 V and I off = 100 na/μm) 25 nm-gate-length ZrO 2 /InAs/InAlAs MOSFETs
Record I on (0.50 ma/μm at V DD = 0.5 V and I off = 100 na/μm) 25 nm-gate-length ZrO 2 /InAs/InAlAs MOSFETs Sanghoon Lee 1*, V. Chobpattana 2,C.-Y. Huang 1, B. J. Thibeault 1, W. Mitchell 1, S. Stemmer
More informationEE E6930 Advanced Digital Integrated Circuits. Spring, 2002 Lecture 12. SOI Devices and Circuits
EE E6930 Advanced Digital Integrated Circuits Spring, 2002 Lecture 12. SOI Devices and Circuits References CBF, Chapter 5 On-line course reader on SOI Many slides borrowed from C. T. Chuang s 2001 tutorial
More informationISSN: [Soni* et al., 6(4): April, 2017] Impact Factor: 4.116
IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY A COMPARITIVELY ANALISIS OF VARIOUS CMOS FINFET STRUCTURE Ragini Soni*, Mrs. Jyotsna Sagar * M.Tech Student (VLSI ) Asst. Professor,
More informationDUAL MATERIAL PILE GATE APPROACH FOR LOW LEAKAGE FINFET. Sanjay S. Chopade 1*, Dinesh V. Padole 1
International Journal of Technology (2017) 1: 168-176 ISSN 2086-9614 IJTech 2017 DUAL MATERIAL PILE GATE APPROACH FOR LOW LEAKAGE FINFET Sanjay S. Chopade 1*, Dinesh V. Padole 1 1 Department of Electronics
More informationJournal of Electron Devices, Vol. 20, 2014, pp
Journal of Electron Devices, Vol. 20, 2014, pp. 1786-1791 JED [ISSN: 1682-3427 ] ANALYSIS OF GIDL AND IMPACT IONIZATION WRITING METHODS IN 100nm SOI Z-DRAM Bhuwan Chandra Joshi, S. Intekhab Amin and R.
More informationDesign and Performance Analysis of SOI and Conventional MOSFET based CMOS Inverter
I J E E E C International Journal of Electrical, Electronics ISSN No. (Online): 2277-2626 and Computer Engineering 3(2): 138-143(2014) Design and Performance Analysis of SOI and Conventional MOSFET based
More informationMicroelectronics, BSc course
Microelectronics, BSc course MOS circuits: CMOS circuits, construction http://www.eet.bme.hu/~poppe/miel/en/14-cmos.pptx http://www.eet.bme.hu The abstraction level of our study: SYSTEM + MODULE GATE CIRCUIT
More informationEEC 216 Lecture #8: Leakage. Rajeevan Amirtharajah University of California, Davis
EEC 216 Lecture #8: Leakage Rajeevan Amirtharajah University of California, Davis Outline Announcements Review: Low Power Interconnect Finish Lecture 7 Leakage Mechanisms Circuit Styles for Low Leakage
More information3. COMPARING STRUCTURE OF SINGLE GATE AND DOUBLE GATE MOSFET WITH DESIGN AND CURVE
P a g e 80 Available online at http://arjournal.org APPLIED RESEARCH JOURNAL RESEARCH ARTICLE ISSN: 2423-4796 Applied Research Journal Vol. 3, Issue, 2, pp.80-86, February, 2017 COMPARATIVE STUDY ON SINGLE
More informationPower MOSFET Zheng Yang (ERF 3017,
ECE442 Power Semiconductor Devices and Integrated Circuits Power MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Evolution of low-voltage (
More informationTHRESHOLD VOLTAGE CONTROL SCHEMES
THRESHOLD VOLTAGE CONTROL SCHEMES IN FINFETS V. Narendar 1, Ramanuj Mishra 2, Sanjeev Rai 3, Nayana R 4 and R. A. Mishra 5 Department of Electronics & Communication Engineering, MNNIT-Allahabad Allahabad-211004,
More informationLow Power, Area Efficient FinFET Circuit Design
Low Power, Area Efficient FinFET Circuit Design Michael C. Wang, Princeton University Abstract FinFET, which is a double-gate field effect transistor (DGFET), is more versatile than traditional single-gate
More informationA Novel Radiation Tolerant SRAM Design Based on Synergetic Functional Component Separation for Nanoscale CMOS.
A Novel Radiation Tolerant SRAM Design Based on Synergetic Functional Component Separation for Nanoscale CMOS. Abstract This paper presents a novel SRAM design for nanoscale CMOS. The new design addresses
More informationJack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php
More informationAlternatives to standard MOSFETs. What problems are we really trying to solve?
Alternatives to standard MOSFETs A number of alternative FET schemes have been proposed, with an eye toward scaling up to the 10 nm node. Modifications to the standard MOSFET include: Silicon-in-insulator
More informationPerformance of Low Power SRAM Cells On SNM and Power Dissipation
Performance of Low Power SRAM Cells On SNM and Power Dissipation Kanika Kaur 1, Anurag Arora 2 KIIT College of Engineering, Gurgaon, Haryana, INDIA Abstract: Over the years, power requirement reduction
More informationIII-V CMOS: Quo Vadis?
III-V CMOS: Quo Vadis? J. A. del Alamo, X. Cai, W. Lu, A. Vardi, and X. Zhao Microsystems Technology Laboratories Massachusetts Institute of Technology Compound Semiconductor Week 2018 Cambridge, MA, May
More informationPartially-insulated MOSFET (PiFET) and Its Application to DRAM Cell Transistor
30 CHANG WOO OH et al : PARTIALLY-INSULATED MOSFET (PIFET) AND ITS APPLICATION TO DRAM CELL TRANSISTOR Partially-insulated MOSFET (PiFET) and Its Application to DRAM Cell Transistor Chang Woo Oh, Sung
More informationReducing Transistor Variability For High Performance Low Power Chips
Reducing Transistor Variability For High Performance Low Power Chips HOT Chips 24 Dr Robert Rogenmoser Senior Vice President Product Development & Engineering 1 HotChips 2012 Copyright 2011 SuVolta, Inc.
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2019 Khanna Jack Keil Wolf Lecture http://www.ese.upenn.edu/about-ese/events/wolf.php
More informationSemiconductor TCAD Tools
Device Design Consideration for Nanoscale MOSFET Using Semiconductor TCAD Tools Teoh Chin Hong and Razali Ismail Department of Microelectronics and Computer Engineering, Universiti Teknologi Malaysia,
More informationHigh Performance and Low Leakage 3DSOI Fin-FET SRAM
American Journal of Engineering and Applied Sciences Original Research Paper High Performance and Low Leakage 3DSOI Fin-FET SRAM 1 Sudha, D., 2 Ch. Santhiraniand 3 Sreenivasa Rao Ijjada 1 Departmet of
More informationINTRODUCTION TO MOS TECHNOLOGY
INTRODUCTION TO MOS TECHNOLOGY 1. The MOS transistor The most basic element in the design of a large scale integrated circuit is the transistor. For the processes we will discuss, the type of transistor
More informationA Process Variation Tolerant Self-Compensation Sense Amplifier Design
University of Massachusetts Amherst ScholarWorks@UMass Amherst Masters Theses 9 - February 24 28 A Process Variation Tolerant Self-Compensation Sense Amplifier Design Aarti Choudhary University of Massachusetts
More informationTrends and Challenges in VLSI Technology Scaling Towards 100nm
Trends and Challenges in VLSI Technology Scaling Towards 100nm Stefan Rusu Intel Corporation stefan.rusu@intel.com September 2001 Stefan Rusu 9/2001 2001 Intel Corp. Page 1 Agenda VLSI Technology Trends
More informationBridging the Gap between Dreams and Nano-Scale Reality
Bridging the Gap between Dreams and Nano-Scale Reality Ban P. Wong Design Methodology, Chartered Semiconductor wongb@charteredsemi.com 28 July 2006 Outline Deficiencies in Boolean-based Design Rules in
More informationEigen # Hole s Wavefunctions, E-k and Equi-Energy Contours from a P-FinFET. Lecture 5
Eigen # Gate Gate Hole s Wavefunctions, E-k and Equi-Energy Contours from a P-FinFET Lecture 5 Thin-Body MOSFET Carrier Transport quantum confinement effects low-field mobility: Orientation and Si Thickness
More informationThe Path Toward Efficient Nano-Mechanical Circuits and Systems
The Path Toward Efficient Nano-Mechanical Circuits and Systems http://www.chi-yun.com/blog/wp-content/uploads/2008/10/ba-road-less.jp Tsu-Jae King Liu 1 Elad Alon 1, Vladimir Stojanovic 2, Dejan Markovic
More informationCHAPTER 2 LITERATURE REVIEW
8 CHAPTER 2 LITERATURE REVIEW 2.1. INTRODUCTION In order to meet the need for low Off current while keeping power consumption under control, the semiconductor industry is working to introduce high-k gate
More informationReducing the Sub-threshold and Gate-tunneling Leakage of SRAM Cells using Dual-V t and Dual-T ox Assignment
Reducing the Sub-threshold and Gate-tunneling Leakage of SRAM Cells using Dual-V t and Dual-T ox Assignment Behnam Amelifard Department of EE-Systems University of Southern California Los Angeles, CA (213)
More informationBeyond Transistor Scaling: New Devices for Ultra Low Energy Information Processing
Beyond Transistor Scaling: New Devices for Ultra Low Energy Information Processing Prof. Tsu Jae King Liu Department of Electrical Engineering and Computer Sciences University of California, Berkeley,
More informationProcess Variability and the SUPERAID7 Approach
Process Variability and the SUPERAID7 Approach Jürgen Lorenz Fraunhofer Institut für Integrierte Systeme und Bauelementetechnologie IISB, Erlangen, Germany ESSDERC/ ESSCIRC Workshop Process Variations
More informationDesign and Analysis of Sram Cell for Reducing Leakage in Submicron Technologies Using Cadence Tool
IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE) e-issn: 2278-1676,p-ISSN: 2320-3331, Volume 10, Issue 2 Ver. II (Mar Apr. 2015), PP 52-57 www.iosrjournals.org Design and Analysis of
More informationAE53/AC53/AT53/AE103 ELECT. DEVICES & CIRCUITS DEC 2015
Q.2 a. By using Norton s theorem, find the current in the load resistor R L for the circuit shown in Fig.1. (8) Fig.1 IETE 1 b. Explain Z parameters and also draw an equivalent circuit of the Z parameter
More informationThis Week s Subject. DRAM & Flexible RRAM. p-channel MOSFET (PMOS) CMOS: Complementary Metal Oxide Semiconductor
DRAM & Flexible RRAM This Week s Subject p-channel MOSFET (PMOS) CMOS: Complementary Metal Oxide Semiconductor CMOS Logic Inverter NAND gate NOR gate CMOS Integration & Layout GaAs MESFET (JFET) 1 Flexible
More informationMULTI-PORT MEMORY DESIGN FOR ADVANCED COMPUTER ARCHITECTURES. by Yirong Zhao Bachelor of Science, Shanghai Jiaotong University, P. R.
MULTI-PORT MEMORY DESIGN FOR ADVANCED COMPUTER ARCHITECTURES by Yirong Zhao Bachelor of Science, Shanghai Jiaotong University, P. R. China, 2011 Submitted to the Graduate Faculty of the Swanson School
More informationPrepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology
Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology OUTLINE Understanding Fabrication Imperfections Layout of MOS Transistor Matching Theory and Mismatches Device Matching, Interdigitation
More informationGlasgow eprints Service
Cheng, B. and Roy, S. and Asenov, A. (2004) The impact of random doping effects on CMOS SRAM cell. In, 30th European Solid-State Circuits Conference (ESSCIRC 2004)., 21-23 September 2004, pages pp. 219-222,
More information+1 (479)
Introduction to VLSI Design http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable
More information3084 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 60, NO. 4, AUGUST 2013
3084 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 60, NO. 4, AUGUST 2013 Dummy Gate-Assisted n-mosfet Layout for a Radiation-Tolerant Integrated Circuit Min Su Lee and Hee Chul Lee Abstract A dummy gate-assisted
More informationTunneling Field Effect Transistors for Low Power ULSI
Tunneling Field Effect Transistors for Low Power ULSI Byung-Gook Park Inter-university Semiconductor Research Center and School of Electrical and Computer Engineering Seoul National University Outline
More informationSustaining the Si Revolution: From 3D Transistors to 3D Integration
Sustaining the Si Revolution: From 3D Transistors to 3D Integration Tsu Jae King Liu Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA USA February 23, 2015
More informationFully Depleted Devices
4 Fully Depleted Devices FDSOI and FinFET Bruce Doris, Ali Khakifirooz, Kangguo Cheng, and Terence Hook CONTENTS 4.1 Overview... 71 4.2 Introduction: Challenges of Conventional CMOS Technology...72 4.3
More informationTopic 3. CMOS Fabrication Process
Topic 3 CMOS Fabrication Process Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Lecture 3-1 Layout of a Inverter
More informationLow-Power and Process Variation Tolerant Memories in sub-90nm Technologies
Low-Power and Process Variation Tolerant Memories in sub-9nm Technologies Saibal Mukhopadhyay, Swaroop Ghosh, Keejong Kim, and Kaushik Roy Dept. of ECE, Purdue University, West Lafayette, IN, @ecn.purdue.edu
More informationFDSOI for Low Power System on Chip. M.HAOND STMicroelectronics, Crolles, France
FDSOI for Low Power System on Chip M.HAOND STMicroelectronics, Crolles, France OUTLINE Introduction : Motivations for FDSOI FDSOI Presentation & Short Channel control MOS VT Construction Performance Analysis
More informationIntroduction to VLSI ASIC Design and Technology
Introduction to VLSI ASIC Design and Technology Paulo Moreira CERN - Geneva, Switzerland Paulo Moreira Introduction 1 Outline Introduction Is there a limit? Transistors CMOS building blocks Parasitics
More informationPower FINFET, a Novel Superjunction Power MOSFET
Power FINFET, a Novel Superjunction Power MOSFET Wai Tung Ng Smart Power Integration & Semiconductor Devices Research Group Department of Electrical and Computer Engineering Toronto, Ontario Canada, M5S
More informationLeakage Current Analysis
Current Analysis Hao Chen, Latriese Jackson, and Benjamin Choo ECE632 Fall 27 University of Virginia , , @virginia.edu Abstract Several common leakage current reduction methods such
More informationComparison of 32nm High-k Metal Gate Predictive Technology Model CMOS and MOSFET-Like CNFET compact Model Based Domino logic Circuits
Comparison of 32nm High-k Metal Gate Predictive Technology Model CMOS and MOSFET-Like CNFET compact Model Based Domino logic Circuits Saravana Maruthamuthu, Wireless Group Infineon Technologies India Private
More informationEE241 - Spring 2013 Advanced Digital Integrated Circuits. Announcements. Sign up for Piazza if you haven t already
EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends and Features of Modern Technologies Announcements Sign up for Piazza if you haven t already 2 1 Assigned Reading R.H.
More information420 Intro to VLSI Design
Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem
More informationSilicon Single-Electron Devices for Logic Applications
ESSDERC 02/9/25 Silicon Single-Electron Devices for Logic Applications NTT Basic Research Laboratories Yasuo Takahashi Collaborators: : Yukinori Ono, Akira Fujiwara, Hiroshi Inokawa, Kenji Shiraishi, Masao
More informationBICMOS Technology and Fabrication
12-1 BICMOS Technology and Fabrication 12-2 Combines Bipolar and CMOS transistors in a single integrated circuit By retaining benefits of bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with
More information