Introduction to VLSI ASIC Design and Technology
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1 Introduction to VLSI ASIC Design and Technology Paulo Moreira CERN - Geneva, Switzerland Paulo Moreira Introduction 1
2 Outline Introduction Is there a limit? Transistors CMOS building blocks Parasitics The [un]desirables The CMOS inverter A masterpiece Gates Just like LEGO Sequential circuits Time also counts! Storage elements A bit in memory Technology scaling, faster Technology Building an inverter Paulo Moreira Introduction 2
3 Introduction Audion (Triode), 1906 Lee De Forest First point contact transistor (germanium), 1947 John Bardeen and Walter Brattain Bell Laboratories Paulo Moreira Introduction 3
4 Introduction First integrated circuit (germanium), 1958 Jack S. Kilby, Texas Instruments Intel Pentium II, 1997 Contained five components, three types: Clock: 233MHz transistors resistors and capacitors Number of transistors: 7.5 M Gate Length: 0.35 Paulo Moreira Introduction 4
5 The world is digital Analogue looses terrain: Computing Instrumentation Control systems Telecommunications Consumer electronics Paulo Moreira Introduction 5
6 analogue, alive and kicking Amplification of very week signals A/D and D/A conversion RF communications Very high frequency amplification and signal processing As digital systems become faster and faster and circuit densities increase: Analogue phenomena are becoming important in digital systems Paulo Moreira Introduction 6
7 Moore s Law The number of transistors that can be integrated on a single IC grows exponentially with time. Integration complexity doubles every three years Gordon Moore Fairchild Corporation Paulo Moreira Introduction 7
8 Trends in transistor count Number of transistors doubles every 2.3 years (acceleration over the last 4 years: 1.5 years) 42 M transistors Increase: ~20K 2.25 K transistors (From: Paulo Moreira Introduction 8
9 Trends in clock frequency 2 GHz Intel Labs Sub-ps switching transistor mp clock > 20 GHz Gate length: 20nm Gate oxide: 3 atomic layers In production: 2007! Paulo Moreira Introduction 9
10 Trends in feature size Intel Labs Sub-ps switching transistor mp clock > 20 GHz Gate length: 20nm Gate oxide: 3 atomic layers In production: 2007! 0.13 mm in production Paulo Moreira Introduction 10
11 Driving force: Economics (1) Traditionally, the cost/function in an IC is reduced by 25% to 30% a year. To achieve this, the number of functions/ic has to be increased. This demands for: Increase of the transistor count Decrease of the feature size (contains the area increase and improves performance) Increase of the clock speed Paulo Moreira Introduction 11
12 Driving force: Economics (2) Increase productivity: Increase equipment throughput Increase manufacturing yields Increase the number of chips on a wafer: reduce the area of the chip: smaller feature size & redesign Use the largest wafer size available Example of a cost effective product (typically DRAM): the initial IC area is reduced to 50% after 3 years and to 35% after 6 years. Paulo Moreira Introduction 12
13 2002 and beyond? Semiconductor Industry Association (SIA) Road Map, 1998 Update Technology (nm) Minimum mask count 22/ /30 Wafer diameter (mm) Memory-samples (bits) 1G 4G 1T Transistors/cm 2 (µp) 6.2M 18M 390M Wiring levels (maximum) Clock, local (MHz) Chip size: DRAM (mm 2 ) Chip size: µp (mm 2 ) Power supply (V) Maximum Power (W) Number of pins (µp) These scaling trends will allow the electronics market to growth at 15% / year IEEE Spectrum, July 1999 Special report: The 100-million transistor IC Paulo Moreira Introduction 13
14 Is there a limit? Silicon lattice constant: 5.42 A Gate oxide: 1.2 nm 3 Si atomic layers! Paulo Moreira Introduction 14
15 Is there a limit? Source: D. Frank et al., Proceedings of the IEEE, 3/2001 Paulo Moreira Introduction 15
16 Is there a limit? High volume factory: Total capacity: 40K Wafer Starts Per Month (WSPM) (180 nm) Total capital cost: $2.7B Production equipment: 80% Facilities: 15% Material handling systems: 3% Factory information & control: 2% Worldwide semiconductor market revenues in 2000: ~$180B Semiconductor market growth rate: ~15% / year Equipment market growth rate: ~19.4% / year By 2010 equipment spending will exceed 30% of the semiconductor market revenues! HEP, where are we: Total LHC production: less than two production days for #10 world wide semiconductor manufacturer in terms of volume. Paulo Moreira Introduction 16
17 How to cope with complexity? By applying: Rigid design methodologies Design automation Rigid Design Methodologies Design Automation (CAE Tools) Successful Design Paulo Moreira Introduction 17
18 Design abstraction levels High System Specification System Level of Abstraction Functional Module Gate + Circuit Device Low S G D Paulo Moreira Introduction 18
19 Outline Introduction Is there a limit? Transistors CMOS building blocks Parasitics The [un]desirables The CMOS inverter A masterpiece Gates Just like LEGO Sequential circuits Time also counts! Storage elements A bit in memory Technology scaling, faster! Technology Building an inverter Paulo Moreira Transistors 19
20 Making Logic CMOS building blocks Silicon switches: The NMOS Its mirror image, the PMOS Electrical behavior: Strong inversion Model How good is the approximation? Weak inversion Gain and inversion Paulo Moreira Transistors 20
21 Making Logic Logic circuit ingredients : Power source Switches Power gain Inversion Power always comes from some form of external EMF generator. NMOS and PMOS transistors: Can perform the last three functions They are the building blocks of CMOS technologies! Paulo Moreira Transistors 21
22 Silicon switches: the NMOS Paulo Moreira Transistors 22
23 Silicon switches: the NMOS Above silicon: Thin oxide (SiO 2 ) under the gate areas; Thick oxide everywhere else; Paulo Moreira Transistors 23
24 Silicon switches: the PMOS Paulo Moreira Transistors 24
25 Cut-off region Linear region Saturation Oxide capacitance MOSFET equations I ds = 0 for V gs V T < 0 2 W V I ds = µ C ox ( V gs V T ) V ds ds ( 1 + λ V ds ) for 0 < V ds < V gs V T L 2 Process transconductance Paulo Moreira Transistors 25 µ C I ox W ds ( ) ( ) L V 2 = gs V T 1 + λ V ds for V ds > V gs V 2 T C ox ox ( ) = ε F / m 2 t ox µ ε ( ) µ C ox = ox A / V 2 t ox 0.24µm process t ox = 5nm (~10 atomic layers) C ox = 5.6fF/µm 2
26 MOS output characteristics Linear region: V ds <V gs -V T Voltage controlled resistor Saturation region: V ds >V gs -V T Voltage controlled current source Curves deviate from the ideal current source behavior due to: Channel modulation effects Paulo Moreira Transistors 26
27 MOS output characteristics 250 L = 240nm, W = 480nm 200 Vgs = 0.7V (< Vt) Vgs = 1.3V Vgs = 1.9V Vgs = 2.5V Ids [ua] Vds [V] Paulo Moreira Transistors 27
28 MOS output characteristics 400 L = 24um, W = 48um Vgs = 0.7V (<Vt) Vgs = 1.3V Vgs = 1.9V Vgs = 2.5V Ids [ua] Vds [V] Paulo Moreira Transistors 28
29 Bulk effect The threshold depends on: Gate oxide thickness Doping levels Source-to-bulk voltage When the semiconductor surface inverts to n-type the channel is in strong inversion V sb = 0 strong inversion for: surface potential > -2φ F V sb > 0 strong inversion for: surface potential > -2φ F + V sb p+ p+ V=0 V=V T0 n+ n+ V>0 V>V T0 n+ n+ Paulo Moreira Transistors 29
30 Bulk effect W = 24µm L = 48µm L = 24um, W = 48um, Vbs = 1 L = 24um, W = 48um, Vbs = -1V V sb = 0V V sb = 1 V Ids [ua] Vgs [V] Paulo Moreira Transistors 30
31 Mobility µ C ox = ( ) µ εox A / V 2 t ox The current driving capability can be improved by using materials with higher electron mobility Paulo Moreira Transistors 31
32 Is the quadratic law valid? 600 Ids - Vgs (Vds = 2.5V, Vbs = 0V) L = 24um, W = 48um L = 2.4um, W = 4.8um L = 240nm, W = 480nm Quadratic law valid for long channel devices only! Ids [ua] Vgs [V] Paulo Moreira Transistors 32
33 Is I d =0 when V gs <V T? For V gs <V T the drain current depends exponentially on V gs In weak inversion and saturation (V ds > ~150mV): W Id L I do e where I do = e q VT n k T qv gs n k T Used in very low power designs Slow operation Weak inversion Paulo Moreira Transistors 33
34 Gain: Signal regeneration at every logic operation Static flip-flops Static RW memory cells Inversion: Intrinsic to the commonsource configuration The gain cell load can be: Resistor Current source Another gain device (PMOS) Gain & Inversion Paulo Moreira Transistors 34
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