The 3 D Tri Gate transistor is a variant of the FinFET developed at UC Berkeley, and is being used in Intel s 22nmgeneration. microprocessors.

Transcription

1 On May 4, 2011, Intel Corporation announced what it called the most radical shift in semiconductor technology in 50 years. A new 3 dimensional transistor design will enable the production of integrated circuit chips that operate faster with less power The 3 D Tri Gate transistor is a variant of the FinFET developed at UC Berkeley, and is being used in Intel s 22nmgeneration microprocessors.

2 Lecture 28 OUTLINE CMOS Technology Advancement The CMOS power crisis Advanced MOSFET structures Thin body MOSFET structures History and future of multi gate MOSFETs Reading: Hu 7.8

3 Historical Voltage Scaling Since V T cannot be scaled down aggressively, the supply voltage (V DD ) has not been scaled down in proportion to the MOSFET gate length: V DD V DD V T Source: P. Packan (Intel), 2007 IEDM Short Course 3

4 Power Density Scaling NOT! Power Density (W/cm 2 ) 1E+03 1E+02 1E+01 1E+00 1E 01 1E 02 1E 03 1E 04 1E 05 Power Density Trend Passive Power Density Active Power Density Gate Length (μm) Source: B. Meyerson (IBM) Semico Conf., January 2004 Power Density (W/cm 2 ) Power Density Prediction circa Sun s Surface Rocket Nozzle Nuclear Reactor 8086 Hot Plate P6 Pentium proc Year Source: S. Borkar (Intel ) 4

5 Parallelism Power Density (W/cm2) Sun s Surface Rocket Nozzle Nuclear Reactor 8086 Core 2 Hot Plate P Pentium proc Year Source: S. Borkar (Intel ) /throughput (ps/op) Computing performance is now limited by power dissipation. This has forced the move to parallelism as the principal means of increasing system performance. Normalized Energy/op Energy vs. Delay per operation dual core single core Run in parallel to recoup performance Operate at a lower energy point (lower V DD ) 5

6 Intel Ivy Bridge Processor 6

7 CMOS Technology Scaling XTEM images with the same scale courtesy V. Moroz (Synopsys, Inc.) 90 nm node 65 nm node 45 nm node 32 nm node T. Ghani et al., IEDM 2003 (after S. Tyagi et al., IEDM 2005) K. Mistry et al., IEDM 2007 P. Packan et al., IEDM 2009 Gate length has not scaled proportionately with device pitch (0.7x per generation) in recent generations. Transistor performance has been boosted by other means. 7

8 MOSFET Performance Boosters Strained channel regions eff High k gate dielectric and metal gate electrodes C ox Cross-sectional TEM views of Intel s 32nm CMOS devices P. Packan et al., IEDM Technical Digest, pp ,

9 Key to V DD Reduction: Gate Control Gate log I D I ON C ox C dep S C C total ox Source Body Drain V DD V GS The greater the capacitive coupling between Gate and channel, the better control the Gate has over the channel potential. lower V DD to achieve target I ON /I OFF reduced short channel effect (SCE) and drain induced barrier lowering (DIBL) 9

10 Why New Transistor Structures? Off state leakage (I OFF ) must be suppressed as L g is scaled down allows for reductions in V T and hence V DD Leakage occurs in the region away from the channel surface Let s get rid of it! L g Thin Body MOSFET: Gate Source Drain Buried Oxide Substrate Silicon on Insulator (SOI) Wafer 10

11 Thin Body MOSFETs I OFF is suppressed by using an adequately thin body region. Body doping can be eliminated higher drive current due to higher carrier mobility Ultra Thin Body (UTB) Double Gate (DG) L g Gate Source Drain Buried Oxide Substrate T Si Source Gate Gate Drain T Si T Si < (1/4) L g T Si < (2/3) L g 11

12 Effect of T Si on OFF state Leakage L g = 25 nm; t ox,eq = 12Å T Si = 10 nm T Si = 20 nm 10 6 G Si Thickness [nm] G 0.0 3x10 2 S G D S D 10 1 Leakage Current Density [A/cm 2 V DS = 0.7 V 20.0 I OFF = 2.1 na/ m I OFF = 19 A/ m G 12

13 Double Gate MOSFET Structures PLANAR: VERTICAL FINFET: L. Geppert, IEEE Spectrum, October

14 DELTA MOSFET D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda (Hitachi Central Research Laboratory), A fully depleted lean channel transistor (DELTA) a novel vertical ultrathin SOI MOSFET, IEEE Electron Device Letters Vol. 11, pp , 1990 Improved gate control observed for W g < 0.3 m L EFF = 0.57 m W l = 0.4 m 14

15 Double Gate FinFET Self aligned gates straddle narrow silicon fin Current flows parallel to wafer surface Gate Length = L g Source Gate 2 G S D G Current Flow Gate 1 Drain Fin Height H fin = W Fin Width W fin = T Si 15

16 1998: First n channel FinFETs D. Hisamoto, W. C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T. J. King, J. Bokor, and C. Hu, A folded channel MOSFET for deep sub tenth micron era, IEEE International Electron Devices Meeting Technical Digest, pp , 1998 Plan View L g = 30 nm W fin = 20 nm H fin = 50 nm L g = 30 nm W fin = 20 nm H fin = 50 nm Devices with L g down to 17 nm were successfully fabricated 16

17 1999: First p channel FinFETs X. Huang, W. C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y. K. Choi, K. Asano, V. Subramanian, T. J. King, J. Bokor, and C. Hu, Sub 50 nm FinFET: PMOS, IEEE International Electron Devices Meeting Technical Digest, pp , 1999 L g = 18 nm W fin = 15 nm H fin = 50 nm Transmission Electron Micrograph 17

18 Recognition DARPA Significant Technical Achievement Award presented at DARPATECH 2000 Symposium 18

19 UC Berkeley FinFET Patent + 27 additional claims 19

20 2001: 15 nm FinFETs Y. K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T. J. King, J. Bokor, C. Hu, "Sub 20nm CMOS FinFET technologies, IEEE International Electron Devices Meeting Technical Digest, pp , 2001 Drain Current, I d [A/um] Transfer Characteristics V d =-1.0 V V d =-0.05 V N-body= 2x10 18 cm -3 PMOS P+Si 0.4 Ge 0.6 Gate V d =1.0 V V d =0.05 V NMOS Gate Voltage, V g [V] Drain Current, I d [ua/um] W fin = 10 nm; T ox = 2.1 nm Output Characteristics PMOS V g -V t =1.2V NMOS Voltage step : 0.2V Drain Voltage, V d [V]

21 2002: 10 nm FinFETs SEM image: B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Y. Yang, C. Tabery, C. Hu, T. J. King, J. Bokor, M. R. Lin, and D. Kyser, "FinFET scaling to 10nm gate length," International Electron Devices Meeting Technical Digest, pp , 2002 TEM images These devices were fabricated at AMD, using optical lithography. 21

22 Tri Gate FET (Intel Corp.) L g = 60 nm W fin = 55 nm H fin = 36 nm B. Doyle et al., IEEE Electron Device Letters, Vol. 24, pp ,

23 Bulk FinFET (Samsung Electronics) FinFETs can be made on bulk Si wafers lower cost improved thermal conduction 90 nm L g FinFETs demonstrated W fin = 80 nm H fin = 100 nm DIBL = 25 mv C. H. Lee et al., Symposium on VLSI Technology Digest, pp ,

24 2004: High k/metal Gate FinFET D. Ha, H. Takeuchi, Y. K. Choi, T. J. King, W. Bai, D. L. Kwong, A. Agarwal, and M. Ameen, Molybdenum gate HfO 2 CMOS FinFET technology, IEEE International Electron Devices Meeting Technical Digest, pp ,

25 Impact of Fin Layout Orientation L. Chang et al. (IBM), SISPAD 2004 (Series resistance is more significant at shorter L g.) If the fin is oriented or to the wafer flat, the channel surfaces lie along (110) planes. Lower electron mobility Higher hole mobility If the fin is oriented 45 to the wafer flat, the channel surfaces lie along (100) planes. 25

26 May 4, 2011: Intel Announcement Ivy Bridge based Intel Core family processors will be the first high volume chips to use 3 D Tri Gate transistors. This silicon technology breakthrough will also aid in the delivery of more highly integrated Intel Atom processor based products reinvents transistors using new 3 d structure 26

27 22 nm node Tri Gate FETs L g = nm; W fin = 8 nm; H fin = 34 nm High k/metal gate stack, EOT = 0.9 nm Channel strain techniques Transfer Characteristics I OFF vs. I EFF I OFF vs. I EFF PMOS NMOS C. Auth et al., Symp. VLSI Technology

28 MOSFET Evolution 32 nm planar 22 nm thin-body beyond 10 nm nanowires? J. Kavalieros et al. (Intel) Symp. VLSI Technology 2006 C. Dupré et al. (CEA LETI) IEDM 2008 P. Packan et al. (Intel), IEDM 2009 K. Cheng et al. (IBM) Symp. VLSI Technology 2009 UC Berkeley DARPA AME proposal: (Feb. 1997) 28

29 Channel Length Scaling Limit Quantum mechanical tunneling sets a fundamental scaling limit for the channel length. If electrons can easily tunnel through the source potential barrier, the gate cannot shut off the transistor. nmosfet Energy Band Diagram (OFF state) SOURCE DRAIN E C J. Wang et al., IEDM Technical Digest, pp , 2002 E C 29

30 Ultimately Scaled MOSFETs M. Luisier et al., IEDM 2011 L g = 5 nm 30

31 National Science Foundation (NSF) Science and Technology Center (STC) for Energy Efficient Electronics Science Goal: Develop a new switch that can operate with V DD = 1 mv PI: Eli Yablonovitch (UC Berkeley) 10 yr project, started 15 Sep 2010 Theme I: Nanoelectronics (Prof. Eli Yablonovitch) Theme II: Nanomechanics (Prof. Tsu Jae King Liu) Theme III: Nanomagnetics (Prof. Jeffrey Bokor) Theme IV: Nanophotonics (Prof. Ming Wu) Contra Costa UC Berkeley MIT LATTC Stanford Tuskegee 31

32 A Vision of the Future The Cloud Diversification of Devices & Materials Heterogeneous Integration Better Energy Efficiency Investment & Functionality, Lower Cost J. Rabaey ASPDAC 08 Mobile Devices The Swarm Sensatex Information technology will be pervasive embedded human centered solving societal scale problems Market Growth Energy Health care Environment Disaster response Philips Transportation 32