Transistor Scaling in the Innovation Era. Mark Bohr Intel Senior Fellow Logic Technology Development August 15, 2011

Transcription

1 Transistor Scaling in the Innovation Era Mark Bohr Intel Senior Fellow Logic Technology Development August 15, 2011

2 MOSFET Scaling Device or Circuit Parameter Scaling Factor Device dimension tox, L, W 1/κ Doping concentration Na κ Voltage V 1/κ Current I 1/κ Capacitance εa/t 1/κ Delay time/circuit VC/I 1/κ Power dissipation/circuit VI 1/κ 2 Power density VI/A 1 R. Dennard, IEEE JSSC, 1974 Classical MOSFET scaling was first described in

3 Scaling Trends Transistor dimensions scale to improve performance, reduce power and reduce cost per transistor 3

4 Transistor Scaling Trends Transistor dimensions scale to improve performance, reduce power and reduce cost per transistor 4

5 30 Years of MOSFET Scaling Dennard JSSC Paper (1974) Intel 65 nm Generation (2005) 1 um 35 nm Physical Gate Length: >1.0 um 35 nm Electrical Channel Length: 1.0 um <20 nm Gate Oxide Thickness: 35 nm 1.2 nm Channel Doping: 4x10 16 cm -3 ~10 18 cm -3 Operating Voltage: 4.0 V 1.2 V 5

6 Gate Oxide Scaling Trends Scaling SiO 2 gate oxide thickness ultimately ran into leakage current limitations 6

7 Voltage Scaling and Leakage Trends V CC -V T overdrive needed for good performance V T scaling and resultant leakage increase no longer tolerable due to power constraint 7

8 MOSFET Scaling Traditional MOSFET scaling ran out of steam in the early 2000s 8

9 If old techniques are no longer effective, Then innovate! 9

10 Lithography Trends If old techniques are no longer effective, then innovate and find new techniques 10

11 Lithography Trends OPC Phase shift Immersion Double pattern Gridded layout If old techniques are no longer effective, then innovate and find new techniques 11

12 Lithography Trends OPC Phase shift Immersion Double pattern Gridded layout If old techniques are no longer effective, then innovate and find new techniques 12

13 Layout Restrictions 65 nm Layout Style 32 nm Layout Style Bi-directional features Varied gate dimensions Varied pitches Uni-directional features Uniform gate dimension Gridded layout 13

14 SRAM Cell Size Scaling 14

15 SRAM Cell Size Scaling 65 nm, um 2 45 nm, um 2 32 nm, um 2 22 nm, um 2 15

16 90 nm Strained Silicon Transistors High Stress Film NMOS PMOS SiGe SiGe SiN cap layer Tensile channel strain SiGe source-drain Compressive channel strain Strained silicon provided increased drive currents, making up for lack of gate oxide scaling 16

17 45 nm High-k Metal Gate Transistors 65 nm Transistor 45 nm HK+MG SiO 2 dielectric Polysilicon gate electrode Hafnium-based dielectric Metal gate electrode High-k + Metal Gate transistors break through gate oxide scaling barrier 17

18 Transistor Scaling and Performance HK + MG Faster Strained Silicon Smaller Transistors continue to get smaller and faster through material and structure innovations 18

19 32 nm System-on-Chip Transistors Lower Leakage 32 nm SoC transistors range from high performance to low power 19

20 Performance vs. Power Landscape 65 nm 45 nm 32 nm +22% HP Leakage Power 10x SP 10x LP Frequency 32 nm transistors offer a broad range of performance/power capabilities 20

21 Performance vs. Power Landscape 65 nm 45 nm +22% HP 32 nm Server Desktop Leakage Power 10x SP Laptop Nettop/Netbook 10x LP Tablet Set Top Box Embedded Pocket Device Frequency 32 nm transistors offer a broad range of performance/power capabilities 21

22 22 nm Tri-Gate Transistors Planar Transistor Tri-Gate Transistor Transistors continue to get smaller and faster through material and structure innovations 22

23 22 nm Tri-Gate Transistors Steeper sub-threshold slope can provide lower leakage, higher performance, and lower active power 23

24 22 nm Tri-Gate Transistors Steeper sub-threshold slope can provide lower leakage, higher performance, and lower active power 24

25 22 nm Tri-Gate Transistors Unprecedented performance gain at low voltage, ~50% active power reduction at constant performance 25

26 32 nm Planar Transistors 22 nm Tri-Gate Transistors 26

27 Transistor Evolution 90 nm 65 nm 45 nm 32 nm 22 nm Invented SiGe Strained Silicon 2 nd Generation SiGe Strained Silicon Invented Gate-Last High-k Metal Gate 2 nd Generation Gate-Last High-k Metal Gate First to Implement Tri-Gate Strained Silicon High-k Metal Gate Continued innovations in transistor materials and structure are needed to continue scaling Tri-Gate 27

28 Future III-V Transistor Options R. Pillarisetty, Intel, IEDM 2010 Goal of III-V FETs is to provide good performance at low voltage 28

29 Future III-V Transistor Options M. Radosavljevic, Intel, IEDM 2010 Goal of III-V FETs is to provide good performance at low voltage 29

30 Future Devices and Materials 5nm Needed Focus: New materials with bottoms-up fill to improve R & C Higher mobility materials to allow voltage scaling New device types, go vertical Exotic: graphene, CNT QW III-V Device 5 nm Nanowires Graphene CNT 30

31 Research-Development-Manufacturing Research Development Manufacturing Highly coordinated R-D-M pipeline is required to bring innovative technologies to high volume manufacturing 31

32 Research-Development-Manufacturing Research Development Components Research Manufacturing Logic Technology Development Manufacturing Fabs Highly coordinated R-D-M pipeline is required to bring innovative technologies to high volume manufacturing 32

33 Research-Development-Manufacturing Research Universities Consortia Components Research Development Manufacturing Suppliers/Vendors Government Labs Logic Technology Development Manufacturing Fabs Highly coordinated R-D-M pipeline is required to bring innovative technologies to high volume manufacturing 33

34 Research-Development-Manufacturing Research Universities Consortia Components Research Development Manufacturing Suppliers/Vendors Government Labs Logic Technology Development Manufacturing Fabs 10 nm 14 nm 22 nm 32 nm Highly coordinated R-D-M pipeline is required to bring innovative technologies to high volume manufacturing 34

35 Research Collaboration Global research collaboration needed to identify breakthrough innovations 35

36 Conclusion Moore s Law continues, but the formula for success is changing Innovations in transistor materials and structures are now essential to continue scaling A highly coordinated R-D-M pipeline is required to bring innovative technologies from research to manufacturing 36