3. COMPARING STRUCTURE OF SINGLE GATE AND DOUBLE GATE MOSFET WITH DESIGN AND CURVE

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1 P a g e 80 Available online at APPLIED RESEARCH JOURNAL RESEARCH ARTICLE ISSN: Applied Research Journal Vol. 3, Issue, 2, pp.80-86, February, 2017 COMPARATIVE STUDY ON SINGLE GATE MOSFET AND DOUBLE GATE MOSFET * Faysal Al Mahmud, Md. Mydul Islam and Md. Hasan Maruf Department of Electrical and Electronics Engineering, Green University of Bangladesh. ARTICLE INFO Article History: Received: 16, January, 2017 Final Accepted: 29, February, 2017 Published Online: 10, March, 2017 Key words: MOSFET; SG-MOSFET; DG-MOSFET; XOR; XNOR; MICROWIND; LTSpice. ABSTRACT This study explored with the comparison between Single gate MOSFET (SG-MOSFET) and Double Gate MOSFET (DG-MOSFET) using Exclusive-OR (XOR) and Exclusive-NOR (XNOR) gate. The structures of XOR and XNOR are simulated for single gate as well as double gate MOSFET in 90nm CMOS process in MICROWIND. Comparative results are given on the basis of the simulated results of SG and DG. Power consumption as well as Noise Margin gives enhanced result in DG-MOSFET. LTSpice and PSpice are also used as a tool for designing and simulation. Furthermore, in this work, study on different curves such as voltage vs time, voltage vs current, frequency vs time and voltage vs voltage for both SG and DG MOSFET. Copy Right, ARJ, All rights reserved 1. INTRODUCTION Semiconductor is a crystalline element or compound where electrons placed in district condition. This material has two types of bands, conduction band, and valance band, a gap remains between two bands. For this reason, when voltage is applied the component neither works as a conductor nor an insulator. MOSFET is an example of an enhancement semiconductor. SG-MOSFET is a transistor consisting of four terminals, Source(S), Drain (D), Gate (G) and Body (B)/Base/Substrate [1]. Source and body terminal usually short circuited internally to make it field effective transistor. SG-MOSFET has two operating modes, Enhancement mode and Depletion mode [2, 3]. In enhancement mode when there is a voltage drop across the oxide a conducting channel is produced between source and drain [3]. Besides, in the depletion mode the carriers of channel deplete the surface layer, so conductivity is going to be decreased. Double gate MOSFET has a four terminal configuration, when back gate bias is fixed and front gate acts as a control electrode, if both terminals are shorted, it gets three terminal configurations [4]. In three terminal configurations, same voltage is applied to both terminal and different voltage is applied at four terminal configurations. By applying different voltages and changing the thickness of oxide asymmetry condition can be brought in Double Gate MOSFET. 2. ADVANTAGES DG-MOSFET has these advantages comparing with SG-MOSFET Formation and Access becomes easier of both gates. Thickness of silicon channel gets better uniformity. Double gate shield the channel electrically. Junction capacitance becomes smaller. Sub-threshold slope comes to nearly ideal condition. Random dopant fluctuation and carrier mobility degradation is reduced. The ration of current on/off ratio becomes higher. For being different terminal configuration design of circuit becomes flexible. 3. COMPARING STRUCTURE OF SINGLE GATE AND DOUBLE GATE MOSFET WITH DESIGN AND CURVE *Corresponding author: Faysal Al Mahmud, fmahmud877@gmail.com Department of Electrical and Electronics Engineering, Green University of Bangladesh.

2 P a g e 81 Faysal Al Mahmud et. al Single Gate XOR and XNOR XOR and XNOR are implemented together using single gate MOSFET in Fig. 1. The gate width and length of PMOS (M1, M4) and NMOS (M2, M3, M5) are fixed w= 0.35µm for all and L= 2µm and 5ɥm respectively. The 60nm technology is used for both implementations. When A=B=0 is applied as an input only PMOS (M1) is on and contact with high voltage. If A=0, B=1 is applied M1 and M2 is off and M3 becomes active but it starts discharging according to its characteristics [4-7]. At A=1, B=0 it shows the same discharging condition but A=B=1 condition M2 is conduct and the output voltage becomes high. Figure 1 Schematic diagram of SG-XOR and XNOR This change able condition neither represents the chrematistics of exclusive NOR gate. M4 and M5 used to invert the characteristics and provide the output of XOR gate. Table 1 Input to output conversion process of SG-XNOR gate A B M1 (PMOS) M2 (NMOS) M3 (NMOS) Output 0 0 ON OFF OFF High 0 1 OFF OFF ON (Discharging condition) Low 1 0 ON ON ON (Discharging condition) (Discharging condition) Low 1 1 OFF ON OFF High Figure 2 Output Curve of SG-XOR and XNOR gate The output curved of single gate XOR and XNOR gate are shown in Fig. 2. Here the input pulse is A= PULSE ( n.5n 500m 2) and B= PULSE ( n 1n 500m 1) Double Gate XOR and XNOR

3 P a g e 82 Applied Research Journal Vol. 3, Issue, 2, pp.80-86, February, 2017 Figure 3 Schematic diagram of DG-XOR and XNOR. Fig. 3 shows the combine schematic diagram of double gate XOR and XNOR. PMOS length, L= 0.25µm and width, w=2µm. NMOS length and width are 0.25µm and 1µ, the working procedure of this implementation also follows the similar way as single gate. The inputted pulses are also same here but it gives the noise free and better output than single gate Layout of Single Gate XOR and XNOR Figure 4 Output of curve of DG-XOR and XNOR MICROWIND EDA software is used for compressing the circuit of single gate XOR XNOR. This layout is done by combining both gates. The layout introduced with 60nm technology using the tool. Figure 5 Layout of SG-XOR and XNOR [8]

4 P a g e 83 Faysal Al Mahmud et. al. P+ diffusion, N+ diffusion, metal1, meta3 and polysilicon are used here. PMOS and NMOS gate length is used 250 lambda.the red and green colour indicates the XOR and XNOR respectively and voltage, VDD=1.20v, maximum current, IDDmax= 0.218mA and average current, iavg= 0.026mA Figure 6 Output curve of SG-XOR and XNOR 3.4. Layout of Double Gate XOR and XNOR Figure 7 Eye Diagram SG-XOR and XNOR. Figure 8 Layout of DG-XOR and XNOR.

5 P a g e 84 Applied Research Journal Vol. 3, Issue, 2, pp.80-86, February, 2017 Figure 9 Output curve of DG-XOR and XNOR 3.5. Propagation Delay Figure 10 Eye Diagram of DG-XOR and XNOR. Propagation depends on the difference between transition of input and out logic level and 50% of their values. The average combination of XOR and XNOR gate is 00,01,10,11. For all of the combination the propagation delay for single gate XOR and XNOR are 9.75ps and 5.125ps respectively. Further for double gate XOR and XNOR are 55.12ps and 49.25ps Noise Margin Noise margin are comparable for SG-XOR and XNOR gate and DG-XOR and XNOR gate. High noise margin and low noise margin are studied by performing DC analysis and eye diagram. Here GND= logical 0 and Vdd= 1. Table 2 Noise margin VOH VIH VIL VOL NMH NML Single gate Double gate Power Consumption The input voltage range is fixed from 0.5v to 1.0v. The power consumption of Single and Double gate MOSFET are varying with the change of voltage. When the voltage increased the power consumption of single gate is increased more than the double gate.

6 P a g e 85 Faysal Al Mahmud et. al Voltage and Current Figure 11 Power consumption The curve represents the comparison of voltage and current between SG and DG XOR and XNOR. Maximum and average drain to drain voltage is different from SG and DG. Iddmax=0.220mA, 0.121mA and Iddavr=.030mA,.016mA. Figure 12 Voltage and current of SG-XOR and XNOR Figure 13 Voltage and current of DG-XOR and XNOR

7 P a g e 86 Applied Research Journal Vol. 3, Issue, 2, pp.80-86, February, RESULT ANALYSIS The outcome of the study is double gate MOSFET is comparatively better than the single gate MOSFET. Double gate reduced the short channel effects, better control of the channel, better I on and I off. Double gate shield the channel so lower gate leakage is occurred. Table 3 Comparison of SG and DG Parameter Single Gate Double gate Gate/control voltage 1.2v 1.2v Output voltage 700mv 830mv Drain to source current 190µA 150µA Propagation delay (XOR,XNOR) (9.75, 5.25)ps (55.12, 49.25)ps Noise margin ( )v ( )v (NMH-NML) Power consumption 21.5µw 7.2µw Output power µw µw Additive noise in the signal HIGH LOW 5. CONCLUSION The paper represents the simulation, layout and performance analysis of Single Gate MOSFET and Double Gate MOSFET using 90nm technology. XOR and XNOR gate layout are designed by 90nm technology, 6 metal copper-strained SiGe where input voltage was 1.2v to 2.5v. The layout design has been simulated in MICROWIND EDA simulator. The propagating delay, power consumption and noise margin give an progress result in DG MOSFET. It is also true to add external noise in DG MOSFET compare to SG MOSFET show better performance. The DG MOSFET can be a replacement of a SG MOSFET in future to develop the technology design 6. REFERENCES [1] Chau, R Challenges and opportunities of emerging nanotechnology for VLSI nanoelectronics. In Semiconductor Device Research Symposium. International Semiconductor Device Research Symposium. [2] Uchino, T., Ashburn, P., Kiyota, Y., & Shiba, T A CMOS-compatible rapid vapor-phase doping process for CMOS scaling. IEEE Transactions on Electron Devices. 51(1): [3] Bui, H. T., Wang, Y., & Jiang, Y Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 49(1): [4] Yuan, S., Li, Y., Yuan, Y., & Liu, Y Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current. Microelectronics Journal. 44(12): [5] Sharma, T., Sharma, K. G., Singh, B. P., & Arora, N High speed, low power 8t full adder cell with 45% improvement in threshold loss problem. Recent Advances in Networking, VLSI and Signal Processing. [6] Wang, J. M., Fang, S. C., & Feng, W. S New efficient designs for XOR and XNOR functions on the transistor level. IEEE Journal of solid-state Circuits. 29(7): [7] Chowdhury, S. R., Banerjee, A., Roy, A., & Saha, H A high speed 8 transistor full adder design using novel 3 transistor XOR gates. International Journal of Electronics, Circuits and Systems. 2(4): [8] Kumar, N., Bansal, M., & Kumar, N VLSI Architecture of Pipelined Booth Wallace MAC Unit. International Journal of Computer Applications. 57(11).