Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI

Transcription

1 Lecture: Integration of silicon photonics with electronics Prepared by Jean-Marc FEDELI CEA-LETI

2 Context The goal is to give optical functionalities to electronics integrated circuit (EIC) The objectives are either: Increase the performance of photonics with embedded electronic Increase the data transmission speed between cores with photonics 2

3 Some goals Minimum impact on EIC designer librairies Development of a specific designer CMOS libraries require a huge effort ( ). So integration of optical components requires minimum change of a design library Wafer testability with high throughput Optical devices on a EIC chip have to be tested with the same procedures as electronic devices. So full wafer testability without any dicing, polishing, assembly Lowest added process complexity This is an issue related to yield, so cost ( ) 3

4 Integration of Si Photonics on EIC?? Pads Mn BE: Back end FE:Front end Transistors M1 Si substrate 4

5 Die flip-chip solution Source PD e=3µm SiO2 BOX Silicon substrate SiO2 BOX Silicon substrate Photonic wafer fabrication Die substrate Not a wafer level fabrication Uncompatibility with microelectronics packaging Could be a good solution for low volume Flip chip bonding on CMOS dies or wafer 5

6 KOTURA example 6

7 Integration of photonics on CMOS Option 2 Combined front-end fabrication 7

8 Combined fabrication Micro-electronics Bulk Technologies (CMOS, BiCMOS, SiGe, etc ) SOI Technology evolution: thin Si upper layer 55nm on BOX 145nm Photonics SOI wafers with Si 200 to 400nm on BOX> 1µm 8

9 Which substrate for combined fabrication? Si upper layer photonics BOX SOI photonics Adapt electronics library to thicker box Si Substrate photonics area photonics BOX SOI electronics area electronics BOX Dedicated area for photonics and electronics Cost? Bulk electronics area photonics area photonics BOX Buried thick BOX on a bulk substrate Cost and quality? 9

10 Option 2: Luxtera approach Proprietary SOI CMOS 130nm technology Proprietary library for IC design Flip chip bonded lasers or external WDM lasers Surface gratings fiber couplers MUX and DEMUX with controlled MMI 10Gb/s modulator based on lateral Si depletion 20GHz Ge photodetectors Electronic control of optical devices 10

11 Option 2: Combined fabrication( Luxtera) SOI? WG width and thickness? Pitch of the grating? Partial etching for the grating? 11

12 Option 2: Combined fabrication( Luxtera) MODULATOR The gray-scale gradient in the figure indicates that the doping density varies laterally from low doping at the junction to high doping at the contact region. This design is the result of a tradeoff between minimizing optical insertion loss due to the presence of free carriers overlapping the optical mode (desire for low doping density) and minimizing the series resistance of the diode (desire for high-doping density). LUXTERA 12

13 Option 2: Combined fabrication( Luxtera) Ge epitaxy in a CVD environment is, usually, naturally selective to oxide When it comes to choose the insertion point of the Ge epitaxy step within a CMOS process, several factors must be considered: the temperature profile of the process, the possibility to contact the Ge device using the standard Si contact module, the salicide sensitivity to thermal treatments, the availability of a clean Si surface, the presence of dielectric films and their interaction on the selective growth of Ge. All these requirements may differ among different technology nodes (Luxtera) 13

14 Lightwire Integration of on optical modulator 14

15 15

16 16

17 MIT Eos1 65 nm test chip Texas Instruments standard 65 nm bulk CMOS process First ever photonic chip in sub-100nm CMOS Automated photonic device layout Monolithic integration with electrical modulator drivers 17

18 MIT Eos1 65 nm test chip Ring modulator Digital driver Two-ring filter Vertical coupler grating One-ring filter Paperclips Photo detector Waveguide crossings M-Z test structures 4 ring filter banks 18

19 MIT Eos1 65 nm test chip Cross-sectional view of a photonic chip SEM image of a poly silicon waveguide Waveguide made of polysilicon Silicon substrate under waveguide etched away to provide optical cladding 64 wavelengths per waveguide in opposite directions 19

20 Option 1: Integration above metallization Photonic layer at the last levels of metallizations with back-end fabrication 1A: Wafer bonding of PIC processed at high temperature on SOI 1B: Back-end fabrication of PIC at low temperature 20

21 Option 2B with low T c technology Source PD SiN or a:si Waveguide formation with SiO2 cladding Bonding InP dies Source PD Connection with EIC through passivation layers Fabrication of source and PD 21

22 SiNx waveguides at low temperature Fabrication at 350 C, Cladding with SiO2 Si 3 N 4 Losses Waveguide (0.4µm x 0.8µm) 2 db/cm Bend (R 25µm) 0.02 db/90 µbend Y junction 1.1 db 1 => 2 MMI 0.5 db ( E<0.2dB) 1 => 4 MMI 1.4dB ( E<0.45dB) 1 to 16 distribution network E<0.5dB 22

23 Option 1: Integration above metallization Photonic layer at the last levels of metallizations with back-end fabrication 1A: Wafer bonding of PIC processed at high temperature on SOI 1B: Back-end fabrication of PIC at low temperature 23

24 Electronic-Photonic Integration CMOS wafer planarized Deposition of SiO2 layer for bonding CMOS wafer transistors metal interconnects 24

25 Rib Silicon Photonic layer SOI 400nm / 2000 nm Litho FC + transition Rib strip : Rib Waveguide definition Si etching 180nm FC 25

26 Stripe Silicon Photonic layer Litho Passive 220nm: AWG, RR, etc.: Stripe Waveguide definition Si etching 220nm FC AWG 26

27 Modulator Processing Lithos for implantation Different implantations FC Modulator AWG 27

28 Ge photodetector Processing Cavity formation Ge epitaxy in cavity P & N Implant FC Modulator AWG Ge PD 28

29 Planarization SiO2 deposition 1µm Planarization FC Modulator AWG Ge PD 29

30 Molecular wafer bonding Alignement of the two wafers (+-2µm) Molecular bonding of photonic wafer on CMOS wafer CMOS wafer transistors metal interconnects 30

31 31

32 Substrate removal Mechanical grinding Si chemical etching FC Modulator AWG Ge PD CMOS wafer transistors metal interconnects 32

33 InP heterostructure bonding bond small InP dice with herostructure on wafer InP substrate removal of dice FC Modulator AWG Ge PD CMOS wafer transistors metal interconnects 33

34 InP heterostructure process Process InP source (InP etching) Planarized with SiO2 FC InP source Modulator AWG Ge PD CMOS wafer transistors metal interconnects 34

35 Vias formation Lithos for different depths Etching SiO2 FC InP source Modulator AWG Ge PD CMOS wafer transistors metal interconnects 35

36 Metal formation Metal deposition Metal etching PAD FC InP source Modulator AWG Ge PD CMOS wafer transistors metal interconnects 36

37 SOI wafer bonded on a CMOS wafer Silicon rib waveguide Germanium 37

38 Monocristalline rib waveguide with Ge in cavity Silicon Ge cavity SiO 2 Metallisations Silicon rib waveguide 38

39 Photonic wafer metallic bonded on EIC wafer Source PD SiO2 BOX Silicon substrate SiO2 BOX Silicon substrate Photonic wafer Photonic functions with high temp technology Die to wafer source bonding Substrate removal Metallic bonding Planarized electrodes formation 39

40 Wafer bonding Cu/Cu of CMOS with SOI photonics Process independantly SOI photonics wafer and CMOS wafer Finish with Cu pad interface Cu-Cu bond at low temperature the two wafers Remove the SOI photonics substrate Contact on the electronics pad by the top surface is not easy 0,08 0,07 0,06 0,05 V(Volt) 0,04 0,03 0,02 0,01 0,00-0,01-0,1 0,0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1,0 1,1 I(Ampere) 40

41 Photonic wafer thinned bonded on EIC wafer with TSV Source PD Photonic wafer Die to wafer source bonding Active device fabrication Bonding a handle wafer and thinning the PIC substrate Through Silicon Vias formation Removal of the handle wafer Bonding EIC with PIC 41

42 42

43 Option 1A approachs MIT technology Concept of BE technology with SiGe 43

44 Integration of a photonic layer by IBM 44

45 IBM 2 45

46 IBM 3 46

47 Integration HP Labs 47

48 Integration of photonics on CMOS Option 1 Photonic layer at the last levels of metallizations with back-end fabrication Option 2 Combined front-end fabrication Option 3 Backside fabrication BE: Back end FE:Front end 48

49 Option 3: Low T C fabrication on the back side Si Substrate Si Substrate Si Substrate a:si Waveguide on backside of CMOS wafer InGaAsPD Fab of InP components Connection with CMOS through the substrate Fabrication of the EIC Protection of the Front side Process of the Back side (needs double side polished) Low temperature technology for photonics components a:si wg InP laser InGaAs photodetectors Vias through the Si substrate 49

50 Option 3: Wafer bonding on the back side Fabrication of the EIC Protection of the Front side Fabrication of the PIC Wafer bonding of an PIC on the rear side of an EIC Removal of the Si substrate of the PIC Vias through the Si substrate (TSV) Si Substrate Si Substrate Si Substrate Si Substrate 50

51 Conclusion No unique integration technology Need of integration depends on the targeted applications Hybrid technology for small volume Full integration for medium to large volume Integration of exotic materials possible with AIC 51