New Wave SiP solution for Power

Transcription

1 New Wave SiP solution for Power Vincent Lin Corporate R&D ASE Group APEC March 7 th, 2018 in San Antonio, Texas. 0

2 Outline Challenges Facing Human Society Energy, Environment and Traffic Autonomous Driving and Technologies Needed A approach to reduce energy and resource Sensors, GPU-Based AI, 5G and Cloud The bottleneck : Wireless /PMIC and Inter Data Center SiP Solutions for Power Tool Box of Passive integration for RF and PMIC Tool Box of Si-Photonic Packaging Concluding Remarks 1 1

3 Outline Challenges Facing Human Society Energy, Environment and Traffic Autonomous Driving and Technologies Needed A approach to reduce energy and resource Sensors, GPU-Based AI, 5G and Cloud The bottleneck : Wireless /PMIC and Inter Data Center SiP Solutions for Power Tool Box of Passive integration for RF and PMIC Tool Box of Si-Photonic Packaging Concluding Remarks 2 2

4 Traffic Resource Wasted : Land, time and Power Life-and-Death Matter, Must to take actions 50% Area of Big City Occupied by road and car parking 5% 1.2M Road traffic deaths each year 50 min. Utilization of familiar car 15 M Typical daily commute time (Statistics by World bank & WHO) Seriously Injured in road crashed each year 3

5 Autonomous Driving: Technologies needed AI-GPU based Sensor 5G Platform Optical interconnection CAR CONNECTIVITY DATA CENTER Training Inference 100Mps to 1Gps 100Gps to 1Tps 4 4

6 Outline Challenges Facing Human Society Energy, Environment and Traffic Autonomous Driving and Technologies Needed A approach to reduce energy and resource Sensors, GPU-Based AI, 5G and Cloud The bottleneck : Wireless /PMIC and Inter Data Center SiP Solutions for Power Tool Box of Passive integration for RF and PMIC Tool Box of Si-Photonic Packaging Concluding Remarks 5 5

7 Heterogeneous Integration Solutions Ultra-high speed (>100Gps) E-O modulation/interconnection Data center Ultra-high density I/O (>200K/PKG) Si-Interposer GPU /HPC and AI SiPh Electrical IC Fiber Adv. Packaging Solutions Glass platform : wafer to panel Passives (L/C) & PKG integration RF & PMIC Small form factor WLP (<1mm 2 ) TSV-Last for 8 wafer Sensors 6 6

8 SiP h Electrical IC Fib er Adv. Packaging Solutions Passive integration : Mission Statement of HyPas Platform Evolution of RF-Passives integration : 2D/ 3D TGV/ 3D Cu-P Inductor : RF to PMIC, Integrated with Magnet 7 7

9 Mission Statement of HyPas Platform IPD vs HyPas: IPD : Integrated Passives (L/C) Device HyPas : Hybrid/ High Performance Passives/ Packaging integration solution HyPas Key Features: High AR Cu-P 3D Structure Embedded with Special Material : Ferrite Hi-Ind, and Hi-Cap Capex/Tool compatible with ASE Panel level FO Plan Passive IC RF-Cap Hi-Cap Magnet RF-Ind 1~20nH 140umt RF-Cap Cap. Density: 0.58nF/mm 2 BD Voltage > 70V < 100umt Hi-Cap Cap. Density: 200nF/mm 2 BD Voltage > 5V < 100umt Hi-Ind 0.1~1uH 140umt Embedded Magnet Joint development w/ Tier-1 Passives Company 8

10 Typical RF FEM (PAMiD) Scenario 7 x 5 mm, 6-7 layers coreless substrate 7-10 Acoustic Filters (BAW/SAW) > 30 passives ( most of 0402 Inductor) PA and Switch Module size reduction trend : 20% per year IPD solution to reduce the discrete passives (Source: Yole) Need have solution of Acoustic Filter size reduction and Passives (L/C) integration 9 9

11 2D vs 3D IPD 50% size reduction 10 10

12 TGV 3D Solution: TGV vs Tall Cu-P Tall Cu-P 130um 250um 1/2 Via Pitch 70um 140um 2X Inductor Density RFIC (Si) MIM-Cap. TGV 100um 250um Much Smaller Module RFIC (Si) Cap bank 140um 2.4x2.4x 0.8 mm < 2x2 x0.5mm 11 11

13 Benchmark Discrete Inductor & ASE win Design Rule/Strategy Typical RF range Size: 0.6 x 0.3 mm 2D inductor Ceramic HQ (0.3mmT) TGV G.Tech 3D/250umt, 150um Via Pitch Double RDL: ASE HQ 3D 140umt, 40um Cu-P pitch Single RDL: 3D/ 140um 7 RDL 3D/ 100um 3D/ 50um 3D/ 70um (nh) 12

14 Inductance Inductor : RF to PMIC, Integrated with Magnet PMIC Discrete PMIC SiP RF Range Hi-Ind 2.0*1.6mm, 140umt 10uH 1uH RF-Ind 0.6*0.3mm, 140umt 100nH 10nH Existing Thick Power Ind 2.0*1.6mm, 700umt 1nH 1MHz 10MHz 50MHz 100MHz 1GHz 5GHz Existing Ferrite Develop w/ TDK Frequency Special Magnet material : 1. Bulk magnet thin down to 100um. 2. Material can support to 30MHz. 3. Ring pattern machining. 2mm 13 13

15 Tool Box of RF Packaging RF Key Devices Active Filter BAW PA SAW Switch Passives ASE Corp. Technology Passive Integrated Wafer Level Technology 2D IPD W2W Bonding RDL/AIC Cap +TSV 3D IPD C2W Bonding Bump/ Cu Pillar WL Molding BAW Filter BAW WLP <1mm HRSi TSV Cap 0.25mm Passive Magnet SW Compact FEM Cap SAW/BAW PA 14 14

16 SiP h Electrical IC Fib er Adv. Packaging Solutions Si-Photonics Packaging Overview: Customer Voice- Data Center Switch Challenges Typical SiPh Packaging Structure- Module level and System level SiPh Module Integration approaches for DC Switch Tool Box Planning of SiPh Packaging 15 15

17 Silicon Photonics (SiPh) CMOS Compatible SOI-platform : Planner Wave guide (λ = µm) Light Source : Discrete or Epi-Layer transfer E-O Modulator : Robust MZI Si-WG instead of Direct LD modulation Receiver : integrated with SiGe Photo Diode Optical coupling : micro structure instead of discrete lens to improve the eff. CMOS Photonic Laser Bond Options Fiber Attach Options Epi-layer Transfer Grating Coupling (Active) Si bench (Active) Si bench (Passive) Si Bench (Passive) Edge Coupling (Active) 16 16

18 Data Center Architecture >100m 17

19 Typical SiPh Packaging Structure- Module level and System level Module level- QSFP System level Switch/ SiPh Modules QSFP SiPh module w/ edge coupling laser/fiber (>100G) LD Submount Electrical IC Fiber SiPh QSFP SiPh module w/ vertical coupling laser /fiber (>100G) Integrated on (>400G) SiPh Module IC >70mm LD Submount Electrical IC SiPh 18

20 Enter Strategy of SiPh Foundry-OSATs ASIC model Base wafer E-Die Photonics Chip Design SiPh / Electrical Chip design Foundry SiPh / Electrical IC Fabrication OSAT/ CoW Platform OSAT/ Optical Assy OSAT/ Module Assy Optical integration & Module level Electrical integration & Wafer level Post-fab & Bumping Wafer sorting/ CoW test WL CoW assembly Production x1 Q4 17 Qual x1 Q4 18 Laser diode attachment Packaging for Laser module WL optical test In Development Module assembly Functional testing In Development Phase-I Phase-II Phase-III 19

21 Tool Box planning of SiPh Packaging Ready Developing Evaluating Key Elements Silicon Optical Final Packaging Special wafer level process SiPh Driver /TIA DSP Switch LD PD Lens Fiber array Metal housing DRIE trench/tsv UBM + Bumping PI DAM CoC PD DA/WB ASE Technology 1 st level ASSY. 2 nd level ASSY. Final ASSY. CoCoS LD Passive alignment WL Optical testing LD module active alignment Fiber active alignment - edge Fiber active alignment - vertical Metal housing ASSY LD Submount IC SiPh Fiber LD Submount IC SiPh 20

22 SiPh Packaging Roadmap Technology Long-term Laser packaging Laser die attachment Laser module packaging Module with fiber E-Die Submount Submount Short-term O/E integration: CoW PSM4: 4x25G WDM: CWDM Modulation: NRZ PKG I/O: WB E-Die P-Die P-Die P-Die E-Die Submount E-Die P-Die P-Die E-Die E-Die1 P-Die P-Die E-Die2 E-Die O/E integration: Multi-die CoW 16x25G/8x50G/NRZ/PAM4 Multi-channel: Multiple E-die CWDM: Single λ Multiple λ PKG I/O: Short WB & FC & Back side TSV QSFP28 100G QSFP-DD (200/400G & beyond) Data Rate 21

23 Outline Challenges Facing Human Society Energy, Environment and Traffic Autonomous Driving and Technologies Needed A approach to reduce energy and resource Sensors, GPU-Based AI, 5G and Cloud The bottleneck : Wireless /PMIC and Inter Data Center SiP Solutions for Power Tool Box of Passive integration for RF and PMIC Tool Box of Si-Photonic Packaging Concluding Remarks 22 22

24 Concluding Remarks Autonomous Driving System Drive IOE key technologies in place not only for economic, but Human Life Key Technologies Sensors, AI, 5G and Optical I/O of DC ASE Adv. Packaging Solutions Extending the Packaging Spectrum Provide Electronic OSAT service and system integration Extend to Wave Devices Packaging, from RF, MM-Wave and Light-Wave 23 23

25 Thank You