EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

Transcription

1 EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1

2 Prof. Zhuo Feng Office: EERC 730 Phone: Class Website Check the class website for lecture materials, assignments and announcements Schedule TR 12:35pm-13:50pm EERC 227 Office hours: TR 4:30pm 5:30pm or by appointments 1.2

3 Topics (tentative) CMOS circuit overview Fabrication and layout MOS Transistor I-V Characteristics DC & Transient Responses Delay and Power Estimation Logic Effort Interconnect Combinational Circuits Sequential Circuits Clock Distribution Memory Package, Power, I/O 1.3

4 Grading Policy Homework: 40% Quizzes 10% Mid-term Exam: 20% Final Exam: 30% Late homework: 50% penalty/day. Letter Grades: A: 85~100; AB: 80~84; B: 75~79; BC: 70~74; C: 65~69; D: 60~64; F: 0~59 1.4

5 Moore s law in Microprocessors 1.5 (MT) Tra ansistors X growth in 1.96 years! P6 Pentium proc Year Transistors on Lead Microprocessors double every 2 years Courtesy, Intel

6 Die Size Growth 100 Die size (mm) Pentium P6 486 p proc ~7% growth per year ~2X growth in 10 years Year Die size grows by 14% to satisfy Moore s Law Courtesy, Intel 1.6

7 Frequenc cy (Mhz) Frequency Doubles every 2 years P6 Pentium proc Year Lead Microprocessors frequency doubles every 2 years Courtesy, Intel 1.7

8 Power Dissipation 100 Pentium proc P6 Power (Watts) Year Lead Microprocessors power continues to increase Courtesy, Intel 1.8

9 Why Scaling? Technology shrinks by ~0.7 per generation With every generation can integrate 2x more functions on a chip; chip cost does not increase significantly Cost of a function decreases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient i design methods Exploit different levels of abstraction 1.9

10 Deep pipeline (2001) Very fast clock KB L2$ Characteristics nm process M transistors GHz Up to 160 W 32/64-bit word size 478-pin PGA Units start to become invisible on this scale Pentium

11 Pentium M Pentium III derivative Better power efficiency 1-2 MB L2$ Characteristics nm process 140M transistors GHz 6-25 W 32-bit word size 478-pin PGA Cache dominates chip area

12 Core2 Duo Dual core (2006) 1-2 MB L2$ / core Characteristics nm process 291M transistors GHz 65 W 32/64 bit word size 775 pin LGA Much better performance/power efficiency

13 Core i7 Quad core (& more) Pentium-style architecture 2 MB L3$ / core Characteristics nm process 731M transistors t GHz Up to 130 W 32/64 bit word size 1366-pin LGA Multithreading On-die memory controller

14 Atom Low power CPU for netbooks Pentium-style architecture 512KB+ L2$ Characteristics nm process 47M transistors GHz W 32/64-bit word size 441-pin FCBGA Low voltage ( V) operation Excellent performance/power

15 Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT S n+ G DEVICE D n

16 Design Metrics How to evaluate performance of a digital circuit (gate, block, )? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function

17 Cost of Integrated Circuits NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Recurrent costs silicon processing, packaging, test proportional p to volume proportional to chip area

18 Cost per Transistor cost: -per-transistor Fabrication capital cost per transistor (Moore s law)

19 Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors Si Si Si Si Si Si Si Si Si

20 Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing i electron, called hole (p-type) Si Si Si Si Si Si - + Si + As Si Si B - Si Si Si Si Si Si Si N-type P-type 1.20

21 P-N Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction Current flow direction p-type anode n-type cathode Electron flow direction 1.21

22 NMOS Transistor Four terminals: gate, source, drain, body Gate oxide body stack looks like a capacitor Gate and body are conductors SiO 2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Even though gate is no longer made of metal Substrate, body or bulk 1.22

23 NMOS Operation Body is commonly tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF Source Gate Drain Polysilicon SiO 2 n+ p n+ bulk Si S 0 D 1.23

24 NMOS Operation Cont. When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON Source Gate Drain Polysilicon SiO 2 n+ p n+ bulk Si S 1 D 1.24

25 PMOS Transistor Similar, but doping and voltages reversed Body tied to high voltage (V DD ) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior 1.25

26 GND = 0 V Power Supply Voltage In 1980 s, V DD = 5V V DD has decreased in modern processes High V DD would damage modern tiny transistors Lower V DD saves power V DD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, 1.26

27 Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain g=0 g=1 d d d nmos g OFF ON s s s d d d pmos g ON OFF s s s 1.27

28 CMOS Inverter A 0 Y V DD 1 A Y A Y GND 1.28

29 CMOS Inverter A Y A Y V DD OFF A=1 Y=0 ON GND 1.29

30 CMOS Inverter A Y A Y V DD ON A=0 Y=1 OFF GND 1.30

31 CMOS NAND Gate A B Y Y 1 0 A 1 1 B 1.31

32 CMOS NAND Gate A B Y ON ON 0 1 Y=1 A=0 1 0 OFF 1 1 B=0 OFF 1.32

33 CMOS NAND Gate A B Y OFF ON Y= A=0 B=1 OFF ON 1.33

34 CMOS NAND Gate A B Y ON OFF Y= A=1 B=0 ON OFF 1.34

35 CMOS NAND Gate A B Y OFF OFF Y= A=1 B=1 ON ON 1.35

36 CMOS NOR Gate A B Y A B Y 1.36

37 3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0 A Y B C 1.37

38 CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section section of wafer in a simplified manufacturing process 1.38

39 Inverter Cross-sectionsection Typically use P-type substrate for NMOS transistors Requires N-well for body of PMOS transistors Silicon dioxide (SiO2) prevents metal from shorting to other layers input A GND Y V DD SiO 2 n+ diffusion n+ n+ p+ p+ n well p substrate p+ diffusion polysilicon metal1 nmos transistor t pmos transistor t 1.39

40 Well and Substrate Taps P-type substrate (body) must be tied to GND N-well is tied to V DD Use heavily doped well and substrate contacts ( taps) Establish a good ohmic contact providing low resistance for bidirectional current flow 1.40

41 Inverter Mask Set Transistors and wires are defined by masks Inverter can be obtained using six masks: n-well, polysilicon, n+ diffusion, p+ diffusion, contacts and metal Cross-section taken along dashed line A Y GND V DD substrate tap nmos transistor pmos transistor well tap 1.41

42 Six masks n-well Detailed Mask Views Polysilicon N+ diffusion P+ diffusion Contact Metal 1.42

43 Fabrication Chips are built in huge factories called fabs Contain clean rooms as large as football fields Courtesy of International Business Machines (IBM) Corporation. Unauthorized use not permitted. 1.43

44 Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO 2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO 2 p substrate 1.44

45 Oxidation Grow SiO 2 on top of Si wafer Celcius with H 2 OorO O 2 in oxidation furnace SiO 2 p substrate 1.45

46 Spin on photoresist Photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light Photoresist SiO 2 psubstrate 1.46

47 Lithography Expose photoresist through n-well mask Strip off exposed photoresist Photoresist SiO 2 p substrate 1.47

48 Etch Etch oxide with hydrofluoric acid (HF) Only attacks oxide where resist has been exposed Photoresist SiO 2 p substrate 1.48

49 Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranha etch Necessary so resist doesn t melt in next step SiO SO 2 p substrate 1.49

50 N-well N-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implantation Blast wafer with beam of As ions Ions blocked by SiO 2, only enter exposed Si SiO 2 n well 1.50

51 Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps p substrate n well 1.51

52 Polysilicon oys Deposit very thin layer of gate oxide (SiO2) < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH 4 ) Forms many small crystals called polysilicon Heavily doped to be good conductor 1.52

53 Polysilicon Patterning Use same lithography process to pattern polysilicon Polysilicon 1.53

54 Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms NMOS source, drain, and n- well contact 1.54

55 N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn t melt during later processing psubstrate n well 1.55

56 N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion 1.56

57 N-diffusion cont. Strip off oxide to complete patterning step 1.57

58 P-Diffusion Similar set of steps form p+ diffusion regions for pmos source and drain and substrate contact p+ Diffusion 1.58

59 Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed Contact p+ n+ n+ p+ p+ n+ Thick field oxide p substrate n well 1.59

60 Metallization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires Metal 1.60

61 Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of λ = f/2 Eg E.g. λ =03μm 0.3 in06μm 0.6 process 1.61

62 Simplified Design Rules Conservative rules to get you started 1.62

63 Inverter Layout Transistor dimensions specified as Width / Length Minimum size is 4λ / 2λ, sometimes called 1 unit In f = 0.6 μm process, this is 1.2 μm wide, 0.6 μm long 1.63

64 Summary MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip! 1.64