Silicon photonics platform for high volume manufacturing. Peter De Dobbelaere Luxtera Inc. 7/11/2018

Transcription

1 Silicon photonics platform for high volume manufacturing Peter De Dobbelaere Luxtera Inc. 7/11/2018 Luxtera Proprietary

2 Outline Introduction Silicon Photonics Technology Wafer Process Modules Photonic Devices & Fiber Interface Light source Integration Integration with Electronics Design examples: 25G NRZ, PAM 4 Silicon Photonics Manufacturing Chipset Manufacturing flow Transceiver Manufacturing flow Roadmap towards Higher Data Rates and ASIC Integration Improving technology performance 2.5D Integration for ASIC integration Page 2

3 Silicon Photonics: What? Why? When? What? Technology enabling design and manufacture of integrated optical circuits using silicon material system and silicon industry, technologies & tools Why? By leveraging from IC industry: low cost, high volume manufacturing, high integration level, tight integration with electronics. Most applications in high speed interconnect (e.g. optical transceivers), some in biotech and sensing. When? Proposed in mid 80s, currently: in volume production and many companies developing the technology: IBM, Intel, Skorpios Technologies, Mellanox, Global Foundries, Elenion, Juniper/Aurrion, Cisco/Lightwire, Luxtera, Sicoya, Ayar Labs, Huawei, Acacia Communications, STMicroelectronics, Page 3

4 Luxtera Company Introduction Founded in 2001, Luxtera has the world s first Silicon Photonics platform proven in volume transceiver production Worldwide leader in silicon photonics technology with over quarter billion investment in R&D, over 250 patent filings In continuous production since 2009, ~ 2 Mu transceivers deployed Cloud Operators require cost effective 100G Single Mode Optics at high volume. Shipments of 100G products started in Q1 2016, with now more than 600 Ku deployed leading the market on price/performance and availability. Luxtera created PSM4 market and now broadening portfolio to dominate intra data center and mobile front haul (< 10 km) through high performance an lower cost. Top tier supply base and highly automated manufacturing infrastructure ready for > 1M units/year Continuing R&D Investment: Roadmap supports 5 year hyper growth cycle of 25/50/100/400G SMF transceivers leading to ASIC integration. Page 4

5 Luxtera s Approach Fabless manufacturing, leveraging semi conductor technology Commercial fabs for photonic wafer fabrication OSAT for test & 1 st level packaging Advanced photonic device libraries High signal to noise ratio required > low insertion losses Efficient & High bandwidth modulators and detectors Simplify optical assembly and test Wafer level assembly and test where possible Test methodologies from semiconductor industry, e.g. BIST Electronic and photonic circuit design Integrated automated design infrastructure for photonics and electronics Reliable and stable light source Page 5

6 Outline Introduction Silicon Photonics Technology Wafer Process Modules Photonic Devices & Fiber Interface Light source Integration Integration with Electronics Design examples: 25G NRZ, PAM 4 Silicon Photonics Manufacturing Chipset Manufacturing flow Transceiver Manufacturing flow Roadmap towards Higher Data Rates and ASIC Integration Improving technology performance 2.5D Integration for ASIC integration Page 6

7 Silicon Photonics Wafer/Device X section Salicide blocking layer Contacts Metal 1 Ge protection layer Field oxide Ge Profile optical mode Buried oxide Silicon substrate PASSIVE WAVEGUIDE PHASE MODULATOR WAVEGUIDE PHOTODETECTOR Silicon photonics devices are formed on a silicon on insulator (SOI) substrate: Fine lithography and etch for formation of photonic devices Selective epitaxy of germanium for photodetectors Implants for phase modulators and contacts Standard metal back end processing (~4 6 metal layers) Page 7

8 Passive Photonics: Lithography and Etch Critical parameters: Min trench CD (< 100 nm) Etch depth control Simultaneous definition of multiple geometries: Isolated, curved waveguides Narrow, dense trenches Dense arrays of holes Isolated waveguides (~0.3 3 um) Arrays of holes Pairs of waveguides with varying spacing In line metrology for tight process control Sidewall roughness may be critical Grating coupler: dense trenches/lines, curved Corrugated structures Page 8

9 Active Photonics: selective Ge Epitaxy Patterned silicon oxide growth mask on SOI substrate Pre growth cleaning of exposed silicon surface Selective growth of Ge on exposed silicon surface Deposition of Ge protection layer/ dielectric Implant and activation of dopants Top view SEM: Selectivity X section SEM: Ge on Si X section TEM: Relaxed Ge film on Si Page 9

10 Photonic Device Library Development Over 15 years experience in developing photonic device libraries in 3 different fab processes Systematic development approach: 1. Device concept 2. Concept simulation, design of experiments (DOE) 3. Tape out of DOE & DVT (automated wafer level test is essential) 4. Optimize design in second DOE 5. Select design, qualify & generate behavioral models (P, V, T, ) Many opportunities for improved performance and functionality Developing library in process co developed with TSMC: drastically improved performance by design & process capability Page 10

11 Silicon Photonic Devices: Waveguides (WG) High index contrast rib waveguides Propagate only TE mode Key performance parameter: insertion loss: 0.8 db/cm (1310 nm) Root cause: absorption, scattering, Multimode waveguides for long straight sections Insertion loss fundamental mode: 0.25 db/cm (1310 nm) Low loss (<< 0.1 db) turning bends and tapers Fundamental mode MM WG WG transitions Single mode WG WG X section WG tapers Low loss bends WG routing US #7,881,575 Page 11

12 Silicon Photonic Devices: Passive Devices Multiple types of splitters for different functions in photonic ICs: Y junction: 1:2 splitter Directional coupler (DC) Optical taps (50%, 10%, 5%, 1%) Key: reproducible and on target splitting ratio Multi Mode Interference (MMI) Coupler Optical taps and splitters Y junction DC MMI Page 12

13 Silicon Photonic Devices: Coupling Light In Out Silicon Waveguide Taper 1 D grating SMF core Silicon Waveguide Inverse Taper SMF core Grating Couplers: Low coupling loss, dependent Fully compatible with CMOS Processes No need for accurate dicing and end face preparation Enables wafer scale testing High density & flexibility in arrangement of optical interfaces Edge coupling with inverse tapers: Need additional optics to enable loss loss coupling Less dependent Difficult to fabricate (etch tip, non standard layer thicknesses & facet formation) Low facet reflections Optical interfaces only at edge of die Page 13

14 Silicon Photonics: Grating Coupler (GC) Design Performance optimization: Apodize diffractive grating to match with SMF mode Optimize BOX thickness Curved grating Remove BEOL dielectrics over GC 1 D GC for coupling light with known polarization in chip or coupling light out of chip. Coupling loss w/smf: < 1 db 2 D GC for coupling light from SMF into chip. Coupling loss w/smf: < 2.1 db US #6,788,847 US #7,245,803 US #7,006,732 US #8,280,207 Page 14

15 Silicon Photonic Devices: Optical Phase Modulators Contact & backend Doped Silicon Rib Waveguide n+ n n p p p+ Buried Oxide Silicon Substrate Physical mechanism for optical phase modulation: carrier depletion effect in pn junction formed in silicon waveguide Optimized performance by maximizing overlap between depletion region and propagating optical mode System level trade offs between: phase shifting efficiency (typ.: V L =2.4 V.cm, insertion loss (typ.: 0.6 db/mm) and capacitance (typ.: 300fF/mm, 0 V) US #7,116,853 US #7,085,443 US #7,251,408 US #9,541,775 Page 15

16 Silicon Photonic Devices: Waveguide Photodetectors Silicon Oxide epi mask Metal Contact Shallow trench Germanium Silicon WG Germanium Ge Silicon n + Si i Si SiO 2 p + Si X section PD: Ge layer Top view PD: Ge strip (no contacts) Double Hetero structure PD Waveguide photo detectors (WGPD) are formed by selective Ge epitaxy Several architectures have been developed: PIN, SH, DH, APD, Double Hetero structure (DH) photodetector has low processing complexity (no contacts to Ge) and has high performance: Responsivity: 1.05 A/W, Idark < 100 na, BW > 43 GHz, C < 10 ff US #7,397,101 US #7,613,369 Page 16

17 Integration Photonics & Electronics Monolithic Integration Single chip solution Lower parasitics between photonics and electronics More complex wafer fabrication process Less area efficient Moving to advanced nodes is complicated & very expensive Monolithic SiP IC Electronics + Photonics Hybrid Integration Multi chip solution Higher parasitics between photonic and electronics Photonics & electronics fabrication processes decoupled Efficient use of area: photonics doesn t take area on (expensive) advanced e node Flexible electronic node selection (CMOS, BiCMOS,..), enabling integration with 3rd party IP Micro bumps Electronic IC Photonic IC Page 17

18 Silicon Photonics Process Design Kit (PDK) Leverage design methodologies from electronics industry Design Kit running on Cadence toolset Behavioral models for library elements representing process corners seen over several CMOS lots Automatic design rule checking (DRC) for optics and electronics components Layout vs Schematic Check (LVS): E to E, E to O, and O to O connectivity and device extraction End to end simulation capability LVS verifies that the layout devices and connectivity match the schematic at all levels of hierarchy. Luxtera Proprietary 7/24/2018 Page 18

19 Light Source Example: LaMP (since 2008) Reliable and stable light source Micro packed InP laser diode for pluggable modules (require co packaging) Remote light source for highly integrated and dense systems decouples light source and transceiver functions, e.g. ASIC integration (High T, serviceability, yield, ) High wall plug efficiency: > 15% (incl. coupling efficiency LD to Si P IC) Single light source for up to 8 channels 25 Gbps (PSM 4) Turning Mirror Isolator Lens Laser 2.5mm x 1.5mm x 1.2mm US #8,772,704 US #8,168,939 Page 19

20 Outline Introduction Silicon Photonics Technology Wafer Process Modules Photonic Devices & Fiber Interface Light source Integration Integration with Electronics Design examples: 25G NRZ, PAM 4 Silicon Photonics Manufacturing Chipset Manufacturing flow Transceiver Manufacturing flow Roadmap towards Higher Data Rates and ASIC Integration Improving technology performance 2.5D Integration for ASIC integration Page 20

21 Silicon Photonics PSM 4 4x25 Gbps Transceiver Serial Interface 1:4 Optical Splitter Digital Control SFP In Single Mode Waveguide HSPM TX Control LSPM Cal. ADC Tap Monitor PD SPGC Optical Outputs Distributed MZI, Driver & Calibration TX Laser Laser Driver SFP Out SFP Driver PD Receiver PSGC RX Optical Inputs US #9,813,152 Page 21

22 Transmitter Design SPGC HSPM TX Control HSPM HSPM HSPM ADC LSPM Tap Monitor PD P P out in 1 cos 2 HSPM HSPM HSPM HSPM Cal. SPGC Δ Mach Zehnder Interferometer (MZI) modulators with control/calibration. Significant power and performance improvement by using segmented MZI with digital timing between the segments 0.9 V CMOS driving circuitry High index contrast allows the MZI to be folded up to minimize area A single laser diode provides multiple channels with CW light US #7,039,258 US #7,450,787 US #7,515,775 US #7,916,377 Page 22

23 PAM4 Modulation by segmented MZI SPGC TX Control ADC 26 GB/s PAM 4 TX eye LSB HSPM HSPM HSPM LSPM Tap Cal. MSB HSPM HSPM HSPM SPGC MZI Generation pj/bit ER PSM4 (NRZ, 26 Gbps) dB CWDM2 (PAM4, 26 GBps) dB PAM 4 modulation can be elegantly implemented by use of a segmented MZI US #8,238,014, #8,665,508, #9,548,811 Page 23

24 Receiver Design (example): Take advantage of low PD capacitance Traditional PD Coupling Differential PD Coupling (example) VPD TIA+LA R VPD LA Low input impedance (R in ) R High input impedance (R in ) BW 3dB 2 R in 1 C PD C Other BW 3dB 1 2 R 2C PD C Other The parasitic capacitance of a waveguide photodetector is significantly lower than that of a conventional surface illuminated photodetector. This allows alternative receiver circuit designs with higher performance. US #9,768,747 Page 24

25 Outline Introduction Silicon Photonics Technology Wafer Process Modules Photonic Devices & Fiber Interface Light source Integration Integration with Electronics Design examples: 25G NRZ, PAM 4 Silicon Photonics Manufacturing Chipset Manufacturing flow Transceiver Manufacturing flow Roadmap towards Higher Data Rates and ASIC Integration Improving technology performance 2.5D Integration for ASIC integration Page 25

26 Transceiver Manufacturing & Test Flow Manufacturing process of silicon photonics transceiver consists of: Wafer manufacturing (Foundry/Fab) Processing / Metrology Wafer acceptance test Chipset assembly and test (OSAT) Die sort Bumping, Assembly, Test Singulation Module assembly test (CM) Die & wire bonding Fiber bonding Module test Page 26

27 Transceiver Manufacturing and Test Flow MEMS Base Wafer MEMS Assembly Burn in O/E Sort Singulation E wafer Process E wafer E WAT E Sort Singulation Wafer scale process P wafer Process P wafer O/E WAT O/E Sort Chip on Wafer LS on Chip on Wafer Chipset Test Singulation Board Assembly Fiber Attach Final Test Page 27

28 Light Source (LaMP) Wafer Level Test Page 28

29 Optical Test for Development, WAT and Sort High efficiency and capable optical test is a must for development and manufacturing Leveraging commercial prober system with some modifications including automated active alignment and planarization, test gage IL measurement better than 0.1 db. Performs both passive optical and electro optical tests Fully automated system: 200 and 300 mm wafers from FOUP, FOSB or cassettes. US #7,183,759 US #7,224,174 Page 29

30 Wafer Scale Assembly: Chip to wafer bonding of electronic IC Technology developed by multiple OSATs Leverages technology developed for semiconductor electronics industry Enables electrical interconnect: High density: pitch ~ 50 micron Low parasitics Wafer level assembly & test Electronic IC Cu Pillars Solder Photonic IC Page 30

31 Wafer Scale Assembly: Light Source to Si P Wafer Bonding High Throughput Optical Assembly Tool based on off the shelf pick and place tool with customized bond heads 12 Assembled Photonics Wafer Chuck (IC Assemblies e die on p die still in wafer form) 6 LaMP Wafer on Blue Tape LaMP wafer loading stage During assembly bond two heads move alternating between a LaMP wafer and silicon photonics wafer Bond head performs active alignment High throughput optical assembly Built in process monitoring Page 31

32 Wafer level assembly & BIST for Known Good (KG) chipset Test can be a significant cost adder for high speed optical transceivers Hybrid architecture + wafer level assembly allows greater overall test coverage: E die: E sort P die: E & O sort Several internal monitors for diagnostics and control (taps and unbiased MPD) High speed electrical loopback enabled by internal PRBS generation on TX & PRBS checker on RX High speed optical loopback enabled by routing 2 nd output of MZI modulator to RX KG assembled chipset (optical engine) Page 32

33 100G PSM 4 Known Good Transceiver Engine Known good assembled chipset (P die, E die & light source) as delivered to module assembly line Chipset is fully tested Chipset assembled in transceiver module Fiber array as optical interface Active alignment fiber array to chip using in house design tool Page 33

34 Fully Automated Active Alignment of Fiber Array to Si P IC Panel level active alignment of fiber array Extensive automated process monitoring Full traceability of panel, PCBA, chipset and fiber array Page 34

35 Outline Introduction Silicon Photonics Technology Wafer Process Modules Photonic Devices & Fiber Interface Light source Integration Integration with Electronics Design examples: 25G NRZ, PAM 4 Silicon Photonics Manufacturing Chipset Manufacturing flow Transceiver Manufacturing flow Roadmap towards Higher Data Rates and ASIC Integration Improving technology performance 2.5D Integration for ASIC integration Page 35

36 Luxtera s Technology Transition for Next Generation Products Next generation products (e.g. 400 G, ASIC integration, ) need: Through Substrate Vias (TSV): High speed signals: parasitics (on die line, pad, wire) affect signal integrity, extra power dissipation to overcome Power supply lines: parasitics, due to limitations metal stack, cause: (1) supply drop and variability (2) power supply noise (3) limited supply isolation/separation (4) current switching generates more supply noise Improved photonic device performance Lower coupling/insertion losses More efficient phase modulators Higher band width photodetectors Supply chain ecosystem Si P process and PDK accessible to 3rd parties through Luxtera Integrated PDK with advanced nodes & Page 36

37 Device Library Development: Overview Device type Parameter Unit Previous Technology TSMC Process Comment Optical I/O SPGC loss db At peak wavelength (Grating couplers) PSGC loss db At peak wavelength Waveguide SMW loss db/mm Detector HSPD Responsivity A/W HSPD GHz HSPD Capacitance ff 6 6 Modulator HSPM Insertion Loss db/mm HSPM Phase Shift Degree/mm 10.5 (2.5 V) 17.5 (1.8 V) HSPM OMA dbm mm, 0 dbm input Excellent performance enabled by process flexibility and new design concepts Preliminary reliability qualifications of active devices and backend have started Full qualification is expected to be completed by Q Luxtera, Inc. Proprietary 7/24/2018 Page 37

38 TSMC process w/ TSV capability Current development towards 400G product family: Front end process frozen, running final integration lots Ready for production tape out in August 2018 Advanced library: pre qualification completed and passed, updating PDK 2.5D integration (Chip on Chip on Substrate process TSMC Amkor): TSV formation in SOI, first assemblies of small interposer test vehicles completed Page 38

39 Expected Evolution of Electronic & Photonic Integration CONTEMPORARY Today Front Pluggable Modules EMERGING 2017 Embedded Optical Modules NEXT ASIC/SOC Integration QSFP28 Module Embedded Optics Module Co packaged ASIC & Photonics ASIC Re timer Front Module ASIC MBO Module Fiber ASIC w/ photonics Fiber Luxtera, Inc. Proprietary 7/24/2018 Page 39

40 Concept of co packaging for Photonics / ASIC integration Switch IC w/integrated optics Power supply Fan 12.8 Tbps Transceiver HD optical interface Front plate w/ MPO connectors + front pluggable TCVRs Remote light sources Switch ASIC 25 Tbps Dense fiber cabling Co packaging of ASIC and transceivers for highdensity and system level power reduction Expected first application: Integrated Ethernet switches (> 25 Tbps) Required technologies: Standardization of internal interfaces Advanced 2.5D technologies Very high density optical interface that can withstand high temperatures Remote light source US #8,831,437 Page 40

41 When do we expect introduction of Integrated Optics? 100,000 51,200 25,600 51,200 12,800 25,600 10,000 6,400 12,800 Total Switch Chip/Serdes Bandwidth (Gbps) 1, ,280 3, Integrated Optics Luxtera, Inc. Proprietary 7/24/2018 Page 41

42 Enabling technologies for Integrated Optics : Design Pre requisites for optical tile design: standardization Which functions reside in switch tile(s)/optical tile(s) Electrical bus (USR) connecting switch tile(s) with optical tile(s): low power dissipation < 1 pj/bit?, high density (substrate design rules), routing on substrate is very challenging Design and layout of transceiver circuits: High density (previously not a strong requirement) Low power and high performance (interoperability with pluggable modules) Advanced silicon photonics technology: Further optimization of photonics performance, lower coupling losses, higher modulation efficiency, high performance photodetectors Page 42

43 Enabling technologies for Integrated Optics Remote Light Source (RLS): Light source is NOT integrated in the assembly RLS: efficient CW DFB laser diodes packaged in thermally enhanced, low cost package with, driver/control circuits and fiber interface Located in cool location on host PCB for efficient operation and serviceability if needed Fiber Interface/connector: High density: > 200 optical I/Os /Optical Tile Low loss optical connector interface operating at high T (~100 C) with fan out to standard optical connector (e.g. MPO) Low insertion force & robust Page 43

44 200 Gbps Module with Duplex Multicore Fiber Interface 8x28 Gbps Chipset with modified fiber interface 8x28 Gbps Embedded Optics Module with MCF interface Luxtera Inc. Proprietary Multicore fiber (8 cores) Multi core fiber (MCF) transceiver: Grating couplers placed in a dense array allowing an optical interface to a multicore fiber Features: Transceiver performance equivalent as multi fiber implementation Very high density interface optical interface to the chip: > 100 Tb/mm2 ECOC 2017, Th.2.A.4: Hayashi et al End to End Multi Core Fibre Transmission Link Enabled by Silicon Photonics Transceiver with Grating Coupler Array Opt. Commun. Lab., Sumitomo Electric Industries, Ltd., Luxtera Inc, Innovation Core SEI, Inc. 7/24/2018 Page 44

45 Enabling technologies for Integrated Optics O wafer WAT O wafer O Sort Incoming Inspection O wafer E Sort MEOL Wafer Foundry E wafer WAT Incoming Inspection E Wafer Bumping E Wafer E sort ASIC wafer WAT Incoming Inspection ASIC probe ASIC C4 bumping Tentative flow of complex supply chain, leveraging semiconductor industry: O die and E die: respective die forming optical tiles Known Good Die (O die, E die & Switch ASIC) must be used, in line test strategy is very important MEOL: process of front side bumping, thinning and RDL/bumping on the back side of the O wafer CoCoS or CoWoS Optical assembly similar to transceiver module assembly Test strategy and coverage Dice Dice Dice OSAT Module Assembly CoCoS CoCoS Test Incoming Inspection Fiber Array Attach Module Assembly Final test Module Organic Substrate Fiber Connector Hardware Page 45

46 How a co packaged solution could look like Remote Light Source Arrays Single Mode Fiber (I/O) Switch Tiles Fiber for (RLS) Optical Tiles Optical Connectors Page 46

47 Summary: Silicon Photonics Scales In Performance: Advanced photonic device libraries allow link margin & performance needed for ever increasing data rates Latest CMOS technology nodes are used for electronic circuits for optical transceivers (e.g. 7 nm) Density scaling in multiple dimensions: data rate, modulation format, wavelength, spatial Enables close integration with ASICs: Very large scale integration & remote III V light source In Manufacturing: Leverages semiconductor industry manufacturing infrastructure (fabless) Leverages semiconductor technology roadmap OSAT for Wafer Test & Assembly DFM, DFT, DFR, Simplified and highly automated optical assembly Page 47

48 Acknowledgement: This presentation contains work of the entire Luxtera team and its past and present technology partners, their contributions are greatly acknowledged. Thank you for your interest. Luxtera Proprietary