Signal Integrity Modeling and Measurement of TSV in 3D IC

Transcription

1 Signal Integrity Modeling and Measurement of TSV in 3D IC Joungho Kim KAIST 1

2 Contents 1) Introduction 2) 2.5D/3D Architectures with TSV and Interposer 3) Signal integrity, Channel bandwidth, ISI and Equalization 4) Power integrity Design 5) Future TSV and Interposer Structure 6) Summary 2

3 Semiconductor Requirements for Smart Mobile Applications - Low power - High performance - Multi-function - Small size - Low cost 3

4 Mobile Application with Increasing I/O count and Bandwidth Bandwidth 50 GB/s Target on Mobile Applications! Wide I/O Ultra book 12.8 GB/s Wide I/O 6.4 GB/s iphone4 Galaxy S2 ipad2 Galaxy S3 iphone5 iphonex LPDDR3 ipadx 4.3 GB/s LPDDR2 3.2 GB/s LPDDR1 Bus width (IO count) Bus width (IO count) 4

5 Why Interposer in Mobile Application? Mobile application requires Faster computing Higher resolution display Longer battery life Compact size Memory Memory Memory Memory Large number of I/O count 10K Low power consumption reduced more than 50 % Short interconnect length hundreds of µm order TSV availability Dense routability Application processor Silicon Interposer Package 5

6 Low Power TB/s Bandwidth 3D IC Structure TB/s Coaxial TSV Analog Chips TB/s Waveguide Interconnect Stacked Memories Wireless Power Transfer Receiver Chip Antenna Chip RF Chip TB/s Coaxial TSV Embedded Si-based Devices Embedded Passive& Filter Processor Silicon Interposer Package Substrate Radioactivity Sensor MEMS & Bio Sensor Innovative new vertical & horizontal Interconnections for TB/s Bandwidth in 3D IC Low Power system using WPT chip Silicon Interposer Embedded Passive / Active Devices 6

7 Key Technology : TSV (Through Silicon Via) 3 rd Chip (Thinned Substrate) Short Interconnection Reduced RC Delays Low Impedance for Power Distribution Network Low Power Consumption Heat Dissipation Through Via 2 nd Chip (Thinned Substrate) 1 st Chip Under fill Dielectric Dielectric Under fill Multi-level On-chip Interconnect SiO2 No Space Limitation for Interconnection High Density Chip Wiring No Limitation of I/O Number No Limitation of I/O Pitch Small Area Package Si-Substrate 3D TSV Stacked IC 7

8 Frequency-dependent Loss of Through Silicon Via Frequency dependent term 0-1 C insulator G Si sub Leakage current Cu SiO 2 Si Insertion loss (db) Capacitive region Resistive region Loss term Frequency (GHz) 8

9 Analysis of a TSV Channel with Insulator Thickness of TSV Insulator thickness of TSV (t) Signal Top Ground Top C Insulator =1.6 pf C Insulator =2.6 pf C Insulator /2 C Insulator /2 S21 magnitude (db) C Insulator =7.8 pf Insulator thickness of TSV Signal Bottom Leakage through silicon substrate dominantly increases due to lowered impedance with increased C insulator in region [A]. Insulator thickness dominantly affects frequency dependent loss of a TSV channel in region [A]. C Insulator /2 C Insulator /2 Leakage current Ground Bottom -3 [A] Frequency (GHz) Equivalent circuit model ( t = 0.5um ) Equivalent circuit model ( t = 0.3um ) Equivalent circuit model ( t = 0.1um ) 20 9

10 TSV Depletion Phenomenon Depending on DC Bias Voltage V bias (V FB < V bias < V Th ) SiO 2 Copper Depletion region L TSV M O S contact R TSV C ox C ox C depl L TSV R TSV Silicon TSV model without considering depletion C TSV = C C ox ox C + C depl depl TSV has MOS structure depletion occurs depending on TSV bias voltage TSV capacitance decreases if depletion region is generated 10

11 Hysteresis of Depletion Capacitance Coupling Capacitance [ff] Hysteresis Start TSV dc bias voltage [V] Coupling capacitance increases as TSV dc bias decreases Coupling capacitance shows hysteresis, which means that capacitance varies depending on the previous TSV dc bias voltage 11

12 Frequency Domain Measurement Result -10 Noise Coupling Coefficient (db) M Noise coupling increases (1.5dB increase at 10MHz) as temperature increases Noise coupling decreases (3dB decrease at 1GHz) as temperature increases measurement at T=25ºC measurement at T=50ºC measurement at T=75ºC measurement at T=100ºC 100M 1G 10G Frequency (Hz) Measurement shows trend reversion between high frequency and low frequency. At very high frequency, noise coupling becomes similar although temperature varies 12

13 Eye Diagram of 4Gbps at 25 C and 100 C 500 Eye-height : 344 mv At 4Gb/s 25ºC =68.8% V At 4Gb/s 100ºC in (500mV) 500 Eye-height : 354 mv =70.8% V in (500mV) Voltage (mv) Voltage (mv) 0 Pk-pk jitter : 11 ps =4.4% UI 0 Pk-pk jitter : 11 ps =4.4% UI Time (ps) Time (ps) Eye height increases about 2% At 4Gbps, trend is reversed compared with low frequency region Jitter is almost same 13

14 Various Structures of TSV on Interposer ILD Organic Silicon Insulation layer Silicon < Normal TSV > < Through Silicon Line Via (TSLV) > Organic Organic Silicon Silicon < Through Organic Line Via (TOLV) > < Coaxial Organic Line Via (COLV) > 14

15 Measured Eye-diagrams at 30 Gbps (Coaxial TSV) Data rate = 30 Gbps ps ps Voltage (mv) mv Voltage (mv) mv Time (ps) < Eye-diagram of TSV channel > Time (ps) < Eye-diagram of Coaxial TSV channel > Eye-diagram of coaxial TSV channel is better than that of normal TSV channel 15

16 Glass Interposer and TGV < Double-sided Glass Interposer > < Double-sided Silicon Interposer > Glass substrate Silicon substrate Physical parameters TGV/TSV diameter: 10µm TGV/TSV pitch: 40µm, 100µm TSV oxide thickness: 0.5µm 16

17 Equivalent Circuit Model of a Through Glass Via (TGV) Signal Top Ground Top Physical parameters C top,imd G top,imd d TSV = 10 µm p TSV = 100 µm h TSV = 100 µm L TSV C Glass L TSV Extracted RLGC parameters R TSV Signal Bottom G Glass C bot,imd G bot,imd C polymer Ground Bottom R TSV C Glass = 9 ff G Glass = 100 kohm C polymer = 0.1 ff G polymer = 10 kohm C top,imd = 7.5 ff G top.imd = 10 MOhm R TSV = 3 mohm L TSV = 49 ph G polymer 17

18 Insertion Loss : TGV vs. TSV 0 TGV GHz Insertion Loss (db) TSV Through Silicon Via (TSV) Through Glass Via (TGV) Frequency (GHz) Larger loss due to the lossy silicon substrate and thin SiO 2 liner of TSV GHz 18

19 Differential Signal TSV Baseline structure of a differential signal TSV (GSSG type) with Bumps Bump diameter Pitch Bump height Bump Bump Underfill Bump Bump IMD IMD height Ground TSV TSV Height Signal TSV Silicon Substrate Signal TSV TSV diameter Ground TSV Insulator thickness Bump Bump Underfill Bump Bottom oxide thickness Bump 19

20 Measured Coupled Voltage of a TSV Channel depending on Signaling <GSG-type> Clock (1V pp ) 20 < Coupled Noise voltage > Single-ended (GSG-type) vs. Differential (GSSG-type) 15 34mV <GSSG-type> Voltage [mv] mV Clock (0.5V pp ) Clock GSG-type single-ended signaling GSSG-type differential signaling Time [ns] 2 Injected signal : 1GHz clock signal Using pulse-pattern generator (PPG) Digital cscilloscope : TDS8000B Even with the larger insertion loss, GSSG-type differential signal TSV has better noise immunity than GSG-type single-ended signal TSV 20

21 Various Structures of On-interposer Metal Lines Signal Ground ILD G S G ILD S G ILD G S G Interposer Insulation layer Interposer Insulation layer Interposer Insulation layer < Baseline structures Coplanar waveguide (Left), Microstrip (Center), and Strip (Right) lines Signal Ground On-interposer lines for wide I/O On-interposer lines for X-talk reduction < Examples of on-interposer metal lines > 21

22 Fabricated TSV Channel for Modeling and Analysis TSV Interposer Line 150um 20um Probing pads 20um < Top view > Length variation < Top view SEM picture > Oxide layer 0.3um 2000 / 3000 / 4000 um Silicon substrate Oxide layer Under-fill layer Dielectric layer Oxide layer Silicon substrate 50um 8um 10um 3um 0.3um 1um 44um 0.3um 300um Metal line TSV UBM < Side view > < Cross-sectional view SEM picture > 22

23 Verification of Proposed Method by Time-domain Measurement Test Vehicle A (Length = 10Gbps - Input voltage = 1V ps (6.1% UI ) ps (14.9% UI ) Voltage (V) V Voltage (V) V Time (ps) <Eye-diagram by using proposed method > <Eye-diagram by time-domain measurement > Time (ps) Error rate of the estimated eye-diagram using the proposed method - Eye-opening voltage : 5.2% V p-p - Timing jitter : 8.8% UI 23

24 Verification of Proposed Method by Time-domain Measurement Test Vehicle B (Length = 1Gbps - Input voltage = 1V ps (9.0% UI ) ps (14.9% UI ) Voltage (V) V Voltage (V) V Time (ns) Time (ns) <Eye-diagram by using proposed method > <Eye-diagram by time-domain measurement > Error rate of the estimated eye-diagram using the proposed method - Eye-opening voltage : 11.2% V p-p - Timing jitter : 5.9% UI 24

25 Passive Equalizer at Interposer 10um 250um 2um 250um 750um 1250um M1 M2 10um 10um 4500um < Top view > Thicknesses of M1 / M2 = 0.7um / 0.7um Total length of stub = 500um, 1000um, 1500um Test pattern will be fabricated by MPW 104 th M/H 0.35um - Die out :

26 Measured Eye-diagrams at 30 Gbps (Passive Equalizer) Data rate = 30 Gbps Eye-diagram is closed 11.8 ps Voltage (mv) 0 Voltage (mv) 0 47 mv Time (ps) < Eye-diagram without passive EQ. > Time (ps) < Eye-diagram with passive EQ. > By using the passive equalizer, the eye-diagram at the data rate of 30 Gbps is improved 26

27 S 21 : Interposer Channel Loss: CPW S 21 (db) Frequency (GHz) 20 Glass interposer (CPW, M1) Glass interposer (CPW, M2) Silicon interposer (CPW, M1) Silicon interposer (CPW, M2) <Simulated interconnect> - Type : Co-planar waveguide (CPW) - Length : 1 mm - width / space : 10 um / 10 um - Distance from M1 to Glass : 1 um 27

28 Insertion Loss Measurement of Glass Interposer 0.5dB loss at 20GHz, 6mm line Length S 21 (db) Z 0 : 59.6Ω (measurement) Z 0 : 57.5Ω (measurement) Type : CPW Length : 6000um G S G -2 < Signal/ground width/space > 25um/25um/25um um / 600um/20um 170um / 600um/25um Frequency (GHz) < side view > 28

29 Eye-diagram of the Glass Channel (Via + Short line + Via) Glass via < Top view of glass channel > Glass < side view > - Glass via diameter: 60um - Glass line: GSG coplanar waveguide ( Width: 25um / space: 175um / length : 200um ) 1Gbps 5Gbps 10Gbp s Eye-diagram of glass channel (glass via + 200um line + glass via) is measured Because glass channel has a little loss, eye-diagram shape is almost determined by the cable ( 90cm high-frequency cable has -1.3dB insertion loss at 10GHz ) 29

30 Simultaneous Switching Noise (SSN) on Interposer and Problems caused by SSN Through-Silicon Via (TSV) Wide I/O (WIO) LPDDR LPDDR Application Processor (AP) 1Gb/s x512bit Silicon Interposer WIO WIO WIO WIO Package 1. Driver performance degradation by SSN Switching current I/O Drivers (512ea.) 2. SSN coupling Sig(4:6) PWR < lines on interposer > PWR GND Sig(1:3) GND 3. SSN transfer through interposer line < AP > < Wide I/O > 30

31 SEM Photos for TSV Connection Test and Physical Dimension Confirmation (2/2) (1) (2) (3) (4-A) (4-B) We confirmed all TSV connections and physical dimensions of the fabricated sample by SEM photos. 31

32 Modeling Method for Grid-type PDN based on a Segmentation Method Unit cell Unit cell Unit cell Unit cell Unit cell Unit cell Unit cell Unit cell Unit cell : Segmentation Method Once we have unit-cell models, we model the whole grid-type PDN by connecting all unit-cells that form the grid-type PDN based on a segmentation method. 32

33 Verification of TSV-based Stacked Grid-type PDN Model 10 3 PDN Impedance (Ω) C PDN : Proposed model : Measurement : 3D EM simulation (CST MWS) L PDN loop Frequency (GHz) PDN self impedance estimated from the proposed model is well-matched with the simulation result and measurement in the frequency range of 0.1 GHz to 20 GHz. 33

34 SEM Image of TSV-based DCSC IMD (Metal: 10 layer) TSV Capacito r 34

35 Comparison b/w measurement and simulation for PDN impedance (Z11) of the proposed TSV-based DCSC - VNA measurement using agilent E5071B - Freq. Range of VNA: 1M ~ 8GHz 100 PDN Impedance Z11 [ohm] 10 1 L_Decap ESL + TSV + PDN loop L Mode Resonanc e of Chip PDN : Simulation of TSV based DCSC (0.47uF X 4ea) : Measurement of TSV 0.1 based DCSC (0.47uF X 4ea) 1M 10M 100M 1G 10G Frequency [Hz] 35

36 Noise Coupling Paths in Stacked Dies using TSV: Non-ideal RCP P-Substrate 3 rd Chip Inductor TSV TSV TSV TSV N+ P+ P+ N+ N+ P+ N-Well 2 N+ P+ N-Well P-Substrate N+ N+ 3 P+ N+ Metal N-Well to Metal Coupling 2 nd Chip TSV to Active Circuit Coupling Inductor 1 TSV TSV TSV to TSV Coupling N+ P+ P+ N+ N+ P+ N-Well N+ P+ N-Well N+ N+ P+ N+ N-Well P-Substrate 1 st Chip 36

37 Analysis of Noise Coupling based on the 3D TLM Model conta ct C sub silicon substrate R sub C TSV TSV ILD/IM D Distance between contact and TSV : 100 μm Substrate height : 100 μm TSV diameter : 30 μm TSV SiO 2 thickness : 0.5 μm Coupling coefficient [db] A B C TSV SiO2 capacitance dominant Silicon resistance dominant Silicon capacitance dominant M 100M 1G 10G Frequency [GHz] Coupling can be divided into 3-regions In region A, B, and C TSV SiO 2 capacitance, silicon resistance, silicon capacitance is the dominant factor to the coupling 37

38 The Shielding Effects of Active Circuit near TSVs Depletion region -30 t junction d keep Silicon substrate DNW contact G DNW Coupling G Noise coupling coefficient [db] No DNW DNW (small contact) DNW (large contact) M 100M 1G 10G Frequency [Hz] S d DNW S DNW Silicon substrate Active circuit is simply modeled as DNW with keep out area from TSV (d keep ) Shielding effects of DNW is validated by 3D EMsimulation and results are shown 38

39 Two cases assumption Case 1 (NMOS No DNW) p+ n+ n+ p+ p- silicon substrate (σ 10 S/m) Case 2 (with σ 500 S/m DNW) p+ p+ p+ n+ Deep N well n- (σ 500 S/m) p- silicon substrate (σ 10 S/m) 39

40 The effect of distance between TSV and ground tie1-30 Noise coupling [db] M 1G 10G Frequency [Hz] Case 2 : Combination of 10S/m Substrate and 500S/m higher conductivity DNW Case 1 : Only 10S/m substrate 40

41 Shielding TSV (bar, ring, fence) Signal TSVs Shielding GND TSVs <Bar type> <Ring type> <Fence type> Shielding TSVs can be formed in various way It roles as an blocking structure between Signal and Signal, PWR and PWR TSVs, and even analog and digital block 41

42 Conclusions (1) -2.5D architecture will be the most practical semiconductor integration solution for future low power and high-performance mobile platform - TSV and interconnections will be the critical interconnection structures in 2.5D IC. - Significant I/O power reduction and bandwidth increase can be achieved using the 2.5D architecture. - Special TSV structures, transmission line structures, and equalizers are needed to meet low power and high-speed data transmission requirements. 42

43 Conclusions (2) -I/O power noise suppression and hierarchical decoupling schemes are needed to suppress excessive I/O SSN noise - Noise coupling is becoming a crucial concern in 2.5D system, and appropriate shielding methods should be applied 43