Effect of Aging on Power Integrity of Digital Integrated Circuits

Transcription

1 Effect of Aging on Power Integrity of Digital Integrated Circuits A. Boyer, S. Ben Dhia 1 May 14 th, 2013

2 Introduction and context Long time operation Harsh environment condition Device aging Negative Bias Temperature Instability (NBTI) Hot Carrier Injection (HCI) Time Dependent Dielectric Breakdown (TDDB)... Degradation mechanism Drain current (ID) Transconductance (gm) Threshold voltage (Vt) Mobility (μ) Impact of aging on circuit Power Integrity (PI)? Noise margin (Vt) Oscillation frequency (gm,vt) Electromigration Metal 2 Metal 1 Transistor Physical parameter Jitter = f(vt,gm) Power integrity Via TDDB HCI NBTI gate gate Gate oxide N+ N+ P+ P+ N type transistor N-well P-well P type transistor Before aging After aging Circuit performances

3 Objectives of the study Clarify the impact of aging on power integrity (PI) of a digital integrated circuit Determine the origins of power supply voltage bounces variations Model the evolution of power supply voltage bounces after aging 3

4 Case study : 90nm digital core The core 40 MHz clock induces power supply bounce on VddCore The core power integrity is monitored by an integrated voltage sensor (avoid high frequency signal attenuation due to IO pad and package filter) Data in VddCore (1.2 V) On-chip sensor VssCore 100 Inverters Clock rising edge Clock falling edge Clock rising edge Clock Clock Tree 100 Inverters 100 stages 59 mv 4.5 ns 25 ns 100 Inverters Data out 4

5 On-chip sensor for PI characterization On-chip oscilloscope for time domain measurement Sub-sampling conditions / Sequential equivalent-time sampling V Synchronization Sampling command On-chip event T T T Sampled data T Ext. acquisition card - Sensor control Delay control Reconstructed Waveform V T On-chip sensor Synchronization reference Delay cell Sampling command Amplifier Ext. acquisition card - Post-processing & Signal reconstruction S/H cell Clock generator VddCore Digital core Clock rising edge Clock falling edge Clock rising edge Voltage bounce measured on VddCore 59 mv 25 ns 4.5 ns 5

6 Sensor characteristics & performances Non invasive sensor & Probes (4fF input capacitor) 20µm High bandwidth (10 GHz) Dedicated power supply (sensor isolation): 3.3V 20µm acquisition time window = 100 ns Measurement ampl. uncertainty: 10 mv Input range [VSS-0.5V / VDD+ 10%] Time resolution: 15 ps

7 Experimental set-up The circuit aging is accelerated by applying electrical DC stress on the digital core power supply. Two stress voltages : V str1 = 3 V and V str2 = 3.6 V, able to induce significant degradation rapidly. Experiment based on a measure-stress-measure flow: electrical stress is applied and interrupt regularly to characterize the power supply voltage bounce. Full experiment duration Normal conditions Electrical stress Normal conditions Electrical stress Normal conditions Electrical stress Normal conditions Electrical stress Normal conditions T 0 T 1 T 2 T N T0 T1 T2 TN-1 TN 7

8 Aging effect on power integrity Experimental results Reduction of the peak-to-peak amplitude of the power supply bounce during stress. The reduction depends on stress voltage and duration. V str1-3v -20 % V str2-3.6v -30 % 59 mv 47 mv 59 mv 42 mv 8

9 Aging effect on power integrity Origin of the PI evolution The power supply voltage bounce depends on: the power distribution network (on-die capacitance, package inductance ) the dynamic current consumption (linked to circuit activity). Integrated circuit Measurement of impedance between VddCore and VssCore Vdd PDN i(t) consumption V Vss 9 No evolution of circuit PDN after electrical stress

10 Aging effect on power integrity Origin of the PI evolution Measurement of the current returning to the ground through Vss pins at several stress times (V stress = 3.6 V). Comparison of the spectral envelops: Decrease of transient current Reduction of high frequency content Noise floor Origin of PI evolution : spreading of the dynamic current consumption due to internal wear-out mechanisms accelerated by electrical stress. 10

11 Aging effect on power integrity Origin of the current consumption spreading (evolution of the propagation delay through the core ) After stress, the core remain operational & no significant evolution of the quiescent current. Increase of the propagation time of a data through the digital core due to electrical stress. V str2 +31 % V str1 +25 % The increase depends on stress voltage and duration. Propagation delay through one D-latch and 100 inverters after stress 11

12 Modeling of Power integrity evolution Digital core ICEM model (IEC ) Passive RLC based PDN Measurement vs. simulation of VddCore bounce Board decoupling Power distribution network (PDN) Internal Activity (IA) Two basic triangular waveforms for both clock edges current I1 I I0 IA modeling Tr Tf 12 Acceptable correlation of waveforms and peak-to-peak amplitude. Sufficient to take into account the impact of aging. time

13 Modeling of Power integrity evolution Simulation of electrical stress impact on PI Proposed method to take into account the impact of aging on the dynamic current consumption with ICEM: Stress Only IA block is modified. Current pulse waveforms are spread according to an empirical coefficient δ «degradation ratio». Current amplitude and rise/fall times are changed to keep constant the charge transfer associated to each gate switching 1, 0 1 current I I1 I0 current Tr Tf t i stress i initial r stress time tr 1 initial, 0 1 Simulation of the effect of δ on VddCore bounce I I1 Tr Tf After 240 min at 3 V After 120 min at 3.6 V I0 time 13

14 Modeling of Power integrity evolution Simulation of electrical stress impact on PI Comparisons between measurement and simulation of the evolution of the peak-topeak amplitude of the power supply bounce during stress. After V str1 (δ = 0.5) After V str2 (δ = 0.58) The basic ICEM model modified by the empirical degradation ratio is able to reproduce the evolution of the power supply voltage bounce with a reasonable accuracy. 14

15 Conclusion Electrical stresses applied on a digital circuit lead to a reduction of the power supply voltage bounce. This evolution is linked to a change of the transient current linked to the circuit activity. This evolution can be modeled by ICEM approach combined with an empirical coefficient (δ) to take into account the change of transient current Perspectives: use this modeling approach to predict the evolution of conducted and radiated emission of integrated circuits. Automation of modeling process, determining the coefficient δ from stress condition and duration. 15