Hot Topics and Cool Ideas in Scaled CMOS Analog Design

Transcription

1 Engineering Insights 2006 Hot Topics and Cool Ideas in Scaled CMOS Analog Design C. Patrick Yue ECE, UCSB October 27, 2006 Slide 1

2 Our Research Focus High-speed analog and RF circuits Device modeling, CAD and test methodology Interface circuits for emerging applications G1 G2 D1 D2 SS October 27, 2006 Slide 2

3 Outline Hot topics Design & Modeling Methodology Analog / RF / mm-wave standard cells Test Scribe-line RF performance screening circuits Circuit RF front-end, continuous-time equalizer Cool ideas Health monitoring silicon Summary October 27, 2006 Slide 3

4 Recent Evolution for RF SoC Lower power, cost and size RF Front-end Baseband DSP (D. Su, et al. ISSCC 2002.) 0.25-μm CMOS 5-GHz RF transceiver (S. Mehta, et al. ISSCC 2005.) 0.18-μm CMOS RF + baseband DSP But difficult to migrate towards 0.13-μm or 90-nm October 27, 2006 Slide 4

5 Challenges for RF/mm-wave SoC in Scaled CMOS High mask cost ($0.5M $1M) Lack of a streamline RF/mm-wave design flow Negative impact of technology scaling Device Process variations RF/mm-wave model uncertainty Interconnect parasitic variations Circuit Low voltage headroom due to reduced Vdd Develop a parasitic-aware RF/mm-wave modeling/design methodology Strongly depend on layout October 27, 2006 Slide 5

6 Overcome RF/mm-wave Modeling Uncertainty Stand-alone single device model is insufficient Accuracy limited by digital RC extraction RF/mm-wave model layout actual circuit layout Design Flexibility Model Scalability Design Automation Model Accuracy Scalable Analog/RF Sub-Circuit Cells Leverage the insight to optimal RF/mm-wave device layout Exploit the modularity of RF/mm-wave circuits at the sub-circuit level October 27, 2006 Slide 6

7 A Digital-Like Standard Cell Library for RF Design Optimized cell library Diff pair, cross-coupled, cascode Inductors and varactors Interconnects Parameterized cells (P-Cells) SKILL code based Process independent Import design rules from tech files Equivalent circuit models Assemble like Lego blocks Similar to digital standard cell based design flow October 27, 2006 Slide 7

8 Single-Transistor RF Cell Layout Gate Drain Source Bulk Folded multi-finger gate Reduce gate resistance Dummy poly-silicon gate Reduce mismatch Substrate contact ring Substrate resistance Modeling uncertainty Highly regular for better manufacturability Includes dummies in the cell template October 27, 2006 Slide 8

9 Parameterized RF/mm-wave Sub-Circuit Cells G2 G2 G1 G1 D S Cascode devices D BB Merged diffusion node D1 D2 SS G1 G2 BB Differential pair D1 D2 G1 G2 D1&G2 D SS D2&G1 BB Cross-coupled pair D1&G2 D2&G1 S No RC extraction needed within cell boundary Each cell has an equivalent circuit model including RC SS SS October 27, 2006 Slide 9

10 Cell Test Structures in 0.13-μm CMOS ACTIVE & PASSIVE DEVICES INTERCONNECTS 2.5 mm 5.0 mm October 27, 2006 Slide 10

11 Cell-Based RF Design Methodology Specifications System-Level Design Silicon re-spins RF Circuit-Level Synthesis Design Layout RF Sub-Circuit Cell Place Layout-Parasitic & Route Extracted (LPE) Simulation Iterations between schematic and layout Final Verification Tapeout / Fab / Chip Testing October 27, 2006 Slide 11

12 RF Performance Screening Using Cell-Based LC Oscillator Array LC oscillators with different loadings as process variation monitoring vehicles in scribe-line Screening individual parasitic components to identify yield hitters C 60C 0C Oscillation Frequency (GHz) Oscillation Frequencies Over PVT Corners Oscillator Case ID Number October 27, 2006 Slide 12

13 Scribe-Line Oscillator Array Layout and Testing PMOS Variable Resistor Inductor Varactor Zoom in on a single oscillator Buffer : Component : I/O Pad 80 μm Vbias GND Vtune Vout GND 800 μm VDD 5000 μm 80 μm Probe1 During bench testing Probe2 Moving Probe2 Vbias GND Vtune Vout GND Oscillator 1 (800 μm) VDD Vout GND VDD Oscillator 2 (700 μm) October 27, 2006 Slide 13

14 Outline Hot topics Design & Modeling Methodology Analog / RF / mm-wave standard cells Test Scribe-line RF performance screening circuits Circuit RF front-end, continuous-time equalizer Cool ideas Health monitoring silicon Summary October 27, 2006 Slide 14

15 UWB (3 5-GHz) RF Front-End Down-conversion Mixer Wideband LNA Vdd LOdc RFdc Vbias IF+ LO+ GND GND RF+ GND RF- IF- LO- GND Integrate the components between antenna and the transceiver Key to cost-effective, small form-factor multi-mode or MIMO systems Antenna Switch October 27, 2006 Slide 15

16 CMOS T/R Switch with LC-tuned Substrate Bias October 27, 2006 Slide 16

17 UWB LNA with On-Chip Transformer Matching Network V DD R load L load M 3 V BIAS M 2 RF out RF in K C c M 1 C p L ps L ss C d L s Input matching source degeneration inductor wide-band transformer Operate from GHz, draws 6.7 mw from 1.2-V Vdd NF < 4.7 db, S21 > 13.7 db, S11 < 10.4 db, S22 < 13.1 db October 27, 2006 Slide 17

18 A 1-V, 3.3-mW, UWB Mixer (Cell-Based) 1-V Vdd L 1 k 12 L 2 Vdd LOdc RFdc RF+ LO- RF- LO+ LO+ Vbias IF+ LO+ GND Vbias IF+ IF- IF- GND R L R L LO- GND Double balanced folded topology PMOS LO switches Broadband RF choke RF+ GND RF- Active chip area : 200μmX500μm Differential pair, inductor and interconnect sub-circuit cells October 27, 2006 Slide 18

19 High-Speed Adaptive Passive Equalizer input Z 0 Lossy Channel Passive EQ Filter LPF output Limiting Amplifier Control voltage: V C Differential Power Detector Adaptive Control Loop Passive filter for low-power operation Continuous-time (frequency domain) compensation No dependency on recovered clock October 27, 2006 Slide 19

20 Tunable Differential Passive Filter 210 ff 44 Ω 44 Ω S S In+ 540 ph Out+ G G Z 0 In V C M 0 (450 μ / 0.25 μ) 540 ph Out Z 0 S S 44 Ω 44 Ω 210 ff V C Broadband input and output matching PMOS in triode region for adjustable resistance LC components can be low-q (~3 at 3 GHz) Self-resonance frequency > 30 GHz October 27, 2006 Slide 20

21 Channel + Equalizer Frequency Response 10-dB GC Combined response has 8-dB gain difference between dc and 5 GHz Equalizer response (for 10 Gbps) Channel attenuation October 27, 2006 Slide 21

22 20-Gb/s Eye Diagrams Over CAT-5 Cables Equalizer Input Equalizer Output 2 m (10-dB loss at 10GHz) 5 m (20-dB loss at 10GHz) October 27, 2006 Slide 22

23 Outline Hot topics Design & Modeling Methodology Analog / RF / mm-wave standard cells Test Scribe-line RF performance screening circuits Circuit RF front-end, continuous-time equalizer Cool ideas Health monitoring silicon Summary October 27, 2006 Slide 23

24 Interface Circuits for Structural Health Monitoring Devices Active Sensing Patch - Dual sensing and actuation - Surface-mountable - Noninvasive and conformable Power Transmission Inductors - Near-field magnetic coupling Wireless Sensor Interface IC - Actuation and sensing circuits - Multiplexing of senor array - Wireless data transmission - Rectifier for AC to DC power conversion October 27, 2006 Slide 24

25 Implantable Bio-Chip for Communication Prosthesis Open questions for a wireless power delivery interface What is the optimal frequency to use? How much power can be transferred wirelessly? October 27, 2006 Slide 25

26 Power Transfer vs. Frequency -25 P in M on chip P OUT P out /P in (db) No Tissue With Tissue Theoretical Limit (MHz) October 27, 2006 Slide 26

27 Optimized Wireless Power Delivery Inductor at 200 MHz SGS Pad Operate at self-resonance as a LC-tank (Q tank = 11) Match R tank to R load for max power 810 μm Turns 13 Width 9 μm Spacing 5 μm L s R s C p 167 nh 19 Ω 3.7 pf RDL M8 M7 M6 M5 M4 2x3 inductor array Strapped metals No skin effect M4 thru RDL 5-μm metal 2.5-μm oxide October 27, 2006 Slide 27

28 Summary CMOS scaling offers many research opportunity due to paradigm shifts in design, modeling, and test methodologies Higher integration level is needed for multi-mode/mimo RF front-ends Channel equalization become important for >10-Gbps I/Os Increasing need for wireless data/power interface circuits for emerging applications October 27, 2006 Slide 28