# 1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6)

Size: px
Start display at page:

Download "1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6)"

## Transcription

1 CSE 493/593 Test 2 Fall 2011 Solution 1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6) Decreasing of W to make the gate slower, which is the usual approach, results in smaller area and less power consumption. However, if the length of a transistor is increased, the channel resistance as well as the gate capacitance are propportional to the channel length. On the other hand, the delay is proportional to both, the channel resistance and gate capacitance. When we consider the influence of larger L on power consumption, we need to consider three components: dynamic power, short circuit power, and leakage power. With the increasing of L, the larger capacitance results in larger dynamic power consumption. The slower transition speed leads to larger short-circuit power. Increasing the length will result in lower subthreshold leakage current but higher gate leakage current. Since gate leakage current is larger than subthreshold leakage current in current technologies, so the total leakage power is increased. So increasing L results in larger power consumption. Therefore, increasing L is the worst case approach to transistor sizing. b. Compare the static, dynamic and sub-threshold leakage power of a static CMOS AND gate and a dynamic CMOS AND gate. Explain your answer. (6) The dynamic power of a dynamic CMOS AND is larger due to the higher switching probability and clock. The static and sub-threshold leakage power of dynamic gate is usually smaller, since it has fewer transistors. c. What is stack effect? How does stacking help reduce the power consumption? (6) When there are two or more stacked off-transistors (as shown in the following figure), the subthreshold leakage is reduced. This is because, turning OFF more than one transistor in a stack of transistors forces the intermediate node voltage to go to a value higher than zero. This causes a negative Vgs, negative Vbs (more body effect) and Vds reduction (less DIBL) in the top transistor, thereby reducing the subthreshold leakage current flowing through the stack considerably, which is known as the stack effect. d. How does the threshold voltage value affect the circuit performance in terms of (i) speed and (ii) power? (6) The higher threshold voltage value results in lower speed and lower power consumption. 1

2 e. What is body biasing? How can you use body biasing to reduce power consumption? Principle: Through body biasing, the threshold voltage of transistor can be varied. With reverse body bias, the leakage current can be decreased effectively. Similar to the Multiple VT, the speed will be affected with reverse body bias. Usage: Reverse biasing the transistor on the non-crucial path. 2. For the schematic shown below, identify the function F implemented in the circuit, and draw the transistor-level circuit diagram for F using the logic styles (a) compound static CMOS (b) Domino CMOS: (10) B Sbar A S F a) Compound static CMOS logic b) Domino CMOS Note that, we can also use two stage to implement this circuit. 2

3 3. A three-input gate is shown in Fig.1. (15) a. Size all transistors such that the worst-case delay is equal to that of an inverter with PMOS size=2 and NMOS size=1. b. Assuming all input combinations are equally likely, what is the transition activity (probability) of the output F? Based on the truth table, we can get the transition probability of the gate: P(F:0 1) = P(F=0)P(F=1) = 3/8 5/8 = 15/ We can also using the following approach: P(F=0)=P(A=1){1 P(B=0)P(C=0)}=1/2*(1 1/4)=3/8 P(F=1)=5/8. So P(F=0)*P(F=1)=15/64 4. You may assume that all input combinations are equally likely. Let Cin=0.8fF, and CL=12fF. (15) a. Calculate the activity factor for the output (F). b. Calculate the dynamic power consumption if the inputs are switching at rate of 200MHz at a supply voltage of 2.5V. Fig.2 a. Calculate the activity factor for the output (F). The inputs to the nand gate are (A nor B) and (A xnor B). This results in F being low only when A=B=0, or P (F=0) = 1/4, and P (F=1) = 1 P (F=0) = 3/4. The transition probability is then P= 3/16 (the transition probabilities for the nor gate and xnor gate are 3/16 and 1/4, respectively). 3

4 b. Calculate the dynamic power consumption if the inputs are switching at rate of 200MHz at a supply voltage of 2.5V. Since we are assuming that all input combinations are equally likely, for all time, the transition probabilities for the gates will be equal to the transition activities (defined as the average over a long period). If we call the nor output node1, and xnor output node 2, the dynamic power will be: P dyn = 1 fc 1 Vdd fc 2 Vdd 2 F fc F Vdd 2 The average switched capacitances ( C) are C 1 = 3/ fF = 0.45fF C 2 = 1/ fF = 1.2fF F C F = 3/16 12fF = 2.25fF Therefore, P dyn = fvdd 2 ( 1 C C 2 + F C F ) = 200MHz (2.5 V) 2 3.9fF 4.9 W Note that, all of these three gates consume power consumption. Since they have different switching probabilities and loading capacitors, so we have to calculate these parts separately and then get the total power. 5. Dynamic circuits: Consider the domino stage shown below. Assume that each of the PDN in the figure has a single NMOS transistor. Assume the precharge time, evaluate time, propagation delay of these static inverters are all equal to 10ns each. Also assume zero rise and fall times for all signals. Complete the timing diagram for signals Out1, Out2, Out3 and Out4 if the IN signal goes high at the rising edge of the clock. Assume clock period is 100ns. (20) Fig.3 4

5 Note that, the difference of this question from our hw question is that different stages are using different clocks and therefore the output waveforms are shifted. 6. Explain how each item below can achieve low power. Describe how a designer can use these techniques in low power design with example. (10) a) Multiple Vdd b) Multiple VT a) Multiple Vdd: Principle: The power consumption will increase with the increasing Vdd: the dynamic power consumption will depend on the square of vdd and the leakage power will depend on V dd. But the speed will be enhanced with increasing Vdd due to stronger driving ability. Usage: In the non-crucial path, low Vdd will be applied to decrease power consumption; in crucial path, high vdd is applied to keep the performance. b) Multiple VT Principle: High VT transistor generates less leakage current, thereby generating less power consumption, but its speed is decreased. On the other hand, low VT transistor generates more leakage power consumption, but its speed characteristics is superior. Usage: High VT transistors are employed to achieve low power design in the non-crucial path; low VT transistors are employed to keep the performance in the crucial path. 5

### CHAPTER 3 PERFORMANCE OF A TWO INPUT NAND GATE USING SUBTHRESHOLD LEAKAGE CONTROL TECHNIQUES

CHAPTER 3 PERFORMANCE OF A TWO INPUT NAND GATE USING SUBTHRESHOLD LEAKAGE CONTROL TECHNIQUES 41 In this chapter, performance characteristics of a two input NAND gate using existing subthreshold leakage

### CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4

CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 1 2 3 4 5 6 7 8 9 10 Sum 30 10 25 10 30 40 10 15 15 15 200 1. (30 points) Misc, Short questions (a) (2 points) Postponing the introduction of signals

### Power and Energy. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

Power and Energy Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu The Chip is HOT Power consumption increases

### Combinational Logic Gates in CMOS

Combinational Logic Gates in CMOS References: dapted from: Digital Integrated Circuits: Design Perspective, J. Rabaey UC Principles of CMOS VLSI Design: Systems Perspective, 2nd Ed., N. H. E. Weste and

### EEC 118 Lecture #12: Dynamic Logic

EEC 118 Lecture #12: Dynamic Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Outline Today: Alternative MOS Logic Styles Dynamic MOS Logic Circuits: Rabaey

### Topic 6. CMOS Static & Dynamic Logic Gates. Static CMOS Circuit. NMOS Transistors in Series/Parallel Connection

NMOS Transistors in Series/Parallel Connection Topic 6 CMOS Static & Dynamic Logic Gates Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Transistors can be thought

### Module 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits

Module 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits Objectives In this lecture you will learn the following Ratioed Logic Pass Transistor Logic Dynamic Logic Circuits

### EE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits

EE 330 Lecture 43 Digital Circuits Other Logic Styles Dynamic Logic Circuits Review from Last Time Elmore Delay Calculations W M 5 V OUT x 20C RE V IN 0 L R L 1 L R R 6 W 1 C C 3 D R t 1 R R t 2 R R t

### Depletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET

Ch. 13 MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor : I D D-mode E-mode V g The gate oxide is made of dielectric SiO 2 with e = 3.9 Depletion-mode operation ( 공핍형 ): Using an input gate voltage

### EE 330 Lecture 44. Digital Circuits. Other Logic Styles Dynamic Logic Circuits

EE 330 Lecture 44 Digital Circuits Other Logic Styles Dynamic Logic Circuits Course Evaluation Reminder - ll Electronic http://bit.ly/isustudentevals Review from Last Time Power Dissipation in Logic Circuits

### Comparison of Power Dissipation in inverter using SVL Techniques

Comparison of Power Dissipation in inverter using SVL Techniques K. Kalai Selvi Assistant Professor, Dept. of Electronics & Communication Engineering, Government College of Engineering, Tirunelveli, India

### ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits

Faculty of Engineering ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits CMOS Technology Complementary MOS, or CMOS, needs both PMOS and NMOS FET devices for their logic gates to be realized

### Leakage Current Analysis

Current Analysis Hao Chen, Latriese Jackson, and Benjamin Choo ECE632 Fall 27 University of Virginia , , @virginia.edu Abstract Several common leakage current reduction methods such

### UNIT-1 Fundamentals of Low Power VLSI Design

UNIT-1 Fundamentals of Low Power VLSI Design Need for Low Power Circuit Design: The increasing prominence of portable systems and the need to limit power consumption (and hence, heat dissipation) in very-high

### Dynamic Logic. Domino logic P-E logic NORA logic 2-phase logic Multiple O/P domino logic Cascode logic 11/28/2012 1

Dynamic Logic Dynamic Circuits will be introduced and their performance in terms of power, area, delay, energy and AT 2 will be reviewed. We will review the following logic families: Domino logic P-E logic

### ! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology. " Gate choice, logical optimization. " Fanin, fanout, Serial vs.

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Design Space Exploration Lec 18: March 28, 2017 Design Space Exploration, Synchronous MOS Logic, Timing Hazards 3 Design Problem Problem Solvable!

### Electronics Basic CMOS digital circuits

Electronics Basic CMOS digital circuits Prof. Márta Rencz, Gábor Takács, Dr. György Bognár, Dr. Péter G. Szabó BME DED October 21, 2014 1 / 30 Introduction The topics covered today: The inverter: the simplest

### EE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits

EE 330 Lecture 43 Digital Circuits Other Logic Styles Dynamic Logic Circuits Review from Last Time Elmore Delay Calculations W M 5 V OUT x 20C RE V IN 0 L R L 1 L R RW 6 W 1 C C 3 D R t 1 R R t 2 R R t

### Chapter 6 Combinational CMOS Circuit and Logic Design. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 6 Combinational CMOS Circuit and Logic Design Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Advanced Reliable Systems (ARES) Lab. Jin-Fu Li,

### Low Power Realization of Subthreshold Digital Logic Circuits using Body Bias Technique

Indian Journal of Science and Technology, Vol 9(5), DOI: 1017485/ijst/2016/v9i5/87178, Februaru 2016 ISSN (Print) : 0974-6846 ISSN (Online) : 0974-5645 Low Power Realization of Subthreshold Digital Logic

### Low Power, Area Efficient FinFET Circuit Design

Low Power, Area Efficient FinFET Circuit Design Michael C. Wang, Princeton University Abstract FinFET, which is a double-gate field effect transistor (DGFET), is more versatile than traditional single-gate

### ! Review: Sequential MOS Logic. " SR Latch. " D-Latch. ! Timing Hazards. ! Dynamic Logic. " Domino Logic. ! Charge Sharing Setup.

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 29, 206 Timing Hazards and Dynamic Logic Lecture Outline! Review: Sequential MOS Logic " SR " D-! Timing Hazards! Dynamic Logic "

### UNIT-II LOW POWER VLSI DESIGN APPROACHES

UNIT-II LOW POWER VLSI DESIGN APPROACHES Low power Design through Voltage Scaling: The switching power dissipation in CMOS digital integrated circuits is a strong function of the power supply voltage.

### 1. What is the major problem associated with cascading pass transistor logic gates?

EE 434 Exam 2 Fall 2003 Name Instructions. Students may bring 4 pages of notes to this exam. There are 9 questions. The first 8 are worth 2 points each and question 9 is worth 4 points. There are 6 problems.

### Chapter 2 Combinational Circuits

Chapter 2 Combinational Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 23, 26 Why CMOS? Most logic design today is done on CMOS circuits

### Power-Area trade-off for Different CMOS Design Technologies

Power-Area trade-off for Different CMOS Design Technologies Priyadarshini.V Department of ECE Sri Vishnu Engineering College for Women, Bhimavaram dpriya69@gmail.com Prof.G.R.L.V.N.Srinivasa Raju Head

### ECE 471/571 The CMOS Inverter Lecture-6. Gurjeet Singh

ECE 471/571 The CMOS Inverter Lecture-6 Gurjeet Singh NMOS-to-PMOS ratio,pmos are made β times larger than NMOS Sizing Inverters for Performance Conclusions: Intrinsic delay tp0 is independent of sizing

### EE 330 Lecture 42. Other Logic Styles Digital Building Blocks

EE 330 Lecture 42 Other Logic Styles Digital Building Blocks Logic Styles Static CMOS Complex Logic Gates Pass Transistor Logic (PTL) Pseudo NMOS Dynamic Logic Domino Zipper Static CMOS Widely used Attractive

### Improved Two Phase Clocked Adiabatic Static CMOS Logic Circuit

Available online www.ejaet.com European Journal of Advances in Engineering and Technology, 2017, 4 (5): 319-325 Research Article ISSN: 2394-658X Improved Two Phase Clocked Adiabatic Static CMOS Logic Circuit

### EE434 ASIC & Digital Systems

EE434 ASIC & Digital Systems Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Spring 2015 Dae Hyun Kim daehyun@eecs.wsu.edu 1 Lecture 4 More on CMOS Gates Ref: Textbook chapter

### EE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad

A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 23 p. 1/16 EE 42/100 Lecture 23: CMOS Transistors and Logic Gates ELECTRONICS Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad University

### 4: Transistors Non idealities

4: Transistors Non idealities Inversion Major cause of non-idealities/complexities: Who controls channel (and how)? Large Body(Substrate) Source Voltage V G V SB - - - - - - - - n+ n+ - - - - - - - - -

### Jan Rabaey, «Low Powere Design Essentials," Springer tml

Jan Rabaey, «e Design Essentials," Springer 2009 http://web.me.com/janrabaey/lowpoweressentials/home.h tml Dimitrios Soudris, Christian Piguet, and Costas Goutis, Designing CMOS Circuits for Low POwer,

### Announcements. Advanced Digital Integrated Circuits. Quiz #3 today Homework #4 posted This lecture until 4pm

EE241 - Spring 2011 dvanced Digital Integrated Circuits Lecture 20: High-Performance Logic Styles nnouncements Quiz #3 today Homework #4 posted This lecture until 4pm Reading: Chapter 8 in the owhill text

### UNIT-III GATE LEVEL DESIGN

UNIT-III GATE LEVEL DESIGN LOGIC GATES AND OTHER COMPLEX GATES: Invert(nmos, cmos, Bicmos) NAND Gate(nmos, cmos, Bicmos) NOR Gate(nmos, cmos, Bicmos) The module (integrated circuit) is implemented in terms

### Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for Sub-130nm CMOS Technologies

Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for Sub-30nm CMOS Technologies Bhaskar Chatterjee, Manoj Sachdev Ram Krishnamurthy * Department of Electrical and Computer

### Sleepy Keeper Approach for Power Performance Tuning in VLSI Design

International Journal of Electronics and Communication Engineering. ISSN 0974-2166 Volume 6, Number 1 (2013), pp. 17-28 International Research Publication House http://www.irphouse.com Sleepy Keeper Approach

### 3: MOS Transistors. Non idealities

3: MOS Transistors Non idealities Inversion Major cause of non-idealities/complexities: Who controls channel (and how)? Large Body(Substrate) Source Voltage V G V SB - - - - - - - - n+ n+ - - - - - - -

### ECE 3110: Engineering Electronics II Fall Final Exam. Dec. 16, 8:00-10:00am. Name: (78 points total)

Final Exam Dec. 16, 8:00-10:00am Name: (78 points total) Problem 1: Consider the emitter follower in Fig. 7, which is being used as an output stage. For Q 1, assume β = and initally assume that V BE =

### CHAPTER 3 NEW SLEEPY- PASS GATE

56 CHAPTER 3 NEW SLEEPY- PASS GATE 3.1 INTRODUCTION A circuit level design technique is presented in this chapter to reduce the overall leakage power in conventional CMOS cells. The new leakage po leepy-

### Electronic Circuits EE359A

Electronic Circuits EE359A Bruce McNair B206 bmcnair@stevens.edu 201-216-5549 1 Memory and Advanced Digital Circuits - 2 Chapter 11 2 Figure 11.1 (a) Basic latch. (b) The latch with the feedback loop opened.

### Lecture 13 CMOS Power Dissipation

EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 13 CMOS Power Dissipation Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken,

### CHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS

70 CHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS A novel approach of full adder and multipliers circuits using Complementary Pass Transistor

### Contents 1 Introduction 2 MOS Fabrication Technology

Contents 1 Introduction... 1 1.1 Introduction... 1 1.2 Historical Background [1]... 2 1.3 Why Low Power? [2]... 7 1.4 Sources of Power Dissipations [3]... 9 1.4.1 Dynamic Power... 10 1.4.2 Static Power...

### 3.CMOS Inverter-homework

3.CMOS Inverter-homework 1. for a CMOS inverter, when the pmos and nmos are long-channel devices,or when the supply voltage is low, velocity does not occur, under these circumstances,vm(vin=vout)=? 2.

### Design of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer

Design of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer Mr. Y.Satish Kumar M.tech Student, Siddhartha Institute of Technology & Sciences. Mr. G.Srinivas, M.Tech Associate

### ! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential

### CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC

138 CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC 6.1 INTRODUCTION The Clock generator is a circuit that produces the timing or the clock signal for the operation in sequential circuits. The circuit

### A Low Power Array Multiplier Design using Modified Gate Diffusion Input (GDI)

A Low Power Array Multiplier Design using Modified Gate Diffusion Input (GDI) Mahendra Kumar Lariya 1, D. K. Mishra 2 1 M.Tech, Electronics and instrumentation Engineering, Shri G. S. Institute of Technology

### SCALING power supply has become popular in lowpower

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 59, NO. 1, JANUARY 2012 55 Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique

### Design of Robust and power Efficient 8-Bit Ripple Carry Adder using Different Logic Styles

Design of Robust and power Efficient 8-Bit Ripple Carry Adder using Different Logic Styles Mangayarkkarasi M 1, Joseph Gladwin S 2 1 Assistant Professor, 2 Associate Professor 12 Department of ECE 1 Sri

### ELEC Digital Logic Circuits Fall 2015 Delay and Power

ELEC - Digital Logic Circuits Fall 5 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal

### Enhancement of Design Quality for an 8-bit ALU

ABHIYANTRIKI An International Journal of Engineering & Technology (A Peer Reviewed & Indexed Journal) Vol. 3, No. 5 (May, 2016) http://www.aijet.in/ eissn: 2394-627X Enhancement of Design Quality for an

### Analysis & Implementation of Low Power MTCMOS 10T Full Adder Circuit in Nano Scale

Analysis & Implementation of Low Power MTCMOS 10T Full Adder Circuit in Nano Scale Brajmohan Baghel,Shipra Mishra, M.Tech, Embedded &VLSI Design NITM Gwalior M.P. India 474001 Asst. Prof. EC Dept., NITM

### Design Analysis of 1-bit Comparator using 45nm Technology

Design Analysis of 1-bit Comparator using 45nm Technology Pardeep Sharma 1, Rajesh Mehra 2 1,2 Department of Electronics and Communication Engineering, National Institute for Technical Teachers Training

Technology and Innovation for Sustainable Development Conference (TISD2006) Faculty of Engineering, Khon Kaen University, Thailand 25-26 January 2006 IMPLEMENTATION OF ADIABATIC DYNAMIC LOGIC IN BIT FULL

### Basic digital logic functions and gates

Basic digital logic functions and gates Digital logic functions and gates are the main blocks behind digital logic design. s and 1s combine to produce values that are generated by basic gates such as NOT,

### ENEE307 Lab 7 MOS Transistors 2: Small Signal Amplifiers and Digital Circuits

ENEE307 Lab 7 MOS Transistors 2: Small Signal Amplifiers and Digital Circuits In this lab, we will be looking at ac signals with MOSFET circuits and digital electronics. The experiments will be performed

### Design & Analysis of Low Power Full Adder

1174 Design & Analysis of Low Power Full Adder Sana Fazal 1, Mohd Ahmer 2 1 Electronics & communication Engineering Integral University, Lucknow 2 Electronics & communication Engineering Integral University,

### Lecture Integrated circuits era

Lecture 1 1.1 Integrated circuits era Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell laboratories. In 1961, first IC was introduced. Levels of Integration:-

### ADIABATIC LOGIC FOR LOW POWER DIGITAL DESIGN

ADIABATIC LOGIC FOR LOW POWER DIGITAL DESIGN Mr. Sunil Jadhav 1, Prof. Sachin Borse 2 1 Student (M.E. Digital Signal Processing), Late G. N. Sapkal College of Engineering, Nashik,jsunile@gmail.com 2 Professor

### ECE520 VLSI Design. Lecture 5: Basic CMOS Inverter. Payman Zarkesh-Ha

ECE520 VLSI Design Lecture 5: Basic CMOS Inverter Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture

### High-Performance of Domino Logic Circuit for Wide Fan-In Gates Using Mentor Graphics Tools

IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 6, Ver. II (Nov -Dec. 2015), PP 06-15 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org High-Performance of Domino Logic

### Design of High Performance Arithmetic and Logic Circuits in DSM Technology

Design of High Performance Arithmetic and Logic Circuits in DSM Technology Salendra.Govindarajulu 1, Dr.T.Jayachandra Prasad 2, N.Ramanjaneyulu 3 1 Associate Professor, ECE, RGMCET, Nandyal, JNTU, A.P.Email:

### DESIGN AND ANALYSIS OF NAND GATE USING BODY BIASING TECHNIQUE

DESIGN AND ANALYSIS OF NAND GATE USING BODY BIASING TECHNIQUE Mr.Om Prakash 1, Dr.B.S.Rai 2, Dr.Arun Kumar 3 1 Assistant Professor, Deptt.Electronics & Comm. IIMT IETMeerut, U.P. (India). 2 HOD & Professor

### Digital Electronics Part II - Circuits

Digital Electronics Part II - Circuits Dr. I. J. Wassell Gates from Transistors 1 Introduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits

### EE E6930 Advanced Digital Integrated Circuits. Spring, 2002 Lecture 7. Clocked and self-resetting logic I

EE E6930 Advanced Digital Integrated Circuits Spring, 2002 Lecture 7. Clocked and self-resetting logic I References CBF, Chapter 8 DP, Section 4.3.3.1-4.3.3.4 Bernstein, High-speed CMOS design styles,

### Design and Implementation of Digital CMOS VLSI Circuits Using Dual Sub-Threshold Supply Voltages

RESEARCH ARTICLE OPEN ACCESS Design and Implementation of Digital CMOS VLSI Circuits Using Dual Sub-Threshold Supply Voltages A. Suvir Vikram *, Mrs. K. Srilakshmi ** And Mrs. Y. Syamala *** * M.Tech,

### High Performance and Low power VLSI CMOS Circuit Designs using ONOFIC Approach

RESEARCH ARTICLE OPEN ACCESS High Performance and Low power VLSI CMOS Circuit Designs using ONOFIC Approach M.Sahithi Priyanka 1, G.Manikanta 2, K.Bhaskar 3, A.Ganesh 4, V.Swetha 5 1. Student of Lendi

### Lecture 4. The CMOS Inverter. DC Transfer Curve: Load line. DC Operation: Voltage Transfer Characteristic. Noise in Digital Integrated Circuits

Noise in Digital Integrated Circuits Lecture 4 The CMOS Inverter i(t) v(t) V DD Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail:

### In this experiment you will study the characteristics of a CMOS NAND gate.

Introduction Be sure to print a copy of Experiment #12 and bring it with you to lab. There will not be any experiment copies available in the lab. Also bring graph paper (cm cm is best). Purpose In this

### IJMIE Volume 2, Issue 3 ISSN:

IJMIE Volume 2, Issue 3 ISSN: 2249-0558 VLSI DESIGN OF LOW POWER HIGH SPEED DOMINO LOGIC Ms. Rakhi R. Agrawal* Dr. S. A. Ladhake** Abstract: Simple to implement, low cost designs in CMOS Domino logic are

### Low Power High Performance 10T Full Adder for Low Voltage CMOS Technology Using Dual Threshold Voltage

Low Power High Performance 10T Full Adder for Low Voltage CMOS Technology Using Dual Threshold Voltage Surbhi Kushwah 1, Shipra Mishra 2 1 M.Tech. VLSI Design, NITM College Gwalior M.P. India 474001 2

### Near-threshold Computing of Single-rail MOS Current Mode Logic Circuits

Research Journal of Applied Sciences, Engineering and Technology 5(10): 2991-2996, 2013 ISSN: 2040-7459; e-issn: 2040-7467 Maxwell Scientific Organization, 2013 Submitted: September 16, 2012 Accepted:

### Novel Buffer Design for Low Power and Less Delay in 45nm and 90nm Technology

Novel Buffer Design for Low Power and Less Delay in 45nm and 90nm Technology 1 Mahesha NB #1 #1 Lecturer Department of Electronics & Communication Engineering, Rai Technology University nbmahesh512@gmail.com

### Static NP Domino Carry gates for Ultra Low Voltage and High Speed Full Adders

INTERNTIONL JOURNL OF CIRCUITS, SYSTEMS ND SIGNL PROCESSING Static NP Domino Carry gates for Ultra Low Voltage and High Speed Full dders Sohail Musa Mahmood and Yngvar erg bstract In this paper we present

### Digital circuits. Bởi: Sy Hien Dinh

Digital circuits Bởi: Sy Hien Dinh This module presents the basic concepts of MOSFET digital logic circuits. We will examine NMOS logic circuits, which contain only n-channel transistors, and complementary

### STATIC POWER OPTIMIZATION USING DUAL SUB-THRESHOLD SUPPLY VOLTAGES IN DIGITAL CMOS VLSI CIRCUITS

STATIC POWER OPTIMIZATION USING DUAL SUB-THRESHOLD SUPPLY VOLTAGES IN DIGITAL CMOS VLSI CIRCUITS Mrs. K. Srilakshmi 1, Mrs. Y. Syamala 2 and A. Suvir Vikram 3 1 Department of Electronics and Communication

### Static Random Access Memory - SRAM Dr. Lynn Fuller Webpage:

ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Static Random Access Memory - SRAM Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Email:

### Microelectronics Circuit Analysis and Design. MOS Capacitor Under Bias: Electric Field and Charge. Basic Structure of MOS Capacitor 9/25/2013

Microelectronics Circuit Analysis and Design Donald A. Neamen Chapter 3 The Field Effect Transistor In this chapter, we will: Study and understand the operation and characteristics of the various types

### EEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic Families

EEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic Families Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Homework 5 this week Lab

### Leakage Power Reduction for Logic Circuits Using Variable Body Biasing Technique

Leakage Power Reduction for Logic Circuits Using Variable Body Biasing Technique Anjana R 1 and Ajay K Somkuwar 2 Assistant Professor, Department of Electronics and Communication, Dr. K.N. Modi University,

### A Tunable Body Biasing Scheme for Ultra-Low Power and High Speed CMOS Designs

1 A Tunable Body Biasing Scheme for Ultra-Low Power and High Speed CMOS Designs Jabulani Nyathi, Member, IEEE Brent Bero, Student, IEEE and Ryan McKinlay Student, IEEE Abstract Interest in VLSI subthreshold

### Investigation on Performance of high speed CMOS Full adder Circuits

ISSN (O): 2349-7084 International Journal of Computer Engineering In Research Trends Available online at: www.ijcert.org Investigation on Performance of high speed CMOS Full adder Circuits 1 KATTUPALLI

### Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits

Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits P. S. Aswale M. E. VLSI & Embedded Systems Department of E & TC Engineering SITRC, Nashik,

### Noise Tolerance Dynamic CMOS Logic Design with Current Mirror Circuit

International Journal of Electrical Engineering. ISSN 0974-2158 Volume 7, Number 1 (2014), pp. 77-81 International Research Publication House http://www.irphouse.com Noise Tolerance Dynamic CMOS Logic

### Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders

Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders B. Madhuri Dr.R. Prabhakar, M.Tech, Ph.D. bmadhusingh16@gmail.com rpr612@gmail.com M.Tech (VLSI&Embedded System Design) Vice

### EE241 - Spring 2002 Advanced Digital Integrated Circuits

EE241 - Spring 2002 dvanced Digital Integrated Circuits Lecture 7 MOS Logic Styles nnouncements Homework #1 due 2/19 1 Reading Chapter 7 in the text by K. ernstein ackground material from Rabaey References»

### EEC 216 Lecture #10: Ultra Low Voltage and Subthreshold Circuit Design. Rajeevan Amirtharajah University of California, Davis

EEC 216 Lecture #1: Ultra Low Voltage and Subthreshold Circuit Design Rajeevan Amirtharajah University of California, Davis Opportunities for Ultra Low Voltage Battery Operated and Mobile Systems Wireless

### Performance Analysis of Novel Domino XNOR Gate in Sub 45nm CMOS Technology

Performance Analysis of Novel Domino Gate in Sub 45nm CMOS Technology AMIT KUMAR PANDEY, RAM AWADH MISHRA, RAJENDRA KUMAR NAGARIA Department of Electronics and Communication Engineering MNNIT Allahabad-211004

### Session 10: Solid State Physics MOSFET

Session 10: Solid State Physics MOSFET 1 Outline A B C D E F G H I J 2 MOSCap MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor: Al (metal) SiO2 (oxide) High k ~0.1 ~5 A SiO2 A n+ n+ p-type Si (bulk)

### Domino Static Gates Final Design Report

Domino Static Gates Final Design Report Krishna Santhanam bstract Static circuit gates are the standard circuit devices used to build the major parts of digital circuits. Dynamic gates, such as domino

### PERFORMANCE ANALYSIS ON VARIOUS LOW POWER CMOS DIGITAL DESIGN TECHNIQUES

PERFORMANCE ANALYSIS ON VARIOUS LOW POWER CMOS DIGITAL DESIGN TECHNIQUES R. C Ismail, S. A. Z Murad and M. N. M Isa School of Microelectronic Engineering, Universiti Malaysia Perlis, Arau, Perlis, Malaysia

### Design of 32-bit ALU using Low Power Energy Efficient Full Adder Circuits

Design of 32-bit ALU using Low Power Energy Efficient Full Adder Circuits Priyadarshini.V Department of ECE Gudlavalleru Engieering College,Gudlavalleru darshiniv708@gmail.com Ramya.P Department of ECE

### VLSI Designed Low Power Based DPDT Switch

International Journal of Electronics and Communication Engineering. ISSN 0974-2166 Volume 8, Number 1 (2015), pp. 81-86 International Research Publication House http://www.irphouse.com VLSI Designed Low

### Pramoda N V Department of Electronics and Communication Engineering, MCE Hassan Karnataka India

Advanced Low Power CMOS Design to Reduce Power Consumption in CMOS Circuit for VLSI Design Pramoda N V Department of Electronics and Communication Engineering, MCE Hassan Karnataka India Abstract: Low

### HW#3 Solution. Dr. Parker. Spring 2014

HW#3 olution r. Parker pring 2014 Assume for the problems below that V dd = 1.8 V, V tp0 is -.7 V. and V tn0 is.7 V. V tpbodyeffect is -.9 V. and V tnbodyeffect is.9 V. Assume ß n (k n )= 219.4 W/L µ A(microamps)/V

### MOS Logic and Gate Circuits. Wired OR

MOS Logic and Gate Circuits A A A B A AB Y Wired OR Contents Introduction NMOS Logic Resistive Load Saturated Enhancement Load Linear Enhancement Load Depletion Load Some Gates Transient in NMOS Circuit