1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6)

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1 CSE 493/593 Test 2 Fall 2011 Solution 1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6) Decreasing of W to make the gate slower, which is the usual approach, results in smaller area and less power consumption. However, if the length of a transistor is increased, the channel resistance as well as the gate capacitance are propportional to the channel length. On the other hand, the delay is proportional to both, the channel resistance and gate capacitance. When we consider the influence of larger L on power consumption, we need to consider three components: dynamic power, short circuit power, and leakage power. With the increasing of L, the larger capacitance results in larger dynamic power consumption. The slower transition speed leads to larger short-circuit power. Increasing the length will result in lower subthreshold leakage current but higher gate leakage current. Since gate leakage current is larger than subthreshold leakage current in current technologies, so the total leakage power is increased. So increasing L results in larger power consumption. Therefore, increasing L is the worst case approach to transistor sizing. b. Compare the static, dynamic and sub-threshold leakage power of a static CMOS AND gate and a dynamic CMOS AND gate. Explain your answer. (6) The dynamic power of a dynamic CMOS AND is larger due to the higher switching probability and clock. The static and sub-threshold leakage power of dynamic gate is usually smaller, since it has fewer transistors. c. What is stack effect? How does stacking help reduce the power consumption? (6) When there are two or more stacked off-transistors (as shown in the following figure), the subthreshold leakage is reduced. This is because, turning OFF more than one transistor in a stack of transistors forces the intermediate node voltage to go to a value higher than zero. This causes a negative Vgs, negative Vbs (more body effect) and Vds reduction (less DIBL) in the top transistor, thereby reducing the subthreshold leakage current flowing through the stack considerably, which is known as the stack effect. d. How does the threshold voltage value affect the circuit performance in terms of (i) speed and (ii) power? (6) The higher threshold voltage value results in lower speed and lower power consumption. 1

2 e. What is body biasing? How can you use body biasing to reduce power consumption? Principle: Through body biasing, the threshold voltage of transistor can be varied. With reverse body bias, the leakage current can be decreased effectively. Similar to the Multiple VT, the speed will be affected with reverse body bias. Usage: Reverse biasing the transistor on the non-crucial path. 2. For the schematic shown below, identify the function F implemented in the circuit, and draw the transistor-level circuit diagram for F using the logic styles (a) compound static CMOS (b) Domino CMOS: (10) B Sbar A S F a) Compound static CMOS logic b) Domino CMOS Note that, we can also use two stage to implement this circuit. 2

3 3. A three-input gate is shown in Fig.1. (15) a. Size all transistors such that the worst-case delay is equal to that of an inverter with PMOS size=2 and NMOS size=1. b. Assuming all input combinations are equally likely, what is the transition activity (probability) of the output F? Based on the truth table, we can get the transition probability of the gate: P(F:0 1) = P(F=0)P(F=1) = 3/8 5/8 = 15/ We can also using the following approach: P(F=0)=P(A=1){1 P(B=0)P(C=0)}=1/2*(1 1/4)=3/8 P(F=1)=5/8. So P(F=0)*P(F=1)=15/64 4. You may assume that all input combinations are equally likely. Let Cin=0.8fF, and CL=12fF. (15) a. Calculate the activity factor for the output (F). b. Calculate the dynamic power consumption if the inputs are switching at rate of 200MHz at a supply voltage of 2.5V. Fig.2 a. Calculate the activity factor for the output (F). The inputs to the nand gate are (A nor B) and (A xnor B). This results in F being low only when A=B=0, or P (F=0) = 1/4, and P (F=1) = 1 P (F=0) = 3/4. The transition probability is then P= 3/16 (the transition probabilities for the nor gate and xnor gate are 3/16 and 1/4, respectively). 3

4 b. Calculate the dynamic power consumption if the inputs are switching at rate of 200MHz at a supply voltage of 2.5V. Since we are assuming that all input combinations are equally likely, for all time, the transition probabilities for the gates will be equal to the transition activities (defined as the average over a long period). If we call the nor output node1, and xnor output node 2, the dynamic power will be: P dyn = 1 fc 1 Vdd fc 2 Vdd 2 F fc F Vdd 2 The average switched capacitances ( C) are C 1 = 3/ fF = 0.45fF C 2 = 1/ fF = 1.2fF F C F = 3/16 12fF = 2.25fF Therefore, P dyn = fvdd 2 ( 1 C C 2 + F C F ) = 200MHz (2.5 V) 2 3.9fF 4.9 W Note that, all of these three gates consume power consumption. Since they have different switching probabilities and loading capacitors, so we have to calculate these parts separately and then get the total power. 5. Dynamic circuits: Consider the domino stage shown below. Assume that each of the PDN in the figure has a single NMOS transistor. Assume the precharge time, evaluate time, propagation delay of these static inverters are all equal to 10ns each. Also assume zero rise and fall times for all signals. Complete the timing diagram for signals Out1, Out2, Out3 and Out4 if the IN signal goes high at the rising edge of the clock. Assume clock period is 100ns. (20) Fig.3 4

5 Note that, the difference of this question from our hw question is that different stages are using different clocks and therefore the output waveforms are shifted. 6. Explain how each item below can achieve low power. Describe how a designer can use these techniques in low power design with example. (10) a) Multiple Vdd b) Multiple VT a) Multiple Vdd: Principle: The power consumption will increase with the increasing Vdd: the dynamic power consumption will depend on the square of vdd and the leakage power will depend on V dd. But the speed will be enhanced with increasing Vdd due to stronger driving ability. Usage: In the non-crucial path, low Vdd will be applied to decrease power consumption; in crucial path, high vdd is applied to keep the performance. b) Multiple VT Principle: High VT transistor generates less leakage current, thereby generating less power consumption, but its speed is decreased. On the other hand, low VT transistor generates more leakage power consumption, but its speed characteristics is superior. Usage: High VT transistors are employed to achieve low power design in the non-crucial path; low VT transistors are employed to keep the performance in the crucial path. 5