High Speed Design Issues and Jitter Estimation Techniques. Jai Narayan Tripathi
|
|
- Ellen Fowler
- 5 years ago
- Views:
Transcription
1 High Speed Design Issues and Jitter Estimation Techniques Jai Narayan Tripathi
2 Outline Part 1 High-speed Design Issues Signal Integrity Power Integrity Jitter Power Delivery Network Building the cumulative PDN model for entire system Effects on supply ripple on output Importance of optimal PDN design vs under/over design Impedance and Ripple profiles before and after optimization Part 2- Jitter Estimation Techniques System under consideration Method1: Numerical Method Method2: EMPSIJ Method3: Delay based Modeling
3 Part 1 High-speed Design Issues
4 Signal Integrity and Power Integrity Interconnects behave as transmission lines at high frequencies. Signal Integrity (SI) refers to the quality of signal propagating from one point to another point in a network in terms of distortion, attenuation and noise. Power Integrity (PI) refers to the quality of power in a system in terms of sufficiency, efficiency and stability. Jitter is timing variation of a rising/falling edge from its ideal timing. It is measured at the midpoints of the rising/falling edges. Jitter is one of the most important timing metrics used for characterizing high-speed systems for signal/power integrity. Jitter is affected by both signal and power integrity. Fig: A sample rising edge having jitter
5 Signal/Power delivery Network (PDN) Most of the electronics systems are typically implemented with multi-layer PCB, Packages where operating circuits need constant supply voltages to function properly. SDN consists of bond wires, PCB traces, package nets, on-chip interconnects, etc. Typically PDN consists of: - Voltage Regulator Module (VRM), Traces, Vias, Power-GND planes and decoupling capacitors (decaps) on PCB. - Traces, Vias, Power-GND planes, Bond wires or RDL on Package - Supply GND rails, supply grids/mesh implemented on Die PCB Package Die Supply Grid/Mesh Supply GND rails
6 Package Supply routing System Description DDR3 based system implemented with Noisy supplies wire-bond BGA package, multi-layer PCB with shared power supplies PACKAGE PCB system on chip (SoC) running multiple processor cores thus leading to very high core current consumption. The core supply is also shared by internal clock tree (buffer -chain), which is susceptible to supply noise and thus adds jitter during clock propagation. 32-bit memory interface operating at 1334 Mbps SoC PLL Supply rail + On-die decaps Core Logic Clock tree DDR Contr -oller Clock manager DDR I/O pad ring Clock jitter at memory input DDR3 Memory 32 bits for storage of application data, thus leading to high IO switching current due to SSO. OSC Core supply VRMs Wire bond package contributes to high PDN impedance. PCB Supply routing + decaps IO supply Fig: A DDR3 memory based system
7 System level co-simulation environment Power delivery network modelling On DIE PDN (I/O ring, CPM) Package PDN PCB PDN with decap network VRM Model Core supply (ideal) I/O supply (ideal) Core Chip power model Noisy supplies at clock tree and Clock IO due to PDN impedance I/O Ring modelling to generate worst case SSN. CPM representing core switching. SoC Clock (Ideal) Internal SoC Clock tree Eye diagram and jitter analysis I/O buffer SPICE model DDR Differential Clock (Ideal) 667 MHz Package Signal trace model PCB Signal trace model High speed clock path modelling Termination Memory IBIS Model Fig: SI/PI Co-simulation environment
8 PDN Impedance extraction and optimization S-parameters for PDN interconnects can be extracted using EM solver tools. Z-parameters or impedances for power delivery network model can be computed from S- parameters. Voltage ripple generated at any location in a PDN can be analysed and contribution of self and transfer impedances can be quantified. PDN should be optimized, such that values of self and transfer impedances are within permissible limit which is known as Target impedance. Target impedance can be determined as : Z(target) = V/I Where V is the acceptable voltage ripple and I is the switching current at the location where Z(target) is determined.
9 PDN Impedance Composite PDN model and resonance Due to interaction of inductors and capacitors, PDN exhibits resonance and anti-resonance, where magnitude of impedance peaks at certain frequencies. Anti-resonance peaks can be suppressed by selection of appropriate decaps based on resonant frequencies. Resistive Inductive Capacitive VRM Model PCB Model with decaps VRM PCB with Decaps Package Die Anti-resonance peaks Frequency Package Model with Decaps On die Model IO supply PDN Core supply PDN Impedance seen from die side is PDN impedance
10 Eye Diagrams Ideal PDN Eye diagrams are used to visualize and measure amplitude noise and timing noise (jitter), over a large number of bits by superimposing them in one time interval. There are various measurements can be performed by creating eye-diagrams e.g. eye-height, SNR, jitter etc.
11 Effects of Power Supply ripples Effect of Power supply ripple are directly transferred to the output of driver circuit. Amplitude distortion and jitter are two adverse effects. Clock Buffer Jitter effects are worse as it impacts the setup hold margins and thereby cause system failure.
12 Importance of optimal PDN design PDN plays important role is ensuring stable and ripple-free power supply to the operating circuits. Both Self impedance and Transfer impedance should be analysed to mitigate self generated ripple and transferred ripple from other aggressor. Thus PDN optimization is an essential task during system design. Under-designed PDN may lead to excessive supply ripple at certain frequencies where PDN impedance is very high due to anti-resonance. Over designing the PDN may require more decoupling capacitors, more PWR-GND plane layers, more area on-die and thus lead to higher cost of system.
13 IO Supply: Impedance profiles with original and optimized PDN Impedance reduction could be achieved at 30MHz and at around 200 MHz by Package decap optimization. Addition of on-die decap indicates improvement in anti-resonance peak at higher frequency. 2 rows of on-die caps are added to reduce the antiresonance peak. Peak impedance is reduced from 3.5 ohm to 1 ohm.
14 Core supply: Impedance profiles with original and optimized PDN VDD PDN Impedance PDN impedance peak reduced from 690mohms to 100mohms. Supply ripple peak reduced from 41mV to 26mV.
15 IO Supply: Ripple profiles in different implementations
16 Differential Clock jitter with original and optimized PDN implementation PCB, PKG default PDN Optimized PKG decaps Additional on-die decaps Eye Jitter (PP) = e-10 Eye Jitter (PP) = e-11 Eye Jitter (PP) = e-11
17 Part II Jitter Estimation Techniques
18 Jitter Estimation Techniques Numerical Method Slope Based Modeling (EMPSIJ) Delay based Modeling
19 Basic Idea Finding large-signal and small-signal analysis separately. Approximating the system response as a linear sum of both the responses. D Fig : (a) System response without PDN and (b) System response with PDN
20 Numerical Method: Circuit Overview A voltage-mode low-voltage signaling driver circuit is analyzed for Power Supply Induced Jitter (PSIJ). Used in high-speed data links e.g. serial links for differential signaling. Differential signaling reduces common-mode noise. Fig : Voltage-Mode Driver* *J. N. Tripathi et al., An Analysis of Power Supply Induced Jitter for a Voltage Mode Driver in High Speed Serial Links, Proc. 20th IEEE Workshop on Signal and Power Integrity (SPI), pp , May 2016, Torino, Italy,
21 Voltage-Mode Driver Fig : Impact of noise on output in Voltage-Mode Driver
22 Voltage-Mode Driver Fig : Voltage supply with PDN noise and Vsup node Voltage is fairly stable at node Vsup, so it can be used as a voltage source for equivalent large-signal model.
23 Numerical Method An equivalent model can be used for large-signal analysis. Fig : Large-signal equivalent model
24 Numerical Method Fig : Path of noise from PDN to DP/DN
25 Numerical Method An equivalent model can be used for small-signal analysis. Fig : Small-signal equivalent model
26 Numerical Method The complete system response can be written as: This can be used to find time interval error using root-finding approach. Fig : Small-signal equivalent model
27 Numerical Method A function can be defined as: This can be used to find time interval error using root-finding approach. TIE for the k th bit can be found as:
28 Numerical Method: Results Fig: PSIJ estimation for noise as sin wave (850 MHz)* Fig: PSIJ estimation for noise as triangular wave (time period: 1.53 nsec)* *J. N. Tripathi, F. G. Canavero, An Efficient Estimation of Power Supply Induced Jitter by Numerical Method, IEEE Microwave and Wireless Components Letters (MWCL), pp. 1-3, 2017 (in press).
29 Slope based Method Instead of using Numerical methods, a nonlinear approximation can be used to speed-up the estimation time (having all other assumptions intact). For the case of VM driver used in earlier case study, the same is demonstrated. Instead if using the large-signal response as a sum of exponentials, it can be approximated as nonlinear functions of time, in different time interval. To estimate jitter the point of interest is midpoint, thus the nonlinear function of that time interval can be used as instead of the complete large-signal model.
30 Slope based Method Fig: Piecewise nonlinear modeling of the output differential voltage for the case when noise = 0
31 Slope based Method
32 Slope based Method Time intervals can be divided into even smaller time intervals. In the limiting case, the time interval having the midpoint, can be modeled as with three points, as a straight line.
33 Slope based Method Thus jitter can be modeled as a ratio of noise output to the slope of output (without noise). If there are multiple frequencies in PDN noise, the output noise can be modeled using Fourier series coefficients of the. Instantaneous Jitter (TIE) for the k th bit can be calculated as*: *J. N. Tripathi et al., An Efficient Modeling of Power Supply Induced Jitter (EMPSIJ), IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), pp. 1-11, July 2017 (early access).
34 Slope based Method: Results Fig: Comparison of PSIJ for a sinusoidal input in 55nm technology Approach-1 is nonlinear modeling and Approach-2 is slope based modeling. Conventional approach is estimation by simulations in EDA tools.
35 Slope based Method: Results Fig: Comparison of PSIJ using both the Proposed and Conventional methods for saw-tooth noise input in 28-nm FD-SOI technology
36 Slope based Method: Results PDN noise contains 8 dominant frequency components. Speed-up is >400 with accuracy being more than 95%. Fig: A practical PDN noise and its impact on the output
37 Delay based Method: Circuit Description A current-mode low-voltage signaling driver circuit is analyzed for Power Supply Induced Jitter (PSIJ). Used in high-speed data links e.g. serial links for differential signaling. Differential signaling reduces common-mode noise. Fig : Current-Mode Driver* *J. N. Tripathi et al., Analysis of a Serial Link for Power Supply Induced Jitter, 27 th IEEE System-On-Chip Conference, pp , Beijing, Sept
38 Delay based Method Fig : Illustration of the current (I s (t)) delivered by the transistor M s (dashed line) and the differential output voltage (v R (t), solid line) across terminals DP and DN Fig : Large-signal equivalent for Current-Mode Driver
39 Delay based Method: Circuit Description Large-signal output response can be modeled by following set of equations:
40 Delay based Method Based on midpoint delays, s single-ended outputs can be modeled as per their effective time constants. ; ; Fig : Input signals v IN1 and v IN2 at gates of M 2 and M 3 respectively, their corresponding output voltages at v X (t) and v Y (t) with delays shown by the markers.
41 Delay based Method Based on the equivalent model, time interval error can be formulated. For differential signal, v Rn (t) = 0 at t m Fig : Comparison of v R (t) obtained using the approximate Model and Simulation by EDA tool
42 Delay based Method Differential small-signal output can be modeled as: where Fig : Small-signal equivalent circuit for CM driver
43 Delay based Method: Results (Ex. 1) Fig: Comparison of PSIJ using both the Proposed Approach and the Conventional methods for pulse train noise input in 55nm technology
44 Delay based Method: Results (Ex. 2) Fig: Construction of a Pulse Train waveform from 20 frequencies Fig: PDN noise (represented by pulse train wave) superimposed on supply voltage (V DD + v n (t); right-y axis, dotted line) and the corresponding differential output (v Rn (t); left-y axis, solid line)
45 Delay based Method: Results (Ex. 3) Fig: Comparison of PSIJ using both the Proposed Approach and the Conventional methods for pulse train noise input in 55nm technology
46 Delay based Method: Results (Ex. 3) Fig: Comparison of PSIJ using both the Proposed and Conventional methods for saw-tooth noise input in 28- nm FD-SOI technology* *J. N. Tripathi et al., Fast Estimation of Time Interval Error in Current-Mode Drivers, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), pp. 1-11, 2017 (in press).
47 Summary/Conclusions Signal/Power Integrity issues are very critical in high-speed Soc designs. Jitter estimation techniques with good accuracy are required to reduce the design time of SoCs. Some of the recently proposed/developed estimation techniques were discussed. The proposed techniques can significantly reduce the estimation time and speed-up the complete design cycle of SoCs.
48 Summary System level PDN modelling carried out with PCB, Package and on-die (CPM, lumped) models. Optimization areas are identified based on resonance profile of PDN. Decap network optimized with appropriate parts based on their resonant frequencies. Significant improvement achieved in Clock tree and Clock IO jitter with optimized PDN.
49 Acknowledgements/Collaborations Prof. Ramachandra Achar, Carleton University, Ottawa, Canada. Prof. Hitesh Shrimali and Vijender Kumar Sharma, Indian Institute of Technology Mandi, H.P., INDIA. Prof. Flavio G. Canavero, Politecnico Di Torino, Turin, Italy. Pratik Damle, Texas Instruments, INDIA. Hiten Advani and Rajkumar Nagpal, Synopsys Inc., INDIA.
50 Thank You.
Engineering the Power Delivery Network
C HAPTER 1 Engineering the Power Delivery Network 1.1 What Is the Power Delivery Network (PDN) and Why Should I Care? The power delivery network consists of all the interconnects in the power supply path
More informationSignal Integrity Design of TSV-Based 3D IC
Signal Integrity Design of TSV-Based 3D IC October 24, 21 Joungho Kim at KAIST joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr 1 Contents 1) Driving Forces of TSV based 3D IC 2) Signal Integrity Issues
More informationEMI Reduction on an Automotive Microcontroller
EMI Reduction on an Automotive Microcontroller Design Automation Conference, July 26 th -31 st, 2009 Patrice JOUBERT DORIOL 1, Yamarita VILLAVICENCIO 2, Cristiano FORZAN 1, Mario ROTIGNI 1, Giovanni GRAZIOSI
More informationThank you for downloading one of our ANSYS whitepapers we hope you enjoy it.
Thank you! Thank you for downloading one of our ANSYS whitepapers we hope you enjoy it. Have questions? Need more information? Please don t hesitate to contact us! We have plenty more where this came from.
More informationPower integrity is more than decoupling capacitors The Power Integrity Ecosystem. Keysight HSD Seminar Mastering SI & PI Design
Power integrity is more than decoupling capacitors The Power Integrity Ecosystem Keysight HSD Seminar Mastering SI & PI Design Signal Integrity Power Integrity SI and PI Eco-System Keysight Technologies
More informationActive and Passive Techniques for Noise Sensitive Circuits in Integrated Voltage Regulator based Microprocessor Power Delivery
Active and Passive Techniques for Noise Sensitive Circuits in Integrated Voltage Regulator based Microprocessor Power Delivery Amit K. Jain, Sameer Shekhar, Yan Z. Li Client Computing Group, Intel Corporation
More informationLow power SERDES transceiver for supply-induced jitter sensitivity methodology analysis
Low power SERDES transceiver for supply-induced jitter sensitivity methodology analysis Micro Chang htc Michael_Chang@hTC.com Jan 9, 2019 X 1 Agenda Jitter-aware target impedance of power delivery network
More informationChip Package - PC Board Co-Design: Applying a Chip Power Model in System Power Integrity Analysis
Chip Package - PC Board Co-Design: Applying a Chip Power Model in System Power Integrity Analysis Authors: Rick Brooks, Cisco, ricbrook@cisco.com Jane Lim, Cisco, honglim@cisco.com Udupi Harisharan, Cisco,
More informationPDN design and analysis methodology in SI&PI codesign
PDN design and analysis methodology in SI&PI codesign www.huawei.com Asian IBIS Summit, November 9, 2010, Shenzhen China Luo Zipeng (luozipeng@huawei.com) Liu Shuyao (liushuyao@huawei.com) HUAWEI TECHNOLOGIES
More informationMicrocircuit Electrical Issues
Microcircuit Electrical Issues Distortion The frequency at which transmitted power has dropped to 50 percent of the injected power is called the "3 db" point and is used to define the bandwidth of the
More informationCyclone III Simultaneous Switching Noise (SSN) Design Guidelines
Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines December 2007, ver. 1.0 Introduction Application Note 508 Low-cost FPGAs designed on 90-nm and 65-nm process technologies are made to support
More informationAutomotive PCB SI and PI analysis
Automotive PCB SI and PI analysis SI PI Analysis Signal Integrity S-Parameter Timing analysis Eye diagram Power Integrity Loop / Partial inductance DC IR-Drop AC PDN Impedance Power Aware SI Signal Integrity
More informationA Simulation Study of Simultaneous Switching Noise
A Simulation Study of Simultaneous Switching Noise Chi-Te Chen 1, Jin Zhao 2, Qinglun Chen 1 1 Intel Corporation Network Communication Group, LOC4/19, 9750 Goethe Road, Sacramento, CA 95827 Tel: 916-854-1178,
More informationBroadband Methodology for Power Distribution System Analysis of Chip, Package and Board for High Speed IO Design
DesignCon 2009 Broadband Methodology for Power Distribution System Analysis of Chip, Package and Board for High Speed IO Design Hsing-Chou Hsu, VIA Technologies jimmyhsu@via.com.tw Jack Lin, Sigrity Inc.
More informationEffect of Power Noise on Multi-Gigabit Serial Links
Effect of Power Noise on Multi-Gigabit Serial Links Ken Willis (kwillis@sigrity.com) Kumar Keshavan (ckumar@sigrity.com) Jack Lin (jackwclin@sigrity.com) Tariq Abou-Jeyab (tariqa@sigrity.com) Sigrity Inc.,
More informationSystem Co-design and optimization for high performance and low power SoC s
System Co-design and optimization for high performance and low power SoC s Siva S Kothamasu, Texas Instruments Inc, Dallas Snehamay Sinha, Texas Instruments Inc, Dallas Amit Brahme, Texas Instruments India
More informationPDS Impact for DDR Low Cost Design
PDS Impact for DDR3-1600 Low Cost Design Jack W.C. Lin Sr. AE Manager jackl@cadence.com Aug. g 13 2013 Cadence, OrCAD, Allegro, Sigrity and the Cadence logo are trademarks of Cadence Design Systems, Inc.
More informationIntro. to PDN Planning PCB Stackup Technology Series
Introduction to Power Distribution Network (PDN) Planning Bill Hargin In-Circuit Design b.hargin@icd.com.au 425-301-4425 Intro. to PDN Planning 1. Intro/Overview 2. Bypass/Decoupling Strategy 3. Plane
More informationPractical Limitations of State of the Art Passive Printed Circuit Board Power Delivery Networks for High Performance Compute Systems
Practical Limitations of State of the Art Passive Printed Circuit Board Power Delivery Networks for High Performance Compute Systems Presented by Chad Smutzer Mayo Clinic Special Purpose Processor Development
More informationPower Distribution Network Design for Stratix IV GX and Arria II GX FPGAs
Power Distribution Network Design for Stratix IV GX and Arria II GX FPGAs Transceiver Portfolio Workshops 2009 Question What is Your PDN Design Methodology? Easy Complex Historical Full SPICE simulation
More informationHigh-speed Serial Interface
High-speed Serial Interface Lect. 9 Noises 1 Block diagram Where are we today? Serializer Tx Driver Channel Rx Equalizer Sampler Deserializer PLL Clock Recovery Tx Rx 2 Sampling in Rx Interface applications
More informationTaking the Mystery out of Signal Integrity
Slide - 1 Jan 2002 Taking the Mystery out of Signal Integrity Dr. Eric Bogatin, CTO, GigaTest Labs Signal Integrity Engineering and Training 134 S. Wolfe Rd Sunnyvale, CA 94086 408-524-2700 www.gigatest.com
More informationDesignCon On-Chip Power Supply Noise and Reliability Analysis for Multi-Gigabit I/O Interfaces
DesignCon 2010 On-Chip Power Supply Noise and Reliability Analysis for Multi-Gigabit I/O Interfaces Ralf Schmitt, Rambus Inc. [Email: rschmitt@rambus.com] Hai Lan, Rambus Inc. Ling Yang, Rambus Inc. Abstract
More informationMinimizing Coupling of Power Supply Noise Between Digital and RF Circuit Blocks in Mixed Signal Systems
Minimizing Coupling of Power Supply Noise Between Digital and RF Circuit Blocks in Mixed Signal Systems Satyanarayana Telikepalli, Madhavan Swaminathan, David Keezer Department of Electrical & Computer
More informationEffect of Aging on Power Integrity of Digital Integrated Circuits
Effect of Aging on Power Integrity of Digital Integrated Circuits A. Boyer, S. Ben Dhia Alexandre.boyer@laas.fr Sonia.bendhia@laas.fr 1 May 14 th, 2013 Introduction and context Long time operation Harsh
More informationECEN720: High-Speed Links Circuits and Systems Spring 2017
ECEN720: High-Speed Links Circuits and Systems Spring 2017 Lecture 9: Noise Sources Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Lab 5 Report and Prelab 6 due Apr. 3 Stateye
More informationIntroduction to EMI/EMC Challenges and Their Solution
Introduction to EMI/EMC Challenges and Their Solution Dr. Hany Fahmy HSD Application Expert Agilent Technologies Davy Pissort, K.U. Leuven Charles Jackson, Nvidia Charlie Shu, Nvidia Chen Wang, Nvidia
More informationWideband On-die Power Supply Decoupling in High Performance DRAM
Wideband On-die Power Supply Decoupling in High Performance DRAM Timothy M. Hollis, Senior Member of the Technical Staff Abstract: An on-die decoupling scheme, enabled by memory array cell technology,
More informationConsiderations in High-Speed High Performance Die-Package-Board Co-Design. Jenny Jiang Altera Packaging Department October 2014
Considerations in High-Speed High Performance Die-Package-Board Co-Design Jenny Jiang Altera Packaging Department October 2014 Why Co-Design? Complex Multi-Layer BGA Package Horizontal and vertical design
More informationAn Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks
An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks Sanjay Pant, David Blaauw University of Michigan, Ann Arbor, MI Abstract The placement of on-die decoupling
More informationCORRELATION OF PDN IMPEDANCE WITH JITTER AND VOLTAGE MARGIN IN HIGH SPEED CHANNELS
CORRELATION OF PDN IMPEDANCE WITH JITTER AND VOLTAGE MARGIN IN HIGH SPEED CHANNELS A Thesis Presented to The Academic Faculty By Vishal Laddha In Partial Fulfillment of the Requirements for the Degree
More informationSi-Interposer Collaboration in IC/PKG/SI. Eric Chen
Si-Interposer Collaboration in IC/PKG/SI Eric Chen 4/Jul/2014 Design Overview U-bump Logic IC Mem IC C4 bump Logic IC Silicon/Organic substrate Interposer Mem IC CAP Package substrate Solder Ball VRM BGA
More informationEnsuring Signal and Power Integrity for High-Speed Digital Systems
Ensuring Signal and Power Integrity for High-Speed Digital Systems An EMC Perspective Christian Schuster Institut für Theoretische Elektrotechnik Technische Universität Hamburg-Harburg (TUHH) Invited Presentation
More informationCIRCUITS. Raj Nair Donald Bennett PRENTICE HALL
POWER INTEGRITY ANALYSIS AND MANAGEMENT I CIRCUITS Raj Nair Donald Bennett PRENTICE HALL Upper Saddle River, NJ Boston Indianapolis San Francisco New York Toronto Montreal London Munich Paris Madrid Capetown
More informationQuick guide to Power. V1.2.1 July 29 th 2013
Quick guide to Power Distribution ib ti Network Design V1.2.1 July 29 th 2013 High level High current, high transient Power Distribution Networks (PDN) need to be able to respond to changes and transients
More informationLearning the Curve BEYOND DESIGN. by Barry Olney
by Barry Olney coulmn BEYOND DESIGN Learning the Curve Currently, power integrity is just entering the mainstream market phase of the technology adoption life cycle. The early market is dominated by innovators
More informationRelationship Between Signal Integrity and EMC
Relationship Between Signal Integrity and EMC Presented by Hasnain Syed Solectron USA, Inc. RTP, North Carolina Email: HasnainSyed@solectron.com 06/05/2007 Hasnain Syed 1 What is Signal Integrity (SI)?
More informationBasic Concepts C HAPTER 1
C HAPTER 1 Basic Concepts Power delivery is a major challenge in present-day systems. This challenge is expected to increase in the next decade as systems become smaller and new materials are introduced
More informationFoundry WLSI Technology for Power Management System Integration
1 Foundry WLSI Technology for Power Management System Integration Chuei-Tang Wang, Chih-Lin Chen, Jeng-Shien Hsieh, Victor C.Y. Chang, Douglas Yu R&D,TSMC Oct. 2016 2 Motivation Outline PMIC system integration
More informationSSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity
DESIGNCON 2009 SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity Vishram S. Pandit, Intel Corporation [vishram.s.pandit@intel.com, (916)356-2059] Ashish N. Pardiwala, Intel Corporation
More informationComparison of IC Conducted Emission Measurement Methods
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 52, NO. 3, JUNE 2003 839 Comparison of IC Conducted Emission Measurement Methods Franco Fiori, Member, IEEE, and Francesco Musolino, Member, IEEE
More informationPDN Application of Ferrite Beads
PDN Application of Ferrite Beads 11 TA3 Steve Weir CTO IPBLOX, LLC 1 Objectives Understand ferrite beads with a good model Understand PDN design w/ sensitive loads Understand how to determine when a ferrite
More informationDDR4 SI/PI Analysis Using IBIS5.0
DDR4 SI/PI Analysis Using IBIS5.0 Socionext Inc. Yumiko Sugaya Asian IBIS Summit, Tokyo, Japan November 16, 2015 Outline Overview DDR4 SI/PI Analysis Issue Over Clocking issue DDR4 SI/PI Analysis Using
More informationAdding On-Chip Capacitance in IBIS Format for SSO Simulation
Adding On-Chip Capacitance in IBIS Format for SSO Simulation Raymond Y. Chen SIGRITY, Inc. Jan. 2004 DesignCon 2004 - IBIS Summit Presentation Agenda 1. Is IBIS good for SSO simulation 2. SSO simulation
More informationDigital Systems Power, Speed and Packages II CMPE 650
Speed VLSI focuses on propagation delay, in contrast to digital systems design which focuses on switching time: A B A B rise time propagation delay Faster switching times introduce problems independent
More informationDesign of the Power Delivery System for Next Generation Gigahertz Packages
Design of the Power Delivery System for Next Generation Gigahertz Packages Madhavan Swaminathan Professor School of Electrical and Computer Engg. Packaging Research Center madhavan.swaminathan@ece.gatech.edu
More informationMyoung Joon Choi, Vishram S. Pandit Intel Corp.
Myoung Joon Choi, Vishram S. Pandit Intel Corp. IBIS Summit at DesignCon 2010 Acknowledgements: Woong Hwan Ryu, Joe Salmon Copyright 2010, Intel Corporation. All rights reserved. Need for SI/PI Co-analysis
More informationHow to anticipate Signal Integrity Issues: Improve my Channel Simulation by using Electromagnetic based model
How to anticipate Signal Integrity Issues: Improve my Channel Simulation by using Electromagnetic based model HSD Strategic Intent Provide the industry s premier HSD EDA software. Integration of premier
More informationANSYS CPS SOLUTION FOR SIGNAL AND POWER INTEGRITY
ANSYS CPS SOLUTION FOR SIGNAL AND POWER INTEGRITY Rémy FERNANDES Lead Application Engineer ANSYS 1 2018 ANSYS, Inc. February 2, 2018 ANSYS ANSYS - Engineering simulation software leader Our industry reach
More informationSignal integrity means clean
CHIPS & CIRCUITS As you move into the deep sub-micron realm, you need new tools and techniques that will detect and remedy signal interference. Dr. Lynne Green, HyperLynx Division, Pads Software Inc The
More informationThe Inductance Loop Power Distribution in the Semiconductor Test Interface. Jason Mroczkowski Multitest
The Inductance Loop Power Distribution in the Semiconductor Test Interface Jason Mroczkowski Multitest j.mroczkowski@multitest.com Silicon Valley Test Conference 2010 1 Agenda Introduction to Power Delivery
More informationSingle-Ended to Differential Converter for Multiple-Stage Single-Ended Ring Oscillators
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003 141 Single-Ended to Differential Converter for Multiple-Stage Single-Ended Ring Oscillators Yuping Toh, Member, IEEE, and John A. McNeill,
More informationModeling System Signal Integrity Uncertainty Considerations
white paper Intel FPGA Modeling System Signal Integrity Uncertainty Considerations Authors Ravindra Gali High-Speed I/O Applications Engineering, Intel Corporation Zhi Wong High-Speed I/O Applications
More informationAn Analog Phase-Locked Loop
1 An Analog Phase-Locked Loop Greg Flewelling ABSTRACT This report discusses the design, simulation, and layout of an Analog Phase-Locked Loop (APLL). The circuit consists of five major parts: A differential
More informationLow Jitter, Low Emission Timing Solutions For High Speed Digital Systems. A Design Methodology
Low Jitter, Low Emission Timing Solutions For High Speed Digital Systems A Design Methodology The Challenges of High Speed Digital Clock Design In high speed applications, the faster the signal moves through
More information04/29/03 EE371 Power Delivery D. Ayers 1. VLSI Power Delivery. David Ayers
04/29/03 EE371 Power Delivery D. Ayers 1 VLSI Power Delivery David Ayers 04/29/03 EE371 Power Delivery D. Ayers 2 Outline Die power delivery Die power goals Typical processor power grid Transistor power
More informationPower Supply Networks: Analysis and Synthesis. What is Power Supply Noise?
Power Supply Networs: Analysis and Synthesis What is Power Supply Noise? Problem: Degraded voltage level at the delivery point of the power/ground grid causes performance and/or functional failure Lower
More informationCharacterization of Alternate Power Distribution Methods for 3D Integration
Characterization of Alternate Power Distribution Methods for 3D Integration David C. Zhang, Madhavan Swaminathan, David Keezer and Satyanarayana Telikepalli School of Electrical and Computer Engineering,
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 Lecture 5: Termination, TX Driver, & Multiplexer Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements
More informationSystem Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor
System Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production Wai-Yeung
More informationThe Role of Voltage Regulation in Power Integrity for Multi-Gbps Parallel I/O Interfaces. Yue Yin
The Role of Voltage Regulation in Power Integrity for Multi-Gbps Parallel I/O Interfaces by Yue Yin A thesis submitted in conformity with the requirements for the degree of Master of Applied Science, The
More informationSystem Power Distribution Network Theory and Performance with Various Noise Current Stimuli Including Impacts on Chip Level Timing
System Power Distribution Network Theory and Performance with Various Noise Current Stimuli Including Impacts on Chip Level Timing Larry Smith, Shishuang Sun, Peter Boyle, Bozidar Krsnik Altera Corp. Abstract-Power
More informationSubstrate Coupling in RF Analog/Mixed Signal IC Design: A Review
Substrate Coupling in RF Analog/Mixed Signal IC Design: A Review Ashish C Vora, Graduate Student, Rochester Institute of Technology, Rochester, NY, USA. Abstract : Digital switching noise coupled into
More informationPrinted circuit board power distribution network modeling, analysis and design, and, statistical crosstalk analysis for high speed digital links
Scholars' Mine Doctoral Dissertations Student Research & Creative Works Spring 2015 Printed circuit board power distribution network modeling, analysis and design, and, statistical crosstalk analysis for
More informationSignal Integrity Modeling and Simulation for IC/Package Co-Design
Signal Integrity Modeling and Simulation for IC/Package Co-Design Ching-Chao Huang Optimal Corp. October 24, 2004 Why IC and package co-design? The same IC in different packages may not work Package is
More informationOn Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital VLSI
ELEN 689 606 Techniques for Layout Synthesis and Simulation in EDA Project Report On Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital
More informationImpedance Matching: Terminations
by Barry Olney IN-CIRCUIT DESIGN PTY LTD AUSTRALIA column BEYOND DESIGN Impedance Matching: Terminations The impedance of the trace is extremely important, as any mismatch along the transmission path will
More informationReliable World Class Insights Your Silicon Valley Partner in Simulation ANSYS Sales, Consulting, Training & Support
www.ozeninc.com info@ozeninc.com (408) 732 4665 1210 E Arques Ave St 207 Sunnyvale, CA 94085 Reliable World Class Insights Your Silicon Valley Partner in Simulation ANSYS Sales, Consulting, Training &
More informationPCB power supply noise measurement procedure
PCB power supply noise measurement procedure What has changed? Measuring power supply noise in high current, high frequency, low voltage designs is no longer simply a case of hooking up an oscilloscope
More informationTITLE. Capturing (LP)DDR4 Interface PSIJ and RJ Performance. Image. Topic: Topic: John Ellis, Synopsys, Inc. Topic: malesuada blandit euismod.
TITLE Topic: o Nam elementum commodo mattis. Pellentesque Capturing (LP)DDR4 Interface PSIJ and RJ Performance malesuada blandit euismod. Topic: John Ellis, Synopsys, Inc. o o Nam elementum commodo mattis.
More informationEECS 473 Advanced Embedded Systems. Lecture 9: Groups introduce their projects Power integrity issues
EECS 473 Advanced Embedded Systems Lecture 9: Groups introduce their projects Power integrity issues Project groups Please give a 2-3 minute overview of your project. Half the groups will do this each
More informationOptimizing On Die Decap in a System at Early Stage of Design Cycle
Optimizing On Die Decap in a System at Early Stage of Design Cycle Naresh Dhamija Pramod Parameswaran Sarika Jain Makeshwar Kothandaraman Praveen Soora Disclaimer: The scope of approach presented is limited
More informationImpact of On-Chip Multi-Layered Inductor on Signal and Power Integrity of Underlying Power-Ground Net
22 nd IEEE Workshop on Signal and Power Integrity, Brest, FRANCE May 25, 2018 Impact of On-Chip Multi-Layered Inductor on Signal and Power Integrity of Underlying Power-Ground Net Akira Tsuchicya 1, Akitaka
More informationElectromagnetic Analysis and Verification of Probe Card Performance for First Pass System Success
San Diego, CA Electromagnetic Analysis and Verification of Probe Card Performance for First Pass System Success Cristian Gozzi Application Engineer Manager Introduction Today in Multi Probe wafer level,
More informationEECS 473 Advanced Embedded Systems. Lecture 9: Groups introduce their projects Power integrity issues
EECS 473 Advanced Embedded Systems Lecture 9: Groups introduce their projects Power integrity issues Final proposal due today Final proposal I should have signed group agreement now. I should have feedback
More informationECE 497 JS Lecture - 22 Timing & Signaling
ECE 497 JS Lecture - 22 Timing & Signaling Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Announcements - Signaling Techniques (4/27) - Signaling
More informationApplication of Generalized Scattering Matrix for Prediction of Power Supply Noise
Application of Generalized Scattering Matrix for Prediction of Power Supply Noise System Level Interconnect Prediction 2010 June 13, 2010 K. Yamanaga (1),K. Masu (2), and T. Sato (3) (1) Murata Manufacturing
More informationDecoupling Capacitance
Decoupling Capacitance Nitin Bhardwaj ECE492 Department of Electrical and Computer Engineering Agenda Background On-Chip Algorithms for decap sizing and placement Based on noise estimation Decap modeling
More informationCompensation for Simultaneous Switching Noise in VLSI Packaging Brock J. LaMeres University of Colorado September 15, 2005
Compensation for Simultaneous Switching Noise in VLSI Packaging Brock J. LaMeres University of Colorado 1 Problem Statement Package Interconnect Limits VLSI System Performance The three main components
More informationJANUARY 28-31, 2013 SANTA CLARA CONVENTION CENTER. World s First LPDDR3 Enabling for Mobile Application Processors System
JANUARY 28-31, 2013 SANTA CLARA CONVENTION CENTER World s First LPDDR3 Enabling for Mobile Application Processors System Contents Introduction Problem Statements at Early mobile platform Root-cause, Enablers
More informationDecoupling capacitor placement
Decoupling capacitor placement Covered in this topic: Introduction Which locations need decoupling caps? IC decoupling Capacitor lumped model How to maximize the effectiveness of a decoupling cap Parallel
More informationA Co-design Methodology of Signal Integrity and Power Integrity
DesignCon 2006 A Co-design Methodology of Signal Integrity and Power Integrity Woong Hwan Ryu, Intel Corporation woong.hwan.ryu@intel.com Min Wang, Intel Corporation min.wang@intel.com 1 Abstract As PCB
More informationDecoupling capacitor uses and selection
Decoupling capacitor uses and selection Proper Decoupling Poor Decoupling Introduction Covered in this topic: 3 different uses of decoupling capacitors Why we need decoupling capacitors Power supply rail
More informationDesign Considerations for Highly Integrated 3D SiP for Mobile Applications
Design Considerations for Highly Integrated 3D SiP for Mobile Applications FDIP, CA October 26, 2008 Joungho Kim at KAIST joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr Contents I. Market and future direction
More informationDesign Fundamentals by A. Ciccomancini Scogna, PhD Suppression of Simultaneous Switching Noise in Power and Ground Plane Pairs
Design Fundamentals by A. Ciccomancini Scogna, PhD Suppression of Simultaneous Switching Noise in Power and Ground Plane Pairs Photographer: Janpietruszka Agency: Dreamstime.com 36 Conformity JUNE 2007
More informationLecture 10. Circuit Pitfalls
Lecture 10 Circuit Pitfalls Intel Corporation jstinson@stanford.edu 1 Overview Reading Lev Signal and Power Network Integrity Chandrakasen Chapter 7 (Logic Families) and Chapter 8 (Dynamic logic) Gronowski
More informationDDR4 memory interface: Solving PCB design challenges
DDR4 memory interface: Solving PCB design challenges Chang Fei Yee - July 23, 2014 Introduction DDR SDRAM technology has reached its 4th generation. The DDR4 SDRAM interface achieves a maximum data rate
More informationDEPARTMENT FOR CONTINUING EDUCATION
DEPARTMENT FOR CONTINUING EDUCATION Reduce EMI Emissions for FREE! by Bruce Archambeault, Ph.D. (reprinted with permission from Bruce Archambeault) Bruce Archambeault presents two courses during the University
More informationDESIGN TIP DT Managing Transients in Control IC Driven Power Stages 2. PARASITIC ELEMENTS OF THE BRIDGE CIRCUIT 1. CONTROL IC PRODUCT RANGE
DESIGN TIP DT 97-3 International Rectifier 233 Kansas Street, El Segundo, CA 90245 USA Managing Transients in Control IC Driven Power Stages Topics covered: By Chris Chey and John Parry Control IC Product
More informationHIGH-SPEED LOW-POWER ON-CHIP GLOBAL SIGNALING DESIGN OVERVIEW. Xi Chen, John Wilson, John Poulton, Rizwan Bashirullah, Tom Gray
HIGH-SPEED LOW-POWER ON-CHIP GLOBAL SIGNALING DESIGN OVERVIEW Xi Chen, John Wilson, John Poulton, Rizwan Bashirullah, Tom Gray Agenda Problems of On-chip Global Signaling Channel Design Considerations
More informationImpact of Low-Impedance Substrate on Power Supply Integrity
Impact of Low-Impedance Substrate on Power Supply Integrity Rajendran Panda and Savithri Sundareswaran Motorola, Austin David Blaauw University of Michigan, Ann Arbor Editor s note: Although it is tempting
More informationVLSI Design I; A. Milenkovic 1
CPE/EE 427, CPE 527 VLSI Design I L02: Design Metrics Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe527-03f
More informationHMC723LP3E HIGH SPEED LOGIC - SMT. 13 Gbps, FAST RISE TIME D-TYPE FLIP-FLOP w/ PROGRAMMABLE OUTPUT VOLTAGE. Typical Applications.
Typical Applications Features The HMC72LPE is ideal for: RF ATE Applications Broadband Test & Measurement Serial Data Transmission up to 1 Gbps Digital Logic Systems up to 1 GHz Functional Diagram Supports
More informationUnderstanding, measuring, and reducing output noise in DC/DC switching regulators
Understanding, measuring, and reducing output noise in DC/DC switching regulators Practical tips for output noise reduction Katelyn Wiggenhorn, Applications Engineer, Buck Switching Regulators Robert Blattner,
More informationEMI. Chris Herrick. Applications Engineer
Fundamentals of EMI Chris Herrick Ansoft Applications Engineer Three Basic Elements of EMC Conduction Coupling process EMI source Emission Space & Field Conductive Capacitive Inductive Radiative Low, Middle
More informationChapter 16 PCB Layout and Stackup
Chapter 16 PCB Layout and Stackup Electromagnetic Compatibility Engineering by Henry W. Ott Foreword The PCB represents the physical implementation of the schematic. The proper design and layout of a printed
More informationSINCE the performance of personal computers (PCs) has
334 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 57, NO. 5, MAY 2010 Multi-Slot Main Memory System for Post DDR3 Jaejun Lee, Sungho Lee, and Sangwook Nam, Member, IEEE Abstract This
More informationDevelopment and Validation of IC Models for EMC
Development and Validation of D. Beetner Missouri University University of Missouri of Science - Rolland Technology UMR EMC Laboratory 1 Who is the UMR/MS&T EMC Laboratory? People 5 professors 3 graduate
More informationNEW WIRELESS applications are emerging where
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 4, APRIL 2004 709 A Multiply-by-3 Coupled-Ring Oscillator for Low-Power Frequency Synthesis Shwetabh Verma, Member, IEEE, Junfeng Xu, and Thomas H. Lee,
More informationModeling the Effect of Wire Resistance in Deep Submicron Coupled Interconnects for Accurate Crosstalk Based Net Sorting
Modeling the Effect of Wire Resistance in Deep Submicron Coupled Interconnects for Accurate Crosstalk Based Net Sorting C. Guardiani, C. Forzan, B. Franzini, D. Pandini Adanced Research, Central R&D, DAIS,
More information