Chapter 16 PCB Layout and Stackup

Transcription

1 Chapter 16 PCB Layout and Stackup Electromagnetic Compatibility Engineering by Henry W. Ott

2 Foreword The PCB represents the physical implementation of the schematic. The proper design and layout of a printed circuit board can mean the difference between the product passing or failing EMC requirements. Such things as component placement, keep out zones, trace routing, number of layers, layer stackup (order of layers and layer spacing), and return path discontinuities all are critical to the EMC performance of the board. 2

3 General PCB Layout Considerations - Partitioning Components should be grouped into logical functional blocks. Some of these blocks might be: (1) high-speed logic, clocks, and clock drivers; (2) memory; (3) medium- and low-speed logic; (4) video; (5) audio and other low-frequency analog circuits; (6) input/output (I/O) drivers; and (7) I/O connectors and common-mode filters 3

4 General PCB Layout Considerations - Partitioning 4

5 General PCB Layout Considerations - Partitioning On a properly partitioned board, the high-speed logic as well as memory should not be located near the I/O area. The crystal or high-frequency oscillator should be located near the integrated circuits (ICs) that use them, and away from the I/O area of the board. The I/O drivers should be located close to the connectors. The video and low-frequency analog circuits should have access to the I/O area without having to pass through the high-frequency digital sections of the board. Proper partitioning will minimize trace lengths, improve signal quality, minimize parasitic coupling, and reduce both PCB emissions and susceptibility. 5

6 General PCB Layout Considerations Keep Out Zones Be particularly careful to keep the oscillators and/or crystals, as well as any other high-frequency circuitry, away from the I/O area. These circuits generate high-frequency fields (both electric and magnetic) that can easily couple directly to the I/O cables, connectors, and circuitry. Experience has shown, that if board size permits, keeping these circuits at least 0.5 in. (13 mm) from the I/O area will minimize the parasitic coupling. Route all critical signal traces away from the edges of the board to allow the return current to spread out under the trace. A good rule is to define a keep out zone, that is 20 times the signal-layer to return-plane spacing, around the periphery of the board. 6

7 General PCB Layout Considerations Keep Out Zones 7

8 General PCB Layout Considerations Critical Signals Experience has shown that 90% of PCB problems are caused by 10% of the circuitry. For emissions, the greatest problems are high-frequency (fast rise time) digital circuits with repetitive wave shapes, such as clocks, buses, and some control signals. These signals contain a multiplicity of large-amplitude, high-frequency harmonics. Clocks are usually the worst offenders, followed in order by buses and then repetitive control signals. An effective metric for categorizing signal speed (in A/s 2 ) is 8

9 General PCB Layout Considerations System Clocks Keep the clock traces as short as possible and provide for optimum placement by routing them first. Locate crystals, oscillators, or resonators as close to the circuits that use them as possible. Add a ground plane on the component side of the board under the crystal, oscillator, and/or clock driver. Connect this plane to the main ground plane with multiple vias. If the crystal or oscillator has a metal case, ground it to this componentside ground plane, and provide a provision for a board level shield over this area in case it should be needed. Small series damping resistors (or ferrite beads) should be added to all clock output traces with a frequency of 20 MHz or more. 9

10 General PCB Layout Considerations System Clocks This is recommended even on short clock traces, unless adding the resistor would increase the length of an already very short trace. A typical value resistor would be 33. Clock oscillators and drivers should also have ferrite beads in series with the V cc line to isolate the circuit from the main power distribution system. 10

11 PCB-to-Chassis Ground Connection A major source of radiation from electronic products is due to commonmode currents on the external cables. The internal circuit ground should be connected to the chassis at a point as close to the location that the cables terminate on the PCB as possible. The connection should be short, and there should be multiple connections to parallel the inductance of the connections, and, hence, decrease the radio frequency (rf) impedance. 11

12 Return Path Discontinuities One of the keys to determining the optimum printed circuit board layout is to understand how and where the signal return currents actually flow. The lowest impedance return path is in a plane directly underneath the signal trace. A plane is really two conductors. Major EMC, and signal integrity (SI), problems occur when there are discontinuities in the return current path. These discontinuities cause the return current to flow in large loops, which increases the ground inductance and the radiation from the board as well as increasing the crosstalk between adjacent traces and causing waveform distortion. 12

13 Return Path Discontinuities In addition, a return plane discontinuity on a constant impedance PCB will change the characteristic impedance of the trace and produce reflections. The three most common return path discontinuities: Slots or splits in the power and/or ground plane Signal traces changing layers, which causes the return currents to change reference planes Ground plane cutouts around connectors, or under ICs Slots in Ground/Power Planes If you must have slots, make sure that no traces cross over them on adjacent layers. 13

14 Return Path Discontinuities Slots in Ground/Power Planes Ground plane slots and/or splits can increase the PCB radiation in excess of 20 db. Fig (B) Holes in ground plane. 14

15 Return Path Discontinuities Split Ground/Power Planes This much larger return current path significantly increases the inductance, and loop area, of the return path. If in the above example, both the power and ground planes are split, then how will the return current get across the gap? The best solution to the split plane problem is to avoid crossing the split with any signal traces, especially critical signal traces. The signal should have been routed on the bottom signal layer adjacent to the solid ground plane. 15

16 Return Path Discontinuities Split Ground/Power Planes Many products today require multiple direct current (dc) voltages to operate. As a result, split power planes are becoming a common occurrence. Five approaches are available for dealing with the problem created by split power planes. Split the power plane and live with the routing restrictions. Use a separate solid power plane for each dc voltage. Use a power island for one or more of the voltages. A power island is a small isolated power plane on a signal layer (usually on the top or bottom layer of the board) under one or more ICs. Route some (or all) of the dc voltages as a trace on a signal layer. As a last resort, add stitching capacitors where the trace crosses the split plane. The power island approach is most useful when a dc voltage is used only by one or more ICs located adjacent to each other. 16

17 Return Path Discontinuities Split Ground/Power Planes Although signal traces should not be run across a split in an adjacent plane, design constraints, and cost considerations, sometimes make it necessary to do so, especially in the case of power planes. The capacitors should be located within 0.1 in. of the trace and have a value of to 0.01 F according to the frequency of the signal. 17

18 Return Path Discontinuities Split Ground/Power Planes This solution is far from a ideal; the return current must now flow through a via, a trace, a mounting pad, a capacitor, a mounting pad, a trace, and finally a via to the other section of the split plane. This adds about 5 nh, or more, of additional inductance (impedance) in the ground return path, but it is better than the alternative of doing nothing. 18

19 Return Path Discontinuities Changing Reference Planes The interplane capacitance is not large enough to provide a low impedance path, so the return current will have to flow through the nearest decoupling capacitor, or plane-to-plane via to change planes. 19

20 Return Path Discontinuities Changing Reference Planes Changing reference planes effectively adds impedance (inductance) in the return path. One solution to this problem is to avoid switching reference planes for critical signals (such as clocks), if at all possible. 20

21 Return Path Discontinuities Changing Reference Planes If you must switch references from a power plane to a ground plane, then you can place an additional decoupling capacitor* adjacent to the signal via to provide a high-frequency current return path between the two planes. This solution is not ideal, however, because this adds considerable additional inductance in the return path (typically about 5 nh). Note that if the two reference planes are of the same type (either both power or both ground), then you can use a plane-to-plane via (groundto-ground, or power-to-power) instead of a capacitor immediately adjacent to the signal via. 21

22 Return Path Discontinuities Changing Reference Planes 22

23 Return Path Discontinuities Referencing the Top and Bottom of the Same Plane To drop a signal via through a plane, a clearance hole (anti-pad) must be provided in the plane; otherwise the signal would be shorted to the reference plane. The inside surface of the clearance hole provides a surface connecting the top and bottom of the plane and provides the path for the return current to flow from the top to the bottom of the plane as depicted in Fig

24 Return Path Discontinuities Referencing the Top and Bottom of the Same Plane High-speed clocks and other critical signals should be routed (in order of preference) as follows: On only one layer adjacent to a plane. On two layers that are adjacent to the same plane. On two layers adjacent to two separate planes of the same type (ground or power) and connect the planes together with plane to plane vias wherever the signal trace changes layers. On two layers adjacent to two separate planes of different types (ground and power) and connect the planes together with capacitors whenever the signal trace changes layers, and hence reference planes. On more than two layers. Preferably this should not be used at all. 24

25 Return Path Discontinuities Connectors 25

26 Return Path Discontinuities Ground Fill Ground fill, or ground pour, is a technique where copper is introduced into areas of the PCB signal layers that contain no traces. The intent is to reduce emissions and susceptibility by reducing field fringing from the signal traces and by providing some degree of shielding on the board. To be effective, the fill must be connected to the existing ground structure on the board at many places. If not properly grounded, the copper fill can actually increase emissions and susceptibility, as well as crosstalk between traces. Copper fill, not properly grounded, can also create an ESD problem. Although often used with analog circuits on double-sided boards, copper fill is not recommended for high-speed digital circuits, because it can cause impedance discontinuities, which can lead to possible functional problems. 26

27 Return Path Discontinuities Ground Fill On multilayer boards, the ground fill, if used, must be connected to the PCB ground plane at multiple points. If ground fill is used on multilayer boards, it should only be applied to the surface layers. 27