Impedance Matching to 50Ω

Transcription

1 Impedance Matching to 50Ω The figure above shows the output matching circuit as implemented on the TRF7960EVM on a simulated Smith chart plot going from the nominal 4 Ohm TX_OUT (Pin 5) to near 50 Ohms output impedance. This plot was specifically generated to serve as an example of what each part of the circuit is doing for the total impedance transformation required. It can be noted that the last shunt capacitance value (theoretically) should have been 250pF (a difference of 63pF) to achieve 50 Ohms on this plot; however the actual value that was found to achieve the 50 Ohms match on the TRF7960EVM board is shown in the reference schematics. It is possible that a system integrator will find that slight variations around the values in the reference design may work better for them; hence the reference should be used as a very good starting point for a production design and the system integrator should absolutely take the extra test and validation steps with their own version of this design to ensure best performance.

2 For Section Layout Considerations Keep all decoupling caps as close to the IC as possible with the high frequency decoupling caps (10 nf) closer than the low frequency decoupling capacitors (2.2 μf). Place ground vias as close to the ground side of the capacitors and reader IC pins to minimize any possible ground loops. Place ground vias as close to the ground side of the capacitors and reader IC pins to minimize any possible ground loops. It is not recommend to use any inductor sizes below 0603 as the output power can be compromised. If smaller sized inductors are absolutely necessary, it is up to the customer to confirm output performance. If the crystal is changed from an HC49 to another crystal type the designer should pay close attention to the internal load capacitance and adjust the two external shunt capacitors accordingly. It is recommended that the designer follow the recommendations of the crystal manufacturer for those values. There should be a common ground plane for the digital and analog sections.the multiple ground sections or islands should have vias that tie the different sections of the planes together. Ensure that the PowerPAD, at the center of the reader IC, is properly laid out. This will help to dissipate the heat away from the IC. The PowerPAD is electrically isolated on the IC. Thus, it could be tied to either a power or ground plane to help dissipate any heat from the package. The suggested layout guidelines for the IC (PCB layout, stencil & vias) are available here: Trace line lengths should be minimized whenever possible. Especially, the RF output path, crystal connections and control lines from the reader to the microprocessor. Proper placement of the reader, microprocessor, crystal and RF connection/connector will help facilitate this. Avoid crossing of digital lines under RF signal lines. Also, avoid crossing of digital lines with other digital lines whenever possible. If the crossings are unavoidable, 90 crossings should be used to minimize coupling of the lines. Depending on the production test plan, the designer should consider possible implementations of test pads and/or test vias for use during testing. The necessary pads/vias should be placed in accordance with the proposed test plan to help enable easy access to those test points. If the system implementation is complex (i.e. RFID reader module is a subsystem of a greater system with other modules (Bluetooth, WiFi, microprocessors and clocks), special considerations should be taken to ensure that there is not any noise coupling into the supply lines. If needed, special filtering/regulator considerations should be used to minimize or eliminate noise in these unique systems. This will ensure optimal RFID reader performance. A suggested reference schematic with the output match from 4 Ω to 50 Ω is provided in this data sheet (SLOU186) and also the EVM document (SLOU193). If the customer chooses to follow this suggested schematic, the following conditions should be verified as each implementation will be slightly different. Verify the TX output power (i.e. +23dBm, when operating +5VDC, full power out system) If the desired output is detected, then the component and system matches the EVM reference. If not detected, then the component value(s) or quality is incorrect. Verify the output impedance, if 50 Ω, then the match is correct and maximum power transfer will be achieved. If not 50 Ω, then it will require some tuning of the output to obtain a 50 Ω output match. Once this is achieved, you will achieve maximum power transfer. For Section 4.4.7

3 Test Point Results in the Output Matching Circuit After system development, and during testing of the first prototypes, the integrator should observe the following waveforms as they go through the circuit from the TX_OUT pin to the 50 Ohm Output, which will connect to the tuned antenna circuit (also at 50 Ohms). TRF796x TX_OUT (PIN 5) IN BETWEEN DC BLOCK CAPS AND L1 IN BETWEEN L1 AND L2

4 TRF796x RX1_IN1 and RX2_IN2 (pin 8 = blue & pin 9 = red) 50Ω Impedance Match Point (J3 RF Test Port)

5 Antenna Coil Signal