The number of layers The number and types of planes (power and/or ground) The ordering or sequence of the layers The spacing between the layers

Transcription

1 PCB Layer Stackup PCB layer stackup (the ordering of the layers and the layer spacing) is an important factor in determining the EMC performance of a product. The following four factors are important with respect to board stackup: The number of layers The number and types of planes (power and/or ground) The ordering or sequence of the layers The spacing between the layers In deciding on the number of layers, the following should be considered: The number of signals to be routed and PCB cost. Clock frequency. Will the product have to meet Class A or Class B emission requirements? Will the PCB be in a shielded or unshielded enclosure? The EMC engineering expertise of the design team. JHLin, AppEMC; PCB Layout & Stackup 28

2 PCB Layer Stackup One- and Two-Layer Boards These boards are selected primarily for cost considerations, not for EMC performance. One- or two-layer boards should only be considered when clock frequencies are less than 10 MHz. On one- or two-layer boards all critical signals should be routed first. Critical signals should be routed as short as possible, with an adjacent ground return trace. Clocks and buses should have a ground return trace on both sides of the signal traces or bus. Small damping resistors ( 33 ) should be placed in all clock outputs to reduce ringing. A small ground plane should be placed under the crystal or oscillator, and the crystal or oscillator case should be connected to it. JHLin, AppEMC; PCB Layout & Stackup 29

3 PCB Layer Stackup One- and Two-Layer Boards On one- or two-layer boards, crystals are usually preferred to oscillators because they have much less harmonic energy. On two-layer digital boards, the ground and power should be routed so as to form a grid. Decouple the V cc on all clocked ICs by adding a small ferrite bead in series with the V cc line, which is located on the power supply side of the decoupling capacitor(s). Consider dithering the clock. Also use a minimum of two decoupling capacitors per IC (four capacitors on square packages); locate them on opposite sides of the IC. One final method of reducing emissions on single- or double-sided boards is with the use of an image plane JHLin, AppEMC; PCB Layout & Stackup 30

4 PCB Layer Stackup One- and Two-Layer Boards The two most important things that must be done to minimize emissions and susceptibility on two-layer boards are as follows: To keep the loop area of critical signals (clocks, etc.) small To grid the ground and power structures JHLin, AppEMC; PCB Layout & Stackup 31

5 PCB Layer Stackup Multilayer Boards A often used rule of thumb is that a four-layer board will produce 20 db or more, less radiation than a two-layer board all other factors being equal. Boards containing planes are much better than those without planes for the following reasons: The planes allow signals to be routed in a microstrip (or stripline) configuration. When the return current is on the adjacent plane, the loop area is reduced. The ground plane significantly decreases the ground impedance and hence the ground noise. Above about 10 MHz, multilayer boards should normally be seriously considered. JHLin, AppEMC; PCB Layout & Stackup 32

6 PCB Layer Stackup Multilayer Board Objectives When using multilayer boards, six design objectives should be kept in mind, as follows: 1. A signal layer should always be adjacent to a plane. 2. Signal layers should be tightly coupled (close) to their adjacent planes. 3. Power and ground planes should be closely coupled together.* 4. High-speed signals should be routed on buried layers located between planes. 5. Multiple-ground planes are very advantageous, because they will lower the ground (reference plane) impedance of the board and reduce the common-mode radiation. 6. When critical signals are routed on more than one layer, they should be confined to two layers adjacent to the same plane. Most PCB designs cannot meet all six objectives, so a compromise is required. An eight-layer PCB is the fewest number of layers that can be used to achieve five of the six above objectives. JHLin, AppEMC; PCB Layout & Stackup 33

7 PCB Layer Stackup Multilayer Board Objectives Another desirable objective, from a mechanical point of view, is to have the cross section of the board symmetrical (or balanced) to prevent warping. JHLin, AppEMC; PCB Layout & Stackup 34

8 PCB Layer Stackup Four-Layer Boards JHLin, AppEMC; PCB Layout & Stackup 35

9 PCB Layer Stackup Four-Layer Boards Three advantages for Fig : 1. Signal loop areas are smaller and therefore produce less differential-mode radiation. 2. Tight coupling between the signal trace and the ground plane reduces the ground plane impedance (inductance), hence reducing the common-mode radiation from the cables connected to the board. 3. Close trace-to-plane coupling will decrease the crosstalk between adjacent traces. For a fixed trace-to-trace spacing, the crosstalk is proportional to the square of the trace height. Advantage: the planes on the outer layers provide shielding to the signal traces on the inner layers. Disadvantage: the ground plane may be cut up considerably with component mounting pads on a high-density PCB. This can be alleviated somewhat, by reversing the planes 36

10 PCB Layer Stackup Four-Layer Boards Second, some designers do not like to have an exposed power plane. Third, the buried signal layers make board rework difficult if not impossible. The power should be routed as a grid, using wide traces, on the signal layers. Two added advantages: 1. the two ground planes produce a much lower ground impedance 2. the two ground planes can be stitched together around the periphery of the board to enclose all the signal traces in a Faraday cage. JHLin, AppEMC; PCB Layout & Stackup 37

11 PCB Layer Stackup Four-Layer Boards A fourth possibility This stackup overcomes the rework problem. It still provides for the low ground impedance as a result of the two ground planes. The planes, however, do not provide any shielding. The configurations of Figs , 16-14B, and all can perform well EMC wise. JHLin, AppEMC; PCB Layout & Stackup 38

12 PCB Layer Stackup Six-Layer Boards Most six-layer boards consist of four signal routing layers and two planes. From an EMC perspective, a six-layer board is preferred over a four-layer board because it is easy to shield high-frequency signals by placing them on buried layers between planes, or to provide for orthogonally routed signal layers that are referenced to the same plane. 39

13 PCB Layer Stackup Six-Layer Boards The only time this arrangement works even moderately well is if all the high-frequency signals are routed on layers 2 and 5 and only lowfrequency signals, or better yet no signals at all (just mounting pads and test points), are located on layers 1 and 6. JHLin, AppEMC; PCB Layout & Stackup 40

14 PCB Layer Stackup Six-Layer Boards Its main drawback, and not a serious one, is the separation of the power and ground planes. In many cases Fig can provide better EMC performance than the stackup of Fig JHLin, AppEMC; PCB Layout & Stackup 41

15 PCB Layer Stackup Six-Layer Boards This configuration has the advantage that orthogonal routed signals always reference the same plane. The disadvantage is that the signals on layers one and six are not shielded. Typical layer spacing for this board might be in/0.005 in/0.040 in/0.005 in/0.005 in. Figure would often be preferred if the product was in an unshielded enclosure (because the high-frequency signal traces are shielded by the outer planes), whereas the configuration of Fig might be preferred if the product were in a shielded enclosure. JHLin, AppEMC; PCB Layout & Stackup 42

16 PCB Layer Stackup Eight-Layer Boards An eight-layer board can be used to add two more routing layers or to improve EMC performance by adding two more planes. Most eight-layer boards (and all the ones that we will concentrate on here) consist of four signal-routing layers and four planes. An eight-layer board can be thought of as a six-layer board with optimized EMC performance. 43

17 PCB Layer Stackup Eight-Layer Boards For best EMC performance and signal integrity, when critical highfrequency signals change layers (e.g., from layer 4 to 5 in the case of Fig ) a ground-to-ground via should be added between the two ground planes near the signal via. The stackup in Fig can be further improved by using some form of embedded PCB capacitance technology. If a design requires two dc voltages (e.g., 5 V and 3.3 V), the stackup of Fig should be considered. 44

18 PCB Layer Stackup Eight-Layer Boards Typical layer spacing for this configuration might be in/0.005 in/0.005 in/0.020 in/0.005 in/0.005 in/0.010 in. An even better layer spacing for the stackup of Fig would be in/0.005 in/0.005 in/0.010 in/0.005 in/0.005 in/0.015 in. JHLin, AppEMC; PCB Layout & Stackup 45

19 PCB Layer Stackup Eight-Layer Boards This is an excellent performing configuration with good signal integrity and is often preferred over the stackup of Fig because of the tightly coupled power/ground planes. The stackup in Fig can be improved even more by using some form of embedded PCB capacitance technology for layers 4 5 to improve the high-frequency decoupling. For high-frequency signals (with harmonics above 500 MHz) on a board in a shielded enclosure, the stackup of Fig would usually be preferred. For lower frequency and/or a product in an unshielded enclosure, the stackup of Fig might be preferred because it provides shielding for the signal layers. JHLin, AppEMC; PCB Layout & Stackup 46

20 PCB Layer Stackup Eight-Layer Boards There is very little EMC advantage to using a board with more than eight layers. More than eight layers are usually only used when additional signal routing layers are required. JHLin, AppEMC; PCB Layout & Stackup 47

21 PCB Layer Stackup Ten-Layer Boards Ten-layer boards usually have six signal layers and four planes. Having more than six signal layers on a 10-layer board is not recommended. High layer count boards (10 plus) require thin dielectrics (typically in or less on a in thick board) and therefore they automatically have tight coupling between all adjacent layers. 48

22 PCB Layer Stackup Ten-Layer Boards The signals on layers 3 and 4 are isolated (shielded) from the signals on layers 7 and 8 by the center power/ground plane pair. For example, high-speed clocks might be routed on one of these pairs, and high-speed address and data buses routed on the other pair. Another possibility for routing orthogonal signals on the 10- layer board shown in Fig is to pair layers 1 and 3, layers 4 and 7, and layers 8 and 10. JHLin, AppEMC; PCB Layout & Stackup 49

23 PCB Layer Stackup Ten-Layer Boards The stackup of Fig is very desirable if you have few low-speed signals to put on the outer signal layers (as in Fig ) and most of your signals are high speed. One consideration with this stackup relates to how badly the outside ground planes will be cut up by the component mounting pads and vias on a highdensity PCB. JHLin, AppEMC; PCB Layout & Stackup 50

24 PCB Layer Stackup Ten-Layer Boards The stackup in Fig can be improved even more by replacing layers 2 and 9 each with a pair of embedded PCB capacitance layers (thereby satisfying objective #3). This, however, effectively converts it to a 12-layer board. The stackup in Fig can be improved with the use of some form of embedded PCB capacitance technology for layers 5 and 6. JHLin, AppEMC; PCB Layout & Stackup 51

25 PCB Layer Stackup Twelve and More Layer Boards JHLin, AppEMC; PCB Layout & Stackup 52

26 PCB Layer Stackup Twelve and More Layer Boards JHLin, AppEMC; PCB Layout & Stackup 53

27 PCB Layer Stackup Basic Multilayer PCB Structures Although contrary to popular practice, I believe that significant evidence exists to show that for high-frequency circuitry, good EMC performance, and signal integrity, routing critical signals on layers that are adjacent to the same plane should take precedence over shielding critical signal layers by burying them between planes. The basic stackup should consist of multiples of the two basic structures that contain two signal layers adjacent to a plane (signal-plane-signal) as shown in Fig A as well as adjacent power and ground plane pairs as shown in Fig B. These two structures can then be combined in multiple ways to form PCBs with six or more layers. JHLin, AppEMC; PCB Layout & Stackup 54

28 PCB Layer Stackup Basic Multilayer PCB Structures Adding the basic building block from Fig B to the center of the board shown in Fig produces a 14-layer board that meets all the design objectives. 55

29 General PCB Design Procedure The following factors are also important in determining the EMC performance of the board: The layer spacing The assigning of signal layer pairs for orthogonal routing of signals The assignment of signals (clock, bus, high speed, low frequency, etc.) to which signal-routing-layer pairs JHLin, AppEMC; PCB Layout & Stackup 56

30 General PCB Design Procedure This discussion on board stackup has assumed a standard in-thick board, with symmetrical cross section, an even number of layers, and conventional via technology. If blind, buried, micro-vias, nonsymmetrical boards, or odd number layer count boards are considered, other factors come into play and additional board stackups not only become possible but also desirable in many cases. The following represents the general steps required in creating a PCB stackup: Determine the number of signal routing layers required Determine how to handle multiple dc voltages Determine the number of power planes required for the various system voltages Determine whether multiple voltages will be on the same power plane layer, thereby requiring a split-plane, and routing restrictions on the adjacent layers JHLin, AppEMC; PCB Layout & Stackup 57

31 General PCB Design Procedure Assign each signal layer pair to a solid reference plane as shown in Fig A Pair power and ground planes as shown in Fig B Determine the ordering of the layers Determine the spacing between layers Define any necessary routing restrictions All the stackups discussed, with the exception of Fig , will provide good-to-excellent EMC performance. The avoiding of current return path discontinuities is probably the most important, and often overlooked, principle involved in good PCB design. JHLin, AppEMC; PCB Layout & Stackup 58