VLSI Design I; A. Milenkovic 1

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1 CPE/EE 427, CPE 527 VLSI Design I L02: Design Metrics Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( ) [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] Major Design Challenges Microscopic issues ultra-high speeds power dissipation and supply rail drop growing importance of interconnect noise, crosstalk reliability, manufacturability clock distribution Macroscopic issues time-to-market design complexity (millions of gates) high levels of abstractions design for test reuse and IP, portability systems on a chip (SoC) tool interoperability Year Tech. Complexity Frequency 3 Yr. Design Staff Size Staff Costs M Tr. 400 MHz 210 $90 M M Tr. 500 MHz 270 $120 M M Tr. 600 MHz 360 $160 M M Tr. 800 MHz 800 $360 M 8/27/2003 VLSI Design I; A. Milenkovic 2 Overview of Last Lecture Digital integrated circuits experience exponential growth in complexity (Moore s law) and performance Design in the deep submicron (DSM) era creates new challenges Devices become somewhat different Global clocking becomes more challenging Interconnect effects play a more significant role Power dissipation may be thelimiting factor Our goal in this class will be to understand and design digital integrated circuits in the deep submicron era Today we look at some basic design metrics 8/27/2003 VLSI Design I; A. Milenkovic 3 VLSI Design I; A. Milenkovic 1

2 Fundamental Design Metrics Functionality Cost NRE (fixed) costs - design effort RE (variable) costs - cost of parts, assembly, test Reliability, robustness Noise margins Noise immunity Performance Speed (delay) Power consumption; energy Time-to-market 8/27/2003 VLSI Design I; A. Milenkovic 4 Cost of Integrated Circuits NRE (non-recurring engineering) costs Fixed cost to produce the design design effort design verification effort mask generation Influenced by the design complexity and designer productivity More pronounced for small volume products Recurring costs proportional to product volume silicon processing also proportional to chip area assembly (packaging) test Fixedcost Cost per IC= Variable cost per IC+ Volume 8/27/2003 VLSI Design I; A. Milenkovic 5 NRE Cost is Increasing 8/27/2003 VLSI Design I; A. Milenkovic 6 VLSI Design I; A. Milenkovic 2

3 Cost per Transistor cost: -per-transistor Fabrication capital cost per transistor (Moore s law) /27/2003 VLSI Design I; A. Milenkovic 7 Silicon Wafer Single die Wafer From Going up to 12 (30cm) 8/27/2003 VLSI Design I; A. Milenkovic 8 Recurring Costs Variable cost Cost of Die cost + Testing cost + Packaging cost = Final test yield Cost of wafer die = Dies per wafer Die yield 8/27/2003 VLSI Design I; A. Milenkovic 9 VLSI Design I; A. Milenkovic 3

4 Dies per Wafer p (Wafer diameter/2) Dies per wafer = Die area 2 p Wafer diameter 2 Die area 8/27/2003 VLSI Design I; A. Milenkovic 10 Yield Defects per unit area Die area Die yield = Wafer yield 1+ a α is approximately 3 diecost = f (diearea) 4 a 8/27/2003 VLSI Design I; A. Milenkovic 11 Chip 386DX 486DX2 PowerPC 601 HP PA 7100 DEC Alpha Super SPARC Pentium Examples of Cost Metrics (1994) Metal layers Line width Wafer cost $900 $1200 $1700 $1300 $1500 $1700 $1500 Defects Area /cm 2 (mm 2 ) Dies/ wafer Yield 71% 54% 28% 27% 19% 13% 9% Die cost $4 $12 $53 $73 $149 $272 $417 8/27/2003 VLSI Design I; A. Milenkovic 12 VLSI Design I; A. Milenkovic 4

5 Yield Example Example #2: 20-cm wafer for a die that is 1.5 cm on a side. Solution: Die area = 1.5x1.5 = 2.25cm2. Dies per wafer = 3.14x(20/2)2/ x20/(2x2.5)0.5=110. Example #1 wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2, α = 3 (measure of manufacturing process complexity) 252 dies/wafer (remember, wafers round & dies square) die yield of 16% 252 x 16% = only 40 dies/wafer die yield! Die cost is strong function of die area proportional to the third or fourth power of the die area 8/27/2003 VLSI Design I; A. Milenkovic 13 Functionality and Robustness Prime requirement IC performs the function it is designed for Normal behavior deviates due to variations in the manufacturing process (dimensions and device parameters vary between runs and even on a single wafer or die) presence of disturbing on- or off-chip noisesources Noise: Unwanted variation of voltages or currents at the logic nodes 8/27/2003 VLSI Design I; A. Milenkovic 14 Reliability? Noise in Digital Integrated Circuits i(t) v(t) V DD Inductive coupling Capacitive coupling Power and ground noise from two wires placed side by side from noise on the power inductive coupling and ground supply rails current change on one wire can can influence signal levels influence signal on the neighboring wire in the gate capacitive coupling voltage change on one wire can influence signal on the neighboring wire cross talk 8/27/2003 VLSI Design I; A. Milenkovic 15 VLSI Design I; A. Milenkovic 5

6 Example of Capacitive Coupling Signal wire glitches as large as 80% of the supply voltage will be common due to crosstalk between neighboring wires as feature sizes continue to scale Crosstalk vs. Technology Pulsed Signal 0.12m CMOS 0.16m CMOS Black line quiet Red lines pulsed Glitches strength vs technology 0.25m CMOS 0.35m CMOS From Dunlop, Lucent, /27/2003 VLSI Design I; A. Milenkovic 16 Static Gate Behavior Steady -state parameters of a gate static behavior tell how robust a circuit is with respect to both variations in the manufacturing process and to noise disturbances. Digital circuits perform operations on Boolean variables x {0,1} A logical variable is associated with a nominal voltage level for each logic state 1 V OH and 0 V OL V(x) V(y) V OH =! (V OL ) V OL =! (V OH ) Difference between V OH and V OL is the logic or signal swing V sw 8/27/2003 VLSI Design I; A. Milenkovic 17 DC Operation Voltage Transfer Characteristic V(y) V OH = f (V IL ) f V(x) V(y) V OH = f(v OL ) V OL = f(v OH ) V M = f(v M ) V(y)=V(x) V M Switching Threshold V OL = f (V IH ) V IL V IH V(x) 8/27/2003 VLSI Design I; A. Milenkovic 18 VLSI Design I; A. Milenkovic 6

7 Mapping between analog and digital signals The regions of acceptable high and low voltages are delimited by VIH and VIL that represent the points on the VTC curve where the gain = -1 (dvout/dvin) 1 V OH V out V OH Slope = -1 V IH Undefined Region V IL Slope = -1 0 V OL V OL V IL V IH V in 8/27/2003 VLSI Design I; A. Milenkovic 19 Definition of Noise Margins For robust circuits, want the 0 and 1 intervals to be as large as possible V DD V DD V OH Noise Margin High Noise Margin Low V OL Gnd Gnd Gate Output NM H = V OH - V IH NM L = V IL - V OL Gate Input "1" V IH Undefined Region V IL "0" Gnd Large noise margins are desirable, but not sufficient 8/27/2003 VLSI Design I; A. Milenkovic 20 The Regenerative Property A gate with regenerative property ensure that a disturbed signal converges back to a nominal voltage level v 0 v 1 v 2 v 3 v 4 v 5 v 6 5 v 2 V (volts) 3 1 v 0 v t (nsec) 8/27/2003 VLSI Design I; A. Milenkovic 21 VLSI Design I; A. Milenkovic 7

8 Conditions for Regeneration v 0 v 1 v 2 v 3 v 4 v 5 v 6 v 1 = f(v 0 ) v 1 = finv(v 2 ) v 3 f(v) finv(v) v 1 v 1 finv(v) v 3 f(v) v 2 v 0 v 0 v 2 Regenerative Gate Nonregenerative Gate To be regenerative, the VTC must have a transient region with a gain greater than 1 (in absolute value) bordered by two valid zones where the gain is smaller than 1. Such a gate has two stable operating points. 8/27/2003 VLSI Design I; A. Milenkovic 22 Noise Immunity Noise margin expresses the ability of a circuit to overpower a noise source noise sources: supply noise, cross talk, interference, offset Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity expresses the ability of the system to process and transmit information correctly in the presence of noise For good noise immunity, the signal swing (i.e., the difference between V OH and V OL ) and the noise margin have to be large enough to overpower the impact of fixed sources of noise 8/27/2003 VLSI Design I; A. Milenkovic 23 Directivity A gate must be undirectional: changes in an output level should not appear at any unchanging input of the same circuit In real circuits full directivity is an illusion (e.g., due to capacitive coupling between inputs and outputs) Key metrics: output impedance of the driver and input impedance of the receiver ideally, the output impedance of the driver should be zero input impedance of the receiver should be infinity 8/27/2003 VLSI Design I; A. Milenkovic 24 VLSI Design I; A. Milenkovic 8

9 (V) V out Fan-In and Fan-Out Fan-out number of load gates connected to the output of the driving gate gates with large fan-out are slower N Fan-in the number of inputs to the gate gates with large fan-in are bigger and slower M 8/27/2003 VLSI Design I; A. Milenkovic 25 The Ideal Inverter The ideal gate should have infinite gain in the transition region a gate threshold located in the middle of the logic swing high and low noise margins equal to half the swing input and output impedances of infinity and zero, resp. V out R i = R o = 0 g = - Fanout = NM H = NM L = VDD/2 8/27/2003 VLSI Design I; A. Milenkovic 26 V in 5.0 An Old-time Inverter 4.0 NM L V M 1.0 NM H V in (V) 8/27/2003 VLSI Design I; A. Milenkovic 27 VLSI Design I; A. Milenkovic 9

10 Delay Definitions V in V out input waveform V in Propagation delay? t V out output waveform signal slopes? t 8/27/2003 VLSI Design I; A. Milenkovic 28 Delay Definitions V in V out input waveform V in 50% Propagation delay t p = (t phl + t plh )/2 t phl t plh t V out output waveform 50% 90% signal slopes t f 10% t r t 8/27/2003 VLSI Design I; A. Milenkovic 29 Ring Oscillator v 0 v 1 v 2 v 3 v 4 v 5 v 0 v1 v5 T = 2 t p N 8/27/2003 VLSI Design I; A. Milenkovic 30 VLSI Design I; A. Milenkovic 10

11 Modeling Propagation Delay Model circuit as first-order RC network R v out v out (t) = (1 e t/τ )V where τ = RC v in C Time to reach 50% point is t = ln(2) τ = 0.69 τ Time to reach 90% point is t = ln(9) τ = 2.2 τ Matches the delay of an inverter gate 8/27/2003 VLSI Design I; A. Milenkovic 31 Power and Energy Dissipation Power consumption: how much energy is consumed per operation and how much heat the circuit dissipates supply line sizing (determined by peak power) P peak = V dd i peak battery lifetime (determined by average power dissipation) p(t) = v(t)i(t) = V dd i(t) P avg = 1/T p(t) dt = V dd /T i dd (t) dt packaging and cooling requirements Two important components: static and dynamic E (joules) = C L V dd 2 P t sc V dd I peak P V dd I leakage f 0 1 = P 0 1 * f clock P (watts) = C L V dd 2 f t sc V dd I peak f V dd I leakage 8/27/2003 VLSI Design I; A. Milenkovic 32 Power and Energy Dissipation Propagation delay and the power consumption of a gate are related Propagation delay is (mostly) determined by the speed at which a given amount of energy can be stored on the gate capacitors the faster the energy transfer (higher power dissipation) the faster the gate For a given technology and gate topology, the product of the power consumption and the propagation delay is a constant Power-delay product (PDP) energy consumed by the gate per switching event An ideal gate is one that is fast and consumes little energy, so the ultimate quality metric is Energy-delay product (EDP) = power-delay 2 8/27/2003 VLSI Design I; A. Milenkovic 33 VLSI Design I; A. Milenkovic 11

12 Summary Digital integrated circuits have come a long way and still have quite some potential left for the coming decades Some interesting challenges ahead Getting a clear perspective on the challenges and potential solutions is the purpose of this course Understanding the design metrics that govern digital design is crucial Cost, reliability, speed, power and energy dissipation 8/27/2003 VLSI Design I; A. Milenkovic 34 VLSI Design I; A. Milenkovic 12