EEC 216 Lecture #10: Ultra Low Voltage and Subthreshold Circuit Design. Rajeevan Amirtharajah University of California, Davis
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1 EEC 216 Lecture #1: Ultra Low Voltage and Subthreshold Circuit Design Rajeevan Amirtharajah University of California, Davis
2 Opportunities for Ultra Low Voltage Battery Operated and Mobile Systems Wireless sensors RFID tags Biomedical implants Mobile Phones, internet devices, and netbooks Maximize operating lifetime for stored energy (minimum energy operation) Wall-plug and Rack Mounted Systems Power-down and sleep modes in servers Maintain state in on-chip caches, SRAM memory while minimizing leakage power Moteiv Sky mote, 26 R. Amirtharajah, EEC216 Winter 29 4
3 Delay: TOT CMOS Delay and Power Dissipation Total Power: CΔV Δt = = I P + P + = Pdynamic + Pshort circuit = αc + V dd L V I 2 dd static f + V + V CLV I dd dd I peak leak static tr + t 2 R. Amirtharajah, EEC216 Winter 29 5 P leak Voltage scaling decreases all power components, at expense of increasing circuit delay. D I dd μc f C W L f L V dd ( V V ) 2 ox dd th 2
4 Low Voltage CMOS Inverter Operation Thermal noise limit: 4kT q 1 mv Inverter gain limit: 8kT q 2 mv Equalized NMOS- PMOS off currents: Swanson and Meindl, JSSC nkT q 57 mv R. Amirtharajah, EEC216 Winter 29 6
5 Supply Voltage Scaling With Technology Node VDD (V.6.4 VDD (High Perf.) 15 1 Length (nm.2 VDD (Low Power) MPU Physical Gate Length From 27 ITRS Roadmap Year R. Amirtharajah, EEC216 Winter 29 7
6 Commercial Wireless Sensor Mote Moteiv Sky mote, 26 Jiang, IPSN/SPOTS 25 Current sensor node: 7 mw all active, 17 μw idle Power sources contribute significant volume and cost Smaller system (1 cm 3 ) desirable (less obtrusive military sensor, implantable biomedical device) Reduce power consumption, get energy from environment R. Amirtharajah, EEC216 Winter 29 8
7 Specific Opportunities for ULV Design Extremely low power mixed-signal circuits Analog design without operational amplifiers Low voltage swing on-chip interconnects Good current drive at low V DD desirable Power gates and cutoff devices to minimize leakage power during inactive state Need steep subthreshold slope to limit leakage current when blocks turned off Low voltage active mode and sleep mode memories, caches Need reliable operation under variable V DD Low voltage standard cells Operate at minimum energy point, balancing leakage and dynamic power R. Amirtharajah, EEC216 Winter 29 9
8 Extremely Brief MOSFET Review Saturation: I D μc 2 W L ( ) 2 V V ( + λv ) ox = GS T 1 DS Triode: Subthreshold: I = μc D ox W L ( ) DS V 2 GS VT VDS Classical MOSFET model, will discuss deep submicron modifications as necessary R. Amirtharajah, EEC216 Winter 29 1 VGS nkt q I = D I Se 1 e V DS kt q V 2
9 Subthreshold Current Equation I D = I S e V n GS kt q 1 ( 1+ λv ) R. Amirtharajah, EEC216 Winter e V DS kt q I s and n are empirical parameters Typically, often ranging around Usually want small subthreshold leakage for digital designs Define quality metric: inverse of rate of decline of current wrt V GS below V T Subthreshold slope factor S: DS n 1 n 1. 5 kt S = n q ln( 1)
10 I D = Detailed Subthreshold Current Equation ( ) qvds V V γv + V 1 exp q Aexp GS T S η nkt V T = zero bias threshold voltage, μ = zero bias mobility Cox = gate oxide capacitance per unit area γ = linear body effect coefficient (small source voltage) η = DIBL coefficient W kt A = μ ox L q R. Amirtharajah, EEC216 Winter D 1.8 C e 2 kt
11 Leakage Currents vs. Active Currents I leak I leak Out A = 1 B = 1 M M1 I active I active /I leak (I on /I off ) ratio can be small in subthreshold R. Amirtharajah, EEC216 Winter 29 13
12 Degraded Output Levels Vdd ideal V OH Vout actual V OL V Vdd Vin Balance current ratio through sizing, limiting fanin R. Amirtharajah, EEC216 Winter 29 14
13 Degraded Logic Levels Impact Functionality Clk = 8 mv I active Q D Clk V DD =.3 V = 22 mv I off Clk = 8 mv Driven by two inverters to intermediate voltage R. Amirtharajah, EEC216 Winter 29 15
14 WL SRAM Cell Leakage Paths 1 BL BL Leakage paths can degrade read and write noise margins R. Amirtharajah, EEC216 Winter 29 16
15 Circuit Design Summary Subthreshold design similar to ratioed ckt design Must guarantee active currents sufficiently greater than leakage currents to maintain valid logic levels Degraded logic levels can cause failure in combinational and sequential circuits All circuits (esp. SRAMs) sensitive to V TH variation Be careful with subthreshold circuits Consider worst case leakage situations (data dependent) when analyzing I on /I off ratio problems Use nonminimum channel lengths, limit fanin Watch sneak leakage paths through pass gates Interrupt pass gate chains with static logic R. Amirtharajah, EEC216 Winter 29 17
16 Challenges for Ultra Low Voltage Device variability (within die, across dies, and across wafers) Variations in threshold voltage drastically affect critical circuit performance parameters Examples: I on /I off ratios, gate delays, static memory noise margins, subthreshold slope for leakage limiting devices Noise and event tolerance Approaching fundamental noise limit may decrease reliability and MTTF Limited charge storage on circuit nodes may increase susceptibility to soft errors in both memory and logic 16
17 Sub-V t Design Challenges RDF.3 t Leakage V OUT (V).2.1 Active V (V) IN on off Sub-V t static CMOS gates exhibit variation in logic levels (V OH, V OL ) From Kwong et al., ISSCC 8 28 IEEE International Solid-State Circuits Conference 28 IEEE
18 Sub-V t Logic Functionality Degraded logic levels adversely impact functionality V OUT (V) V (V) IN Voltage (V) CLK CLK Time (µs) N2,Q N3 N4 N2 CLK N3 N4 Not completely off, causing functional failure From Kwong et al., ISSCC 8 28 IEEE International Solid-State Circuits Conference 28 IEEE
19 Sub-V t Logic Design Functional metric necessary to manage sizing trade-off t σv t 1 WL NAND NOR V OUT-NAND, V IN-NOR.2.1 NAND NOR.1.2 V OUT-NAND, V IN-NOR.2.1 NAND NOR Logic failure.1.2 V IN-NAND, V OUT-NOR V IN-NAND, V OUT-NOR From Kwong et al., ISSCC 8 28 IEEE International Solid-State Circuits Conference 28 IEEE
20 Sub-V t Standard Cell Library Occurrences 2 1 Leakage Active V OL (V) t Occurrences 1 5 Outliers V OH (V) 1 t 1 Occurrences 5 Occurrences V OL (V) From Kwong et al., ISSCC V OH (V) 28 IEEE International Solid-State Circuits Conference 28 IEEE
21 Sub-V t SRAM Challenges Hold SNM WL WL Read SNM NT 1. NC BL 1. BL NT NC NT, NC (V) Hold SNM preserved to low-voltages NT, NC (V) Read SNM degraded at low-voltages NC, NT (V) From Kwong et al., ISSCC NC, NT (V) 28 IEEE International Solid-State Circuits Conference 28 IEEE
22 SRAM Architecture and Bit-Cell Based on Verma, ISSCC 27 Buffer eliminates read SNM limitation Peripheral assists allow sub-v t writing and sensing From Kwong et al., ISSCC 8 28 IEEE International Solid-State Circuits Conference 28 IEEE
23 Volts Volts WR WR Peripheral Assists VV DD Write NT VV DD 1 1 NT NC 1 NC µs RDBL Voltage Read From Kwong et al., ISSCC 8 1 VV DD 6T Cell PCHRG 1 (256, 64 Cells) No sub-v t leakage 1 (256 Cells) 1 (64 Cells) µs 28 IEEE International Solid-State Circuits Conference 28 IEEE
24 Sub-V t Timing Analysis Challenges Order-of-magnitude higher delay variation in sub-v t Occurrences Occurrences From Kwong et al., ISSCC 8 28 IEEE International Solid-State Circuits Conference 28 IEEE
25 Comprehensive Timing Simulations Increasing mean delay Path # σ /µ (Std. dev. over mean) Simulation of 3 timing paths illustrates trends in sub-vt delay variability Delay (ns) 2 Mean delay [ns] From Kwong et al., ISSCC 8 28 IEEE International Solid-State Circuits Conference 28 IEEE 4
26 Test-Chip Summary Process DC-DC Converter SRAM Logic Minimum Energy Point Minimum Functional V DD Area Performance 65nm CMOS.12mm mm 2.14mm 2 V DD = 5mV V DD = 3mV 1.86mm Core logic (2 power domains) 128Kb SRAM array 2.29mm DC-DC converter From Kwong et al., ISSCC 8 28 IEEE International Solid-State Circuits Conference 28 IEEE
27 Conclusions Many opportunities for ultra low voltage design exist Energy Constrained Applications: wireless sensors, mobile devices, biomedical implants Minimum Power Applications: sleep and minimum leakage modes in processors and memories Main challenge is device parameter variations Threshold voltage variation severely impacts delays, noise margins in logic and SRAM Very active area of circuits research ISSCC 29 Advanced Circuits Forum on Ultra Low Voltage 17
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