ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Two Problems. Outline. Output not go to Rail
|
|
- Elaine Cleopatra Rice
- 5 years ago
- Views:
Transcription
1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 6: September 19, 2011 Restoration Today How do we make sure logic is robust Can assemble into any (feed forward) graph Can tolerate voltage drops and noise.while maintaining digital abstraction 1 2 Outline Two Problems Two problems Cascade failure Restoration Transfer Curves Noise Margins Non-linear 1. Output not go to rail Stops short of Vdd or Gnd 2. Signals may be perturbed by noise V x = V ideal ± V noise 3 4 Output not go to Rail Output not go to Rail CMOS, capacitive load Mostly doesn t have problem CMOS, resistive load? Consider: Vdd=1V Vin=Gnd (both inputs) Ron (PMOS) = 500Ω Rload = 10KΩ What is Vout? R on =500 Ω R on =500 Ω R load =10K Ω How close to rail do I need to get? 5 6 1
2 Wire Resistance Wire Resistance 1000 µm long wire? 1 cm long wire? Length of die side? Last Monday: R wire =10Ω R = ρl A 7 8 Die Sizes Processor Die Size Transistor Count Process Implications What does the circuit really look like for an inverter in the middle of the chip? Core 2 Extreme X mm² 291 Mio. 65 nm Core 2 Duo E mm² 291 Mio. 65 nm Core 2 Duo E mm² 291 Mio. 65 nm Core 2 Duo E mm² 167 Mio. 65 nm Core 2 Duo E mm² 167 Mio. 65 nm Pentium D mm² 376 Mio. 65 nm Athlon 64 FX mm² 227 Mio. 90 nm Athlon mm² 154 Mio. 90 nm Implications What does the circuit really look like for an inverter in the middle of the chip? Rwire IR-Drop R rest_of_chip Since interconnect is resistive and gates pull current off the supply interconnect The Vdd seen by a gate is lower than the supply Voltage by V drop =I supply x R distribute Rwire Rrest_of_chip Two gates in different locations See different R distribute Therefore, see different V drop
3 Output not go to Rail CMOS, capacitive load no problem CMOS, resistive load voltage divider Due to IR drop, rails for two communicating gates may not match Two Problems 1. Output not go to rail Is this tolerable? 2. Signals may be perturbed by noise Voltage seen at input to a gate may not lower/higher than input voltage Noise Sources? Signals will be degraded What did we see in lab when zoomed in on signal transition? Signal coupling Crosstalk Leakage Ionizing particles IR-drop in signal wiring 1. Output not go to rail Is this tolerable? 2. Signals may be perturbed by noise Voltage seen at input to a gate may not lower/higher than input voltage What happens to degraded signals? Preclass Preclass All 1 s logical output? 1.0 inputs, gate: o=1-ab output voltage?
4 Preclass 0.95 inputs, gate: o=1-ab output voltage? Degradation Cannot have signal degrade across gates Want to be able to cascade arbitrary set of gates Gate Creed Gates should leave the signal better than they found it better closer to the rails Restoration Discipline Define legal inputs Gate works if Vin close enough to the rail Restoration Gate produces Vout closer to rail This tolerates some drop between one gate and text (between out and in) Call this our Noise Margin Noise Margin Restoration Discipline (getting precise) V oh output high V ol output low Define legal inputs Gate works if Vin close enough to the rail V ih input high V il input low Vin > V ih or Vin < V il Restoration Gate produces Vout closer to rail NM h = V oh -V ih NM l = V ol -V il One mechanism, addresses numerous noise sources. 23 Vout < V ol or Vout > V oh Note: don t just say V in >V ih V out >V oh 24 4
5 Transfer Function What gate is this? Restoring Transfer Function Restoring Transfer Function Restoring Transfer Function V il, V ih = slope -1 points V oh =f(v il ) V ol =f(v ih ) For multi-input functions, should be worst case. i.e. hold non-controlling inputs at Vil, Vih respectively. (relate preclass exercise) Ideal Transfer Function Linear Transfer Function? O=Vdd-A Noise Margin?
6 Linear Transfer Function? Consider two in a row (buffer) O1=Vdd-A What is transfer function to buffer output O2? O2=(Vdd-O1) = Vdd-(Vdd-A)=A Linear Transfer Function? For buffer: O2=A Consider chain of buffers What happens if A drops a bit between each buffer? A i+1 = A i -Δ Conclude: Linear transfer functions do not provide restoration Non-linearity Transistor Non-Linearity Need non-linearity in transfer function Could not have built restoring gates with R, L, C circuit Linear elements V ol V oh All Gates If we hope to assemble design from collection of gates, Voltage levels must be consistent and supported across all gates Must adhere to a V il, V ih, V ol, V oh that is valid across entire gate set =MAX ( g.v ol) V il =MIN ( g.v il) =MIN ( g.v oh) V ih =MAX ( g.v ih) 35 Admin Wednesday in Ketterer Lab combo Read through HW2 Be ready to run electric and spice on linux CETS machines <or> own laptop that you bring with you Friday back here 36 6
7 Big Idea Need robust logic Can assemble into any (feed forward) graph Can tolerate loss and noise.while maintaining digital abstraction Restoration and noise margins Every gate makes signal better Design level of noise tolerance 37 7
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Two Problems. Outline. Output not go to Rail
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 6: September 17, 2012 Restoration Today How do we make sure logic is robust Can assemble into any (feed forward) graph Can
More informationECE520 VLSI Design. Lecture 5: Basic CMOS Inverter. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 5: Basic CMOS Inverter Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture
More informationLecture 11 Digital Circuits (I) THE INVERTER
Lecture 11 Digital Circuits (I) THE INVERTER Outline Introduction to digital circuits The inverter NMOS inverter with resistor pull-up Reading Assignment: Howe and Sodini; Chapter 5, Sections 5.1-5.3 6.12
More informationLecture 11 Circuits numériques (I) L'inverseur
Lecture 11 Circuits numériques (I) L'inverseur Outline Introduction to digital circuits The inverter NMOS inverter with resistor pull-up 6.12 Spring 24 Lecture 11 1 1. Introduction to digital circuits:
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Previously: Two XOR Gates. Pass Transistor Logic. Cascaded Pass Gates
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lecture Outline! Pass Transistor Logic! Performance Lec 15: March 2, 2017 Combination Logic: Pass Transistor Logic, and Performance 2 Previously:
More informationLecture 12 - Digital Circuits (I) The inverter. October 20, 2005
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 12-1 Lecture 12 - Digital Circuits (I) The inverter October 2, 25 Contents: 1. Introduction to digital electronics: the inverter 2. NMOS inverter
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Teaser. Pass Transistor Logic. Identify Function.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lecture Outline! Pass Transistor Logic! Performance Lec 15: March 1, 2018 Combination Logic: Pass Transistor Logic, and Performance 2 Pass Transistor
More informationCPE/EE 427, CPE 527 VLSI Design I CMOS Inverter. CMOS Inverter: A First Look
CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic CMOS Inverter: A First Look C L 9/11/26 VLSI
More informationELEC 2210 EXPERIMENT 12 NMOS Logic
ELEC 2210 EXPERIMENT 12 NMOS Logic Objectives: The experiments in this laboratory exercise will provide an introduction to NMOS logic. You will use the Bit Bucket breadboarding system to build and test
More informationLecture 4. The CMOS Inverter. DC Transfer Curve: Load line. DC Operation: Voltage Transfer Characteristic. Noise in Digital Integrated Circuits
Noise in Digital Integrated Circuits Lecture 4 The CMOS Inverter i(t) v(t) V DD Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail:
More informationVLSI Design I; A. Milenkovic 1
CPE/EE 427, CPE 527 VLSI Design I L02: Design Metrics Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe527-03f
More informationDigital Electronics. Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region. Positive Logic.
Digital Electronics Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region Positive Logic Logic 1 Negative Logic Logic 0 Voltage Transition Region Transition
More informationECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics
ECE 484 VLSI Digital Circuits Fall 2016 Lecture 02: Design Metrics Dr. George L. Engel Adapted from slides provided by Mary Jane Irwin (PSU) [Adapted from Rabaey s Digital Integrated Circuits, 2002, J.
More informationEECS 141: SPRING 98 FINAL
University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey 511 Cory Hall TuTh3:3-5pm e141@eecs EECS 141: SPRING 98 FINAL For all problems, you
More informationDigital Electronic Circuits
ECE 25 VI Diode Circuits Lab VI Digital Electronic Circuits In this lab we will look at two different kinds of inverters: nmos versus CMOS. VI.1 PreLab 1) Power consideration of inverters: a. Using PSICE,
More informationPC accounts for 353 Cory will be created early next week (when the class list is completed) Discussions & Labs start in Week 3
EE141 Fall 2005 Lecture 2 Design Metrics Admin Page Everyone should have a UNIX account on Cory! This will allow you to run HSPICE! If you do not have an account, check: http://www-inst.eecs.berkeley.edu/usr/
More informationEE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 23 p. 1/16 EE 42/100 Lecture 23: CMOS Transistors and Logic Gates ELECTRONICS Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad University
More informationChapter 6 DIFFERENT TYPES OF LOGIC GATES
Chapter 6 DIFFERENT TYPES OF LOGIC GATES Lesson 8 NMOS gates Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline NMOS (n-channel based MOSFETs based circuit) NMOS Features
More information4-bit counter circa bit counter circa 1990
Digital Logic 4-bit counter circa 1960 8-bit counter circa 1990 Logic gates Operates on logical values (TRUE = 1, FALSE = 0) NOT AND OR XOR 0-1 1-0 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1 0 1 0 1 1 1 1 1 0 0 0
More informationTopic 6. CMOS Static & Dynamic Logic Gates. Static CMOS Circuit. NMOS Transistors in Series/Parallel Connection
NMOS Transistors in Series/Parallel Connection Topic 6 CMOS Static & Dynamic Logic Gates Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Transistors can be thought
More informationESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. MOSFET Ids vs. Vgs, Vds MOSFET. Preclass. MOSFET I vs.
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 2: September 7, 2012 Transistor Introduction Today MOSFET Capacitive and resistive loads Zero-th order transistor model
More informationDigital Electronics Part II - Circuits
Digital Electronics Part II - Circuits Dr. I. J. Wassell Gates from Transistors 1 Introduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits
More informationLecture Summary Module 1 Switching Algebra and CMOS Logic Gates
Lecture Summary Module 1 Switching Algebra and CMOS Logic Gates Learning Outcome: an ability to analyze and design CMOS logic gates Learning Objectives: 1-1. convert numbers from one base (radix) to another:
More informationECE2274 Pre-Lab for MOSFET logic LTspice NAND Gate, NOR Gate, and CMOS Inverter
ECE2274 Pre-Lab for MOFET logic LTspice NAN ate, NOR ate, and CMO Inverter 1. NMO NAN ate Use Vdd = 9.. For the NMO NAN gate shown below gate, using the 2N7000 MOFET LTspice model such that Vto = 2.0.
More informationChapter 6 DIFFERENT TYPES OF LOGIC GATES
Chapter 6 DIFFERENT TYPES OF LOGIC GATES Lesson 9 CMOS gates Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline CMOS (n-channel based MOSFETs based circuit) CMOS Features
More informationUNIT-III GATE LEVEL DESIGN
UNIT-III GATE LEVEL DESIGN LOGIC GATES AND OTHER COMPLEX GATES: Invert(nmos, cmos, Bicmos) NAND Gate(nmos, cmos, Bicmos) NOR Gate(nmos, cmos, Bicmos) The module (integrated circuit) is implemented in terms
More informationDIGITAL ELECTRONICS. Digital Electronics - A2 28/04/ DDC Storey 1. Politecnico di Torino - ICT school. A2: logic circuits parameters
Politecnico di Torino - ICT school A2: logic circuits parameters DIGITAL ELECTRONICS A INTRODUCTION A.2 Logic circuits parameters» Static parameters» Interfacing and compatibility» Output stages» Dynamic
More informationDIGITAL VLSI LAB ASSIGNMENT 1
DIGITAL VLSI LAB ASSIGNMENT 1 Problem 1: NMOS and PMOS plots using Cadence. In this exercise, you are required to generate both NMOS and PMOS I-V device characteristics (I/P and O/P) using Cadence (Use
More informationTTL LOGIC and RING OSCILLATOR TTL
ECE 2274 TTL LOGIC and RING OSCILLATOR TTL We will examine two digital logic inverters. The first will have a passive resistor pull-up output stage. The second will have an active transistor and current
More informationDigital Electronics. Assign Ò1Ó and Ò0Ó to a range of voltage (or current), with a separation that minimizes a transition region.
Digital Electronics Assign Ò1Ó and Ò0Ó to a range of voltage (or current), with a separation that minimizes a transition region Positive Logic Logic 1 Negative Logic Logic 0 Voltage Transition egion Transition
More informationDigital Microelectronic Circuits ( ) Terminology and Design Metrics. Lecture 2: Presented by: Adam Teman
Digital Microelectronic Circuits (361-1-3021 ) Presented by: Adam Teman Lecture 2: Terminology and Design Metrics 1 Last Week Introduction» Moore s Law» History of Computers Circuit analysis review» Thevenin,
More informationPractical Aspects Of Logic Gates
Practical Aspects Of Logic Gates Introduction & Objectives Logic gates are physically implemented as Integrated Circuits (IC). Integrated circuits are implemented in several technologies. Two landmark
More informationDIGITAL ELECTRONICS. A2: logic circuits parameters. Politecnico di Torino - ICT school
Politecnico di Torino - ICT school A2: logic circuits parameters DIGITAL ELECTRONICS A INTRODUCTION A.2 Logic circuits parameters» Static parameters» Interfacing and compatibility» Output stages» Dynamic
More informationWritten Examination on. Wednesday October 17, 2007,
Written Examination on Wednesday October 17, 2007, 08.00-12.00 The textbook and a calculator are allowed on the examination 1. The following logical function is given Q= AB( CD+ CE) + F a. Draw the schematic
More informationLecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1
Lecture 16 Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Outline Complementary metal oxide semiconductor (CMOS) Inverting circuit Properties Operating points Propagation delay Power dissipation
More informationEEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic Families
EEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic Families Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Homework 5 this week Lab
More informationQuad 2-Input NAND Gate High-Voltage Silicon-Gate CMOS
TECHNICAL DATA Quad 2-Input NAND Gate High-oltage Silicon-Gate CMOS The NAND gates provide the system designer with direct emplementation of the NAND function. Operating oltage Range:.0 to 18 Maximum input
More informationDigital Systems Laboratory
2012 Fall CSE140L Digital Systems Laboratory Lecture #2 by Dr. Choon Kim CSE Department, UCSD chk034@eng.ucsd.edu Lecture #2 1 Digital Technologies CPU(Central Processing Unit) GPU(Graphics Processing
More informationLecture 13 - Digital Circuits (II) MOS Inverter Circuits. October 25, 2005
6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-1 Lecture 13 - Digital Circuits (II) MOS Inverter Circuits October 25, 25 Contents: 1. NMOS inverter with resistor pull-up (cont.) 2. NMOS
More information4-bit counter circa bit counter circa 1990
Digital Logic 4-bit counter circa 1960 8-bit counter circa 1990 Logic gates Operates on logical values (TRUE = 1, FALSE = 0) NOT AND OR XOR 0-1 1-0 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1 0 1 0 1 1 1 1 1 0 0 0
More information! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential
More informationReading. Lecture 17: MOS transistors digital. Context. Digital techniques:
Reading Lecture 17: MOS transistors digital Today we are going to look at the analog characteristics of simple digital devices, 5. 5.4 And following the midterm, we will cover PN diodes again in forward
More informationMicrocontroller Systems. ELET 3232 Topic 13: Load Analysis
Microcontroller Systems ELET 3232 Topic 13: Load Analysis 1 Objective To understand hardware constraints on embedded systems Define: Noise Margins Load Currents and Fanout Capacitive Loads Transmission
More informationIn this experiment you will study the characteristics of a CMOS NAND gate.
Introduction Be sure to print a copy of Experiment #12 and bring it with you to lab. There will not be any experiment copies available in the lab. Also bring graph paper (cm cm is best). Purpose In this
More informationESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Variation. Variation. Process Corners.
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and Area Today Coping with Variation (from last time) Layout Transistors Gates Design rules Standard
More informationIntroduction. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, 2002 1 What is this book all about? Introduction to digital integrated circuits.
More information! Review: Sequential MOS Logic. " SR Latch. " D-Latch. ! Timing Hazards. ! Dynamic Logic. " Domino Logic. ! Charge Sharing Setup.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 29, 206 Timing Hazards and Dynamic Logic Lecture Outline! Review: Sequential MOS Logic " SR " D-! Timing Hazards! Dynamic Logic "
More information! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology. " Gate choice, logical optimization. " Fanin, fanout, Serial vs.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Design Space Exploration Lec 18: March 28, 2017 Design Space Exploration, Synchronous MOS Logic, Timing Hazards 3 Design Problem Problem Solvable!
More informationCHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS
70 CHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS A novel approach of full adder and multipliers circuits using Complementary Pass Transistor
More informationAP1511A / B IR Filter Switch Driver
AP1511A / B with one-shot output for IR-Cut Removable (ICR) ANAPEX TECHNOLOGY INC. 2F -1, No.5, Tai-Yuen 1st St., Jhubei City, Hsinchu 30265, Taiwan, R.O.C. Agent: AENEAS ELECTRONICS CO.,LTD. Tel: +886-2-87974259
More informationDigital Integrated Circuits EECS 312
14 12 10 8 6 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) 0 1950 1960 1970 1980
More informationECE 301 Digital Electronics
ECE 301 Digital Electronics Constraints in Logic Circuit Design (Lecture #14) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and
More informationCD4063BMS. CMOS 4-Bit Magnitude Comparator. Pinout. Features. Functional Diagram. Applications. Description. December 1992
CD3BMS December 99 Features CMOS -Bit Magnitude Comparator Pinout High Voltage Type (V Rating) Expansion to 8,,... N Bits by Cascading Units CD3BMS TOP VIEW Medium Speed Operation - Compares Two -Bit Words
More informationCombinational Logic. Prof. MacDonald
Combinational Logic Prof. MacDonald 2 Input NOR depletion NFET load l Pull Down Network can pull OUT down if either or both inputs are above Vih consequently the NOR function. l Depletion NFET could really
More informationDigital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Ratioed Logic Introduction Digital IC EE141 2 Ratioed Logic design Basic concept Resistive load Depletion
More informationDual Passive Input Digital Isolator. Features. Applications
Dual Passive Input Digital Isolator Functional Diagram Each device in the dual channel IL611 consists of a coil, vertically isolated from a GMR Wheatstone bridge by a polymer dielectric layer. A magnetic
More informationIntroduction. Introduction. Digital Integrated Circuits A Design Perspective. Introduction. The First Computer
Digital Integrated Circuits A Design Perspective Prentice Hall Electronics and VLSI Series ISBN 0-3-20764-4 [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,
More informationLow current consumption : 0.4 ma typ. Driver output current : 70 ma max. 5 MHz (cascade connection) Selectable H/L for latch and driver enable
The is a CMOS thermal print head driver containing a 64-bit shift register and a latch. It can be used for general purpose because H or L can be selected for the latch and the driver enable. It is ideal
More informationSolution HW4 Dr. Parker EE477
Solution HW4 Dr. Parker EE477 Assume for the problems below that V dd = 1.8 v, V tp0 is -.7 v. and V tn0 is.7 V. V tpbodyeffect is -.9 v. and V tnbodyeffect is.9 V. Assume ß n (k n )= 219.4 W/L µ A(microamps)/V
More informationECEN3250 Lab 9 CMOS Logic Inverter
Lab 9 CMOS Logic Inverter ECE Department University of Colorado, Boulder 1 Prelab Read Section 4.10 (4th edition Section 5.8), and the Lab procedure Do and turn in Exercise 4.41 (page 342) Do PSpice (.dc)
More informationEEC 216 Lecture #10: Ultra Low Voltage and Subthreshold Circuit Design. Rajeevan Amirtharajah University of California, Davis
EEC 216 Lecture #1: Ultra Low Voltage and Subthreshold Circuit Design Rajeevan Amirtharajah University of California, Davis Opportunities for Ultra Low Voltage Battery Operated and Mobile Systems Wireless
More informationQuad Audio Switch REV. B BLOCK DIAGRAM OF ONE SWITCH CHANNEL
a FEATURES CIickless Bilateral Audio Switching Four SPST Switches in a -Pin Package Ultralow THD+N:.8% @ khz ( V rms, R L = k ) Low Charge Injection: 3 pc typ High OFF Isolation: db typ (R L = k @ khz)
More informationMassachusetts Institute of Technology Department of Electrical Engineering and Computer Science Electronic Circuits Spring 2007
assachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.002 Electronic Circuits Spring 2007 Lab 2: OSFET Inverting Amplifiers & FirstOrder Circuits Handout S07034
More informationUnit 1 Session - 3 TTL Parameters
Objectives Understanding various TTL Parameters Floating Inputs Worst-Case Input Voltages & Output Voltages Profiles and Windows Compatibility Sourcing and Sinking Noise Immunity Standard Loading and Loading
More informationECE 2300 Digital Logic & Computer Organization
ECE 2300 Digital Logic & Computer Organization Spring 2018 CMOS Logic Lecture 4: 1 NAND Logic Gate X Y (X Y) = NAND Using De Morgan s Law: (X Y) = X +Y X X X +Y = Y Y Also a NAND We can build circuits
More information! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2017 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!
More informationMOS TRANSISTOR THEORY
MOS TRANSISTOR THEORY Introduction A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain is modulated by a voltage applied to the
More informationECE 497 JS Lecture - 22 Timing & Signaling
ECE 497 JS Lecture - 22 Timing & Signaling Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Announcements - Signaling Techniques (4/27) - Signaling
More informationNote that none of the above MAY be a VALID ANSWER.
ECE 270 Learning Outcome 1-1 - Practice Exam / Solution LEARNING OUTCOME #1: an ability to analyze and design CMOS logic gates. Multiple Choice select the single most appropriate response for each question.
More informationMultiplexer for Capacitive sensors
DATASHEET Multiplexer for Capacitive sensors Multiplexer for Capacitive Sensors page 1/7 Features Very well suited for multiple-capacitance measurement Low-cost CMOS Low output impedance Rail-to-rail digital
More informationNOVEMBER 28, 2016 COURSE PROJECT: CMOS SWITCHING POWER SUPPLY EE 421 DIGITAL ELECTRONICS ERIC MONAHAN
NOVEMBER 28, 2016 COURSE PROJECT: CMOS SWITCHING POWER SUPPLY EE 421 DIGITAL ELECTRONICS ERIC MONAHAN 1.Introduction: CMOS Switching Power Supply The course design project for EE 421 Digital Engineering
More informationECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers
ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic
More informationISSN: [Kumar* et al., 6(5): May, 2017] Impact Factor: 4.116
IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY IMPROVEMENT IN NOISE AND DELAY IN DOMINO CMOS LOGIC CIRCUIT Ankit Kumar*, Dr. A.K. Gautam * Student, M.Tech. (ECE), S.D. College
More informationDigital Integrated Circuits (83-313) Lecture 3: Design Metrics
Digital Integrated Circuits (83-313) Lecture 3: Design Metrics Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 2 April 2017 Disclaimer: This course was prepared, in its entirety,
More informationLow Power Consumption IPS009BL9_BL9A_BLAA AT Cut 32KHz SPXO
Description IPS009BL9, IPS009BL9A and is the specific SPXO IC for achieving 32KHz output by divide, corresponding to the fundamental crystal from 14MHZ to 27MHz and 33.554MHz corresponding to each IC.
More informationSubmission date: Wednesday 21/3/2018
Faculty of Information Engineering & Technology Electrical & Electronics Department Course: Microelectronics Lab ELCT605 Spring 2018 Dr. Eman Azab Eng. Samar Shukry Analog Report 1, 2 DC, TRANSIENT, AND
More informationJack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php
More informationM74HCT04. Hex inverter. Features. Description
Hex inverter Features High speed: t PD = 11 ns (typ.) at =4.5V Low power dissipation: I CC = 1 μa (max.) at T A =25 C Compatible with TTL outputs: V IH = 2 V (min.) V IL = 0.8 V (max) Balanced propagation
More informationEE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector
EE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector Group Members Uttam Kumar Boda Rajesh Tenukuntla Mohammad M Iftakhar Srikanth Yanamanagandla 1 Table
More informationPrecision, Low-Power and Low-Noise Op Amp with RRIO
MAX41 General Description The MAX41 is a low-power, zero-drift operational amplifier available in a space-saving, 6-bump, wafer-level package (WLP). Designed for use in portable consumer, medical, and
More informationPractice 6: CMOS Digital Logic
Practice 6: CMOS Digital Logic Digital Electronic Circuits Semester A 2012 The MOSFET as a Switch The MOSFET as a Switch We can look at the MOSFET as a Switch, passing the data between the diffusions when
More informationCHAPTER 6 DIGITAL CIRCUIT DESIGN USING SINGLE ELECTRON TRANSISTOR LOGIC
94 CHAPTER 6 DIGITAL CIRCUIT DESIGN USING SINGLE ELECTRON TRANSISTOR LOGIC 6.1 INTRODUCTION The semiconductor digital circuits began with the Resistor Diode Logic (RDL) which was smaller in size, faster
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2019 Khanna Jack Keil Wolf Lecture http://www.ese.upenn.edu/about-ese/events/wolf.php
More information2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)
1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2) Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic
More information! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2016 Khanna Adapted from GATech ESE3060 Slides Lecture
More informationCombinational Logic Gates in CMOS
Combinational Logic Gates in CMOS References: dapted from: Digital Integrated Circuits: Design Perspective, J. Rabaey UC Principles of CMOS VLSI Design: Systems Perspective, 2nd Ed., N. H. E. Weste and
More informationLecture 9: Clocking for High Performance Processors
Lecture 9: Clocking for High Performance Processors Computer Systems Lab Stanford University horowitz@stanford.edu Copyright 2001 Mark Horowitz EE371 Lecture 9-1 Horowitz Overview Reading Bailey Stojanovic
More informationObsolete Product(s) - Obsolete Product(s)
QUAD 2 INPUT NAND GATE PROPAGATION DELAY TIME t PD = 60ns (Typ.) at V DD = 10V BUFFERED INPUTS AND OUTPUTS STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V
More informationI. Digital Integrated Circuits - Logic Concepts
I. Digital Integrated Circuits - Logic Concepts. Logic Fundamentals: binary mathematics: only operate on and (oolean algebra) simplest function -- inversion = symbol for the inverter INPUT OUTPUT EECS
More informationEXPERIMENT 12: DIGITAL LOGIC CIRCUITS
EXPERIMENT 12: DIGITAL LOGIC CIRCUITS The purpose of this experiment is to gain some experience in the use of digital logic circuits. These circuits are used extensively in computers and all types of electronic
More information3. COMPARING STRUCTURE OF SINGLE GATE AND DOUBLE GATE MOSFET WITH DESIGN AND CURVE
P a g e 80 Available online at http://arjournal.org APPLIED RESEARCH JOURNAL RESEARCH ARTICLE ISSN: 2423-4796 Applied Research Journal Vol. 3, Issue, 2, pp.80-86, February, 2017 COMPARATIVE STUDY ON SINGLE
More informationVisible Light Detector B
Over 150 million die shipped per year DESCRIPTION The is a low cost visible light sensor, with a current output which is directly proportional to the light level. It has a built in optical filter to provide
More informationCPE/EE 427, CPE 527 VLSI Design I L01: Introduction, Design Metrics. What is this course all about?
CPE/EE 427, CPE 527 VLSI Design I L01: Introduction, Design Metrics Aleksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe527-05f What is this course all about? Introduction to
More informationExercise 1: DC Operation of a NOT and an OR-TIE
Open Collector and Other TTL Gates Digital Logic Fundamentals Exercise 1: DC Operation of a NOT and an OR-TIE EXERCISE OBJECTIVE When you have completed this exercise, you will be able to demonstrate the
More informationPlace answers on the supplied BUBBLE SHEET only nothing written here will be graded.
ECE 270 Learning Outcome 1-1 - Practice Exam B OUTCOME #1: an ability to analyze and design CMOS logic gates. Multiple Choice select the single most appropriate response for each question. Note that none
More informationLow Power Design for Systems on a Chip. Tutorial Outline
Low Power Design for Systems on a Chip Mary Jane Irwin Dept of CSE Penn State University (www.cse.psu.edu/~mji) Low Power Design for SoCs ASIC Tutorial Intro.1 Tutorial Outline Introduction and motivation
More informationDigital Integrated CircuitDesign
Digital Integrated CircuitDesign Lecture 11 BiCMOS PMOS rray Q1 NMOS rray Y NMOS rray Q2 dib brishamifar EE Department IUST Contents Introduction BiCMOS Devices BiCMOS Inverters BiCMOS Gates BiCMOS Drivers
More informationRuixing Yang
Design of the Power Switching Network Ruixing Yang 15.01.2009 Outline Power Gating implementation styles Sleep transistor power network synthesis Wakeup in-rush current control Wakeup and sleep latency
More informationLab 7 (Hands-On Experiment): CMOS Inverter, NAND Gate, and NOR Gate
Lab 7 (Hands-On Experiment): CMOS Inverter, NAND Gate, and NOR Gate EECS 170LB, Wed. 5:00 PM TA: Elsharkasy, Wael Ryan Morrison Buu Truong Jonathan Lam 03/05/14 Introduction The purpose of this lab is
More information