ELEC Digital Logic Circuits Fall 2015 Delay and Power

Transcription

1 ELEC - Digital Logic Circuits Fall 5 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL vagrawal@eng.auburn.edu Fall 5, Nov 3 ELEC- Lecture 8

2 Power and Delay of a Transition R on V DD v i (t) i c (t) v o (t) R = large C L Ground C L = Total load capacitance for gate; includes transistor capacitances of driving gate + routing capacitance + transistor capacitances of driven gates; obtained by layout analysis. Fall 5, Nov 3 ELEC- Lecture 8

3 Charging of a Capacitor R = R on t = V DD i(t) C = C L v(t) Charge on capacitor, q(t) = C v(t) Current, i(t) = dq(t)/dt = C dv(t)/dt Fall 5, Nov 3 ELEC- Lecture 8 3

4 i(t) = C dv(t)/dt = [V DD v(t)] /R dv(t) dt = V DD v(t) RC ln [V DD v(t)] = t RC + A Initial condition, t =, v(t) = A = ln V DD t v(t) = V DD [ exp( )] =.5V DD RC t =.69 RC Fall 5, Nov 3 ELEC- Lecture 8 4

5 Delay: Definitions Rise time is the time a signal takes to rise from % to 9% of its peak value. Fall time is the time a signal takes to drop from 9% to % of its peak value. Delay of a gate or circuit is the time interval between the input crossing 5% of peak value and the output crossing 5% of peak value. A NOT gate B VDD A GND VDD B GND 9% VDD % VDD Fall time Time Rise time Time 9% VDD % VDD Gate delay Fall 5, Nov 3 ELEC- Lecture 8 5

6 Inverter: Idealized Input V DD INPUT GND V DD Gate delay OUTPUT.5V DD GND t =.69CR time Fall 5, Nov 3 ELEC- Lecture 8 6

7 Timing of a Digital Circuit Most digital circuits are clocked synchronous finite state machines (FSM). Primary Inputs FF FF Combinational circuit (Gates interconnected without feedback) FF FF Primary Outputs Clock FF FF Fall 5, Nov 3 ELEC- Lecture 8 7

8 Large Circuit Timing Analysis Determine gate delays: From layout analysis, or use approximate delays: Gate delay increases in proportion to number of fanouts (increased capacitance) Delay decreases in proportion to increase in gate size (reduced transistor channel resistance) Purpose of analysis is to verify timing behavior determine maximum speed of operation. Methods of analysis: Circuit simulation most accurate, expensive (Spice program) Static timing analysis (STA) most efficient, approximate Fall 5, Nov 3 ELEC- Lecture 8 8

9 Static Timing Analysis (STA) Combinational logic for critical path delays. Circuit represented as an acyclic directed graph (DAG). Gates characterized by delays; gate function ignored. No inputs are used worst-case analysis static analysis (simulation would be dynamic). Fall 5, Nov 3 ELEC- Lecture 8 9

10 Combinational Circuit of an FSM A Gate delay H B C D E 4 Fanout = 4 F G J Input to Output delay must not exceed clock period Fall 5, Nov 3 ELEC- Lecture 8

11 Fall 5, Nov 3 ELEC- Lecture 8 Static Timing Analysis (STA) Step A B D E 4 F J G H C Levelize circuit. Initialize arrival times at primary inputs to. Level Level of a gate is one greater than the maximum of fanin gate levels

12 Fall 5, Nov 3 ELEC- Lecture 8 Static Timing Analysis (STA) Step A B D E 4 F J G H C Level Determine output arrival times of gates in level order Arrival time at a gate output = maximum of input arrivals + gate delay

13 Fall 5, Nov 3 ELEC- Lecture 8 3 Static Timing Analysis (STA) Step 3 A B D E 4 F J G H C Level Trace critical paths from the output with longest arrival time. Critical path: C, E, F, G, H; delay =

14 Power in CMOS Logic (Inverter) VDD No current flows from power supply! Where is power consumed? GND F. M. Wanlass and C. T. Sah, Nanowatt Logic using Field-Effect Metal-Oxide-Semiconductor Triodes, IEEE International Solid- State Circuits Conference Digest, vol. IV, February 963, pp Fall 5, Nov 3 ELEC- Lecture 8 4

15 Three Components of Power Dynamic, when output changes Signal transitions (major component) Logic activity Glitches Short-circuit (small, often neglected) Static, when signal is in steady state Leakage (small) P total = P dyn + P stat = P tran + P sc + P stat Fall 5, Nov 3 ELEC- Lecture 8 5

16 Charging of Output Capacitor From Slide 4: t v(t) = V [ exp( )] RC dv(t) V t i(t) = C = exp( ) dt R RC Fall 5, Nov 3 ELEC- Lecture 8 6

17 Total Energy Per Charging Transition from Power Supply V t E trans = V i(t) dt = exp( ) dt R RC = CV Fall 5, Nov 3 ELEC- Lecture 8 7

18 Energy Dissipated Per Transition in Transistor Channel Resistance V -t R i (t) dt = R exp( ) dt R RC = CV Fall 5, Nov 3 ELEC- Lecture 8 8

19 Energy Stored in Charged Capacitor - t V - t v(t) i(t) dt = V [-exp( )] exp( ) dt RC R RC = CV Fall 5, Nov 3 ELEC- Lecture 8 9

20 Transition Power Gate output rising transition Energy dissipated in pmos transistor = ½CV Energy stored in capacitor = ½CV Gate output falling transition Energy dissipated in nmos transistor = ½ CV Energy dissipated per transition = ½ CV Power dissipation: P trans = E trans α f ck = ½ α f ck CV α = activity factor = prob.(gate has transition) f ck = clock frequency Fall 5, Nov 3 ELEC- Lecture 8

21 Power Density of a Chip Assume dynamic power is major component. Power density = ½ α f ck CV gate density C = average gate capacitance Gate density = number of gates per unit area Example: α =.5, f ck = GHz, C = pf, V = volt, gate density = million gates/cm Power density = 5 watts/cm Fall 5, Nov 3 ELEC- Lecture 8

22 CMOS Gate Power v i (t) R = R on V i(t) v(t) v(t) i(t) Output signal transition Dynamic current Large resistance i sc (t) Ground C i sc (t) Short-circuit current Leakage current Leakage current time Fall 5, Nov 3 ELEC- Lecture 8

23 References Delay modeling, simulation and testing: M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer,. Timing analysis and design: G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 994. N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 999. PrimeTime (A static timing analysis tool): H. Bhatnagar, Advanced ASIC Chip Synthesis, Second Edition, Springer, CMOS digital circuit power: A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Design, Boston: Springer, 995. Fall 5, Nov 3 ELEC- Lecture 8 3