Lecture 4. The CMOS Inverter. DC Transfer Curve: Load line. DC Operation: Voltage Transfer Characteristic. Noise in Digital Integrated Circuits
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1 Noise in Digital Integrated Circuits Lecture 4 The CMOS Inverter i(t) v(t) V DD Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: p.cheung@ic.ac.uk (a) Inductive coupling (b) Capacitive coupling (c) Power and ground noise Lecture 4-1 Lecture 4-2 DC Operation: Voltage Transfer Characteristic DC Transfer Curve: Load line Consider a simple inverter When Vin = 0 Vout = Vdd When Vin = Vdd Vout = 0 In between, depends on current through transistors as determined by transistor width and length By KCL, steady state condition is: I dsn = I dsp Find transfer function by solving equations, but better insight using graphical method Lecture 4-3 Lecture 4-4
2 DC Transfer Curve Operating Regions Lecture 4-5 Lecture 4-6 Effect of beta ratio on switching thresholds Noise Margins Extract switching point depends on β p / β n If β p / β n = 1, switching occurs at around Vdd/2 Otherwise: Lecture 4-7 Lecture 4-8
3 Maximize Noise Margins Voltage Transfer Characteristic of Real Inverter Select logic levels at unity gain point of DC transfer characteristic NM L (V) V M 1.0 NM H V in (V) Lecture 4-9 Lecture 4-10 The Regenerative Property Delay Definitions V in... v 0 v 1 v 2 v 3 v 4 v 5 v 6 (a) A chain of inverters. v 1, v 3,... v 1, v 3,... f(v) finv(v) finv(v) f(v) 50% t phl t plh t 90% 50% v 0, v 2,... (b) Regenerative gate v 0, v 2,... (c) Non-regenerative gate t f 10% t r t Lecture 4-11 Lecture 4-12
4 Ring Oscillator Power Dissipation v 0 v 1 v 2 v 3 v 4 v 5 v 0 v 1 v 5 T = 2 t p N Lecture 4-13 Lecture 4-14 Delay Estimation RC Delay Models Need to estimate delay without circuit simulation e.g. SPICE Not as accurate as simulation But easier to ask What if? The step response usually looks like a 1 st order RC response with a decaying exponential Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R so that t pd = RC Characterize transistors by finding their effective R depends on average current as gate switches For each MOS transistor Assume ideal switch + capacitance + ON resistance Unit nmos has resistance R, gate capacitance C Unit pmos has resistance 2R, gate capacitance C Capacitance width ON resistance 1/width Lecture 4-15 Lecture 4-16
5 Computing the Capacitances Computing the Capacitances V DD V DD V in C gd12 M2 C db2 C g4 M4 2 M1 C db1 C w Interconnect C g3 M3 Fanout Simplified Model V in C L Lecture 4-17 Lecture 4-18 Impact of Rise Time on Delay Delay as a function of V DD Assuming Vdd = 5V t phl (nsec) t rise (nsec) Normalized Delay V DD (V) Lecture 4-19 Lecture 4-20
6 Where Does Power Go in CMOS? Dynamic Power Dissipation Dynamic power charging and discharging capacitors Short circuit currents short circuit path between power rails during switching Leakage power Leaking diodes and transistors Vin Vdd C L Vout Energy/transition = C L * V dd 2 Power = Energy/transition * f = C L * V dd 2 * f Not a function of transistor sizes! Need to reduce C L, V dd, and f to reduce power. Lecture 4-21 Lecture 4-22 Short Circuit Currents Leakage Vdd Vdd Vin Vout C L Vout 0.15 Drain Junction Leakage I VDD (ma) Sub-Threshold Current V in (V) Sub-Threshold Current Dominant Factor Lecture 4-23 Lecture 4-24
7 Sub-Threshold in MOS How to reduce power? Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages ( V by 2010!) Maintaining performance by threshold scaling leads to increased leakage Reduce switching activity Reduce physical capacitance Lecture 4-25 Lecture 4-26
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