DIGITAL ELECTRONICS. A2: logic circuits parameters. Politecnico di Torino - ICT school

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1 Politecnico di Torino - ICT school A2: logic circuits parameters DIGITAL ELECTRONICS A INTRODUCTION A.2 Logic circuits parameters» Static parameters» Interfacing and compatibility» Output stages» Dynamic parameters Review of digital circuits parameters Static electrical characteristics; V/I parameters Interfacing and compatibility Output stage: OC, TP, 3S Models for the output stage Dynamic parameters: Tr, Tf, Tp; RC models for delay evaluation Reference 1: Storey, ch 14 Reference 2: 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 2

2 Digital modules Power supply and signal A digital module uses A Power Supply (V PW ) Input and out signals, represented as binary words» Groups of 1/0, in serial or parallel format DIGITAL MODULE V PW Power supply voltage V PW is (mostly) a positive voltage Some modules use several supply voltages Most usual values: 5 V; 3,3 V; 2,5 V; 1,8 V;... 0,8 V Here we analyze signals on single inputs and outputs Results usable for modules with any number of inputs and outputs V PW DIGITAL MODULE /03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 4

3 Logic states and voltage levels Output of logic circuits Logic states (0/1, L/H) are represented by electric quantities (usually voltages: V) The logic state voltage assignment is arbitrary positive logic : 1 V H ; 0 V L negative logic : 0 V H ; 1 V L In this course state 1, H : electric level High, most positive voltage, labeled as V H state 0, L : electric level Low, most negative voltage, labeled as V L V V (1) H V L (0) SPDT switch at the output First approximation model: V H = V PW and V L = 0V () state 1, H : = V H state 0, L : = V L V PW 0V V H V PW V L 0V, 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 6

4 Input of logic circuits Input output connection Sense the logic state by comparing the input voltage with a threshold V T. comes from a logic output; and must match. > V T : state H Sensed as High state High level V H Sensed as High state < V T : state L V T Sensed as Low state Low level V L V T Sensed as Low state 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 8

5 Output levels and Input threshold IN/OUT specifications Manufacturer cannot guarantee the value of ; Two limit values are specified: H and L Manufacturer cannot guarantee the value of V T Two limit values are specified: H and L Ranges, not levels output V input > H : state H < L : state L H L H L > H : state H < L : state L Correct values for output voltages High level Low level max H L min H L MAX Allowed range for input voltage MIN 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 10

6 Connection among logic gates Compatibility of logic circuits With these ranges the input reads the correct logic states from the output voltage Compatible logic circuits can exchange logic states Inputs read in the correct way the output voltage levels. Conditions for logic compatibility: H L High level Low level H V T L L < L» Guarantees that the voltage issued by a LOW logic output is read as LOW state by logic inputs connected to that output. H > H» Guarantees that the voltage issued by a HIGH logic output is read as HIGH state by logic inputs connected to that output. To guarantee compatibility in any condition :» use Lmax,Hmin,Hmin, Lmax 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 12

7 An example of (in)compatibility Output A drives 1 and 2 inputs with the voltage V Input 1 senses V as High state (V > H2 ) Input 2 may read V as High or Low state» If V T between V and H2, it is sensed as Low A V 1 2 V H L Output A Input 1 Input 2 18/03/ DigElnA DDC H1 L1 H2 L2 Logic families We have seen that different devices use different voltages ranges for their logic levels. They also differ in other characteristics In order to assure correct operation when gates are interconnected they are produced in families. Digital circuits which belong to the same family have compatible IN/OUT V and I levels. A2.14 Storey, Electronics: A Systems Approach, 3 rd Edition Pearson Education Limited DDC Storey DDC Storey 14

8 Actual signals Noise margins Noise and interferences modify the output voltage. Interconnection (group D) The gaps H - H, and L - L guarantee correct sensing of the logic state, even with noise output High level H V input MAX H L The output ranges become wider H V T L The gap is called noise margin: NM H = H - H NM L = L - L Noise margin L Low level H L Undefined logic state MIN 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 16

9 Digital signal recovery A2: logic circuits parameters All digital inputs compare with a threshold The input circuit verifies if >< V T DIGITAL MODULE Vin INPUT V H /V L CIRCUIT LOGIC OPERATOR Vout H OUTPUT CIRCUIT Vout Review of digital circuits parameters Static electrical characteristics; V/I parameters Interfacing and compatibility Output stage: OC, TP, 3S Models for the output stage Dynamic parameters: Tr, Tf, Tp; RC models for delay evaluation The output issues voltages external to H -L L V T Vin 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 18

10 Logic inverter with MOS transistor Inverter transcharacteristic Structure: V GS = nmos (used as Switch) towards R PU towards power supply Behavior: 0V < V TH (state I = L)» MOS OFF, SW open» V U (state U = H) V PW = > V TH (state I = H)» MOS ON, SW closed I SWn» V U 0V (state U = L) R PU G R PU D S V PW MOSn U Basic inverter ( ) transcharacteristic. R PU VO MOSn Input voltage Vi 0V; output Vo Val Input voltage Vi Val; output Vo 0V Intermediate levels; undefined logic state 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 20

11 Simplified equivalent output circuit Refined equivalent output circuit Low state: output to ground High state: through R PU Low state: partition of (R ON << R PU ) High state: through R PU R PU R PU R PU R PU R ON I OFF 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 22

12 Inverter with load Complementary MOS inverter Output parameters: Val = 5 V Rpu = 10 kω Ron = 100 Ω Ioff = 100 na Evaluate Vo (for L and H states) No-load Load 10 kω towards Load 3 kω towards Val, and towards 3V Load 1 kω towards Val, 3V, Load 300Ω towards Val, 3V, CMOS structure Combination of nmos (towards ) and pmos (towards Val)» Output = 1 when I = 0 (SWp closed, SWn open)» Output = 0 when I = 1 (SWp open, SWn closed) I MOSp D U I U D MOSn I U 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 24

13 CMOS inverter: characteristic Features of CMOS inverter V GSp G V GSn Sp Sn Dp Dn V GSn = < V THn MOSn fully OFF V GSp = - < V THp MOSp fully ON V THn Mixed case; both MOSn and MOSp partially ON 0-0 I D V THp 0 V GSn = V GSp = - V GSn = > V THn MOSn fully ON V GSp = - > V THp MOSp fully OFF Fully symmetric structure The MOS/SW pair operate as a unique SPDT switch which brings the output to or to the power supply. No pull-up or pull-down resistor Symmetric behavior in H and L states I U I SWp SWn U I U 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 26

14 CMOS inverter transcharacteristic Current CMOS devices Compared with R-SW Symmetric More steep Actual circuits have very steep transcharacteristic G S S D D Input 0V; Output Intermediate voltage, undefined logic behavior Input ; Output 0V Input voltages are interpreted as H/L comparing the level with a threshold V T > V T H < V T L Threshold voltage V T < V T L H > V T H 0V L 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 28

15 H and L parameters Example: logic inverters V T changes with power supply, temperature,. V T does not have a precise value Manufactures can guarantee a range for V T : L.H H 45 tangents Transcharacteristic of a CMOS device (74HC04) C: Val = 5V D: Val = 3V V H output and Threshold V T change with Val >H logic state H < L logic state L L < < H Undefined logic state L L State L V T??? H State H No change of V T! Transcharacteristic of a BJT logic gate (74LS04) A: Val = 5V B: Val = 3V 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 30

16 CMOS equivalent circuit Logic circuits output types The output MOS have an equivalent resistance R O Different towards or Val (nmos and pmos) Totem Pole (TP) Standard type, 2 switches/transistors R OH R OL Open Collector/Open Drain (OC/OD) Only the SW towards, high state from a pull-up resistor Allow to get logic operators by wiring (WIRED LOGIC) Used to collect multiple signaling on a single wire (interrupts) Three State (3-S) L, H + high Z (open) Require Enable command Allow to put on the same line several outputs Used for microcomputer buses 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 32

17 Open Collector (Open Drain) output Open Collector/Drain model Output stage with a single switch (MOS or BJT) towards SW closed: Out to out state: L SW open: Out hig Z out state: depends from external circuit No collision In Out Out The output MOS forces the low level by connecting the output to L = 0V Whe the MOS is OFF, goes to the high level thanks to an external pullup resistor R PU H = SW L R PU SW L R PU VO 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 34

18 OC model with Ron Logic operators with O.C. MOS switches have ON resistance For correct (static) operation R ON << R PU Strong asymmetry of the equivalent resistance Ro in the H and L states SW L R ON R PU OC outputs can be used to build logic operators L node is LOW if at least one among SW (A, B) is closed 1 any SW closed Logic operator: NOR out = 0 when at leastone of the inputs = 1 WIRED OR Application: Interrupt request line A In1 In2 B L R PU L 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 36

19 Wired-AND operation Totem Pole and 3-state outputs The TP output has a single command MOSp MOSp MOSn MOSn The 3S output has two commands, and uses two control variables A2.37 Storey, Electronics: A Systems Approach, 3 rd Edition Pearson Education Limited /03/ DigElnA DDC 2009 DDC Storey DDC Storey 38

20 3 State output model Model for 3-S outputs with Enable SW H H Z L SPDP switch (SW L, as for TP) + SPST switch (SW E ) to Enable/disable the output SW L SW E OE SW L Two SPST switches use independent commands If both switches are open, (ENABLE = 0), the output SPDT has a new state Z. With output = Z, the logic state depends from external circuits. The model points out the operation of the OUT ENABLE (OE) command The output logic state (H/L) depends from SW L The electric state (Active/HighZ) depends from SW E The Enable command can be shared by several outputs 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 40

21 Application of three-state outputs Output current: state H A control unit issues mutually exclusive enable signals (only one at a time) The control unit knows which output should be enabled Application examples: Memory or register reading Multiplexer Cannot be used if the pre-selection is not available Example: interrupt In1 In2 In3 OE1 OE2 OE3 Enable control L OEi A High output drives a load to Current I O < 0 Voltage depends from current I O : = + R OH I O For correct operation > H, To get > H, I O > I OH R OH Actual,I O I O R L I OH R L H I O 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 42

22 Output current: state L Operating areas A Low output drives a load to V PW Current I O < 0 Voltage depends from current I O : = R OL I O For correct operation < L, To get < L, I O < I OL R OL I R O C VP L R C I OL W Actual,I O I O For correct operation ( external to L /H ), the current I O must be within the I OL - I OH limits High state I OH L V PW H Low state I OL Too high I O current I O < I OH Correct operation I O > I OL I O 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 44

23 Input and output static parameters Logic compatibility check H : maximum value of the threshold V T Input voltages > H are interpreted as H state L : minimum value of the threshold V T Input voltages < L are interpreted as L state H : high state minimum output voltage State H: > H, as long as I O < I OH L : low state maximum output voltage State L: < L, as long as I O < I OL Separate analysis for Low and High states Verify voltage levels compatibility L < L ; H > H Evaluate output currents for Low and High states adding Input currents of connected logic circuits I IL, I IH Load currents» Low state: loads connected to V PW» High state: loads connected to Verify current compatibility Low state: I O < I OL ; high state: I O > I OH 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 46

24 Dynamic parameters of signals Dynamic parameters of modules Rise time and Fall time Defined from 10% to 90% of swing Delays from input to output (propagation time t P ) Reference level: 50% of H - L swing V H H L (H + L )/2 t V L 10 0 t f t r t H L t PHL t PLH t 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 48

25 From CMOS data sheet Origin of delays and linear model t r, t f t TLH, (transition time L H, H L) The label defines the direction of change Delays and edge slope depends on reactive parameters (L and C) Actual circuit have nonlinear, II-order behavior Linear, I order models can be used for a first approximation analysis Delays among modules: t D Delays inside modules: t P 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 50

26 Delay RC model: L H transition Delay RC model: H L transition Thevenin network (V A, R OH ) for the output R I C I at input V A output R OH V B B input CI R I Thevenin network (V A =0, R OL ) for the output R I C I at input output R OL V B B input CI R I The state change (L H) is sensed when V B crosses V T (transmission delay t DLH ) H L V A V B t DLH V T t The state change (H L) is sensed when V B crosses V T (transmission delay t DHL ) H L V A V B t DHL V T t 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 52

27 Delay evaluation R/SW output circuit The state change delay t DXY Can be evaluated from V(t) and static electric parameters Variable delay, depending on C, V T, and other parameters Specs define maximum delay for a maximum capacitive load» Minimum delay is unknown; may be assumed = 0 H V T1 L V t DLH2 V T2 t For correct (static) operation R OL << R PU Strong asymmetry of the equivalent resistance Ro in the H and L states Strong asymmetry of the time constant Ro x C in the H and L states V A R PU R ON B B C C t DLH1 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 54

28 Delays in R/SW structures CMOS logic output Asymmetric waveform Fast H L transient (τ HL = C R OL //R PU ) Slow L H transient (τ LH = C R PU ) Slow L H transient τ LH = C R PU τ LH >> τ LùHL Fast H L transient τ HL = C R OL //R PU R OL << R PU The equivalent output resistance Ro is: R OH for state H R OL for state L R OL and R OH have similar values R OH R OL SW H SW L C 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 56

29 Delays for CMOS structure Effect of load Same approach as R/SW, but now R OH R OL Same time constants: τ LH τ HL Symmetric transitions TP output: Small resistors, fast transitions symmetric time constants OC output: asymmetric time constants V H V L τ LH = C R OH τ HL = C R OL t The equivalent total capacitance C T depends from the number of connected inputs: C T = sum (C I ) With many connected inputs: Delay and transition time go up Transitions becomee slower (may cause multiple state change) The maximum number of inputs which can be driven by a single output is limited by capacitive loading V A R O B input C I1 C I2 R 1I R I2 CMOS: very high input resistance 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 58

30 Fan out Lesson A2: final test The maximum number of inputs which can be connected to an output is the FAN OUT Fan Out depends from Static compatibility (max output & input currents, loads) Dynamic compatibility (delays, rise/fall times) In CMOS circuits the input current is very small (I I 0) Each input adds a parasitic capacitor Fan out is limited by capacitive loading Describe the specific features and benefits of digital signals. Explain the compatibility among logic circuits Define the noise margin Is it possible to measure H e L from a single device? Explain the asymmetry of rise/fall times in a R-SW gate Which parameters influence the delays in CMOS circuits? 18/03/ DigElnA DDC 18/03/ DigElnA DDC 2009 DDC Storey DDC Storey 60