Digital Electronics. Assign Ò1Ó and Ò0Ó to a range of voltage (or current), with a separation that minimizes a transition region.

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1 Digital Electronics Assign Ò1Ó and Ò0Ó to a range of voltage (or current), with a separation that minimizes a transition region Positive Logic Logic 1 Negative Logic Logic 0 Voltage Transition egion Transition egion Logic 0 Logic 1 We will use positive logic (usually the case) Simplest binary function: inversion A B A B Circuit must take the Ò1Ó voltage range at the input and deliver the Ò0Ó voltage range at the output.

2 An Ideal Inverter Voltage transfer curve for an inverter -- it should yield 0 V when a high voltage is input and the high voltage, V, when a low voltage is input. An ideal inverter would be very forgiving of imperfect input voltages... >V M = V / 2 --> = 0 V < V M = V / 2 --> = V Note that the ideal inverter returns correct logical outputs (0 V or V ) even when the input voltage is corrupted by noise, voltage spikes, etc. that are nearly half the supply voltage! V V = V /2 0 0 V V M = 2 V (a) (b)

3 eal Inverters The inverters which we can build are approximations to the ideal inverter. A typical inverter characteristic is: V MAX V OH V M = 1 V OL V MIN 0 0 V IL V M V V IH On the output and input axes, several voltages are deþned: V M = voltage midpoint where = = V M. V OL = Òvoltage output lowó = max. output voltage for a valid Ò0Ó V OH = Òvoltage output highó = min. output voltage for a valid Ò1Ó V IL = Òvoltage input lowó = smaller input voltage where slope equals -1 V IH = Òvoltage input highó = larger input voltage where slope equals -1 V MAX = for = 0 V; usually, V MAX = V, the supply voltage V MIN = for = V and is the minimum output voltage

4 Noise Margins Digital electronic circuits consist of series of logic gates; the voltage signals are contaminated by ÒnoiseÓ -- actually, mostly generated by capacitive coupling from other parts of the circuit 1 v NOISE 2 V OH1 V OH2 V IH1 NM H V IH2 Voltage V IL1 V OL1 NM L V IL2 V OL2 NM H = V OH V IH NM L = V IL V OL Output of inverter #1 is at least V OH1 (assuming it had a valid low input 1 < V IL1 ); therefore, thereõs a margin of V OH1 - V IH2 to spare before the input to inverter #2 has an invalid high input. For the case of cascaded identical inverters, we deþne noise margins NM H = V OH - V IH = noise margin (high) NM L = V IL - V OL = noise margin (low)

5 Inverter Circuits: NMOS-esistor Pull-Up First example: motivate the concept of a MOSFET switch enabling an approximation to the inverter. V DD C L _ V DD = 5 V (typically) C L = load capacitance (from interconnections and from other inverters connected to the output V BS = 0 V -- bulk-to-source short-circuit is assumed to be present unless indicated otherwise

6 Finding the Voltage Transfer Curve Approach 1: start with = 0 and increase it; Þgure out the operating regions for the MOSFET and substitute I D = I D (V GS, V DS ) = I D (, ) and Þnd Approach 2: use a graphical technique = V DD Ð I D >> we know I D (, ) from the MOSFETÕs drain characteristics >> we can Þnd another equation relating I D and from KVL -- = V DD - I D I D = (V DD - ) / load line we donõt care what goes here! I D V _ DD Intersections between the family of drain characteristics and the load line yield as a function of

7 Voltage Transfer Curve using Load Line Technique Graphical intersection of I D versus characteristics with load line I D V DD V DD * Given µ n C ox = 50 µa/v 2, (W/L) = 4.5/1.5 = 3, V Tn = 1.0 V, and λ n = 0 (V) Inverter Characteristics = 5 kω = 25 kω (V)

8 Improved Inverters First try: quantify how increasing the resistor affects the slope of the voltage transfer curve at the midpoint (a measure of the steepness of the transition region) dv OUT dv IN V M = A v From our small-signal modelling concepts, this slope is equal to the ratio of the small-signal voltages v out and v in v out = A v v in How to Þnd v out / v in? Use the small-signal model! Small-signal model of the battery V DD --> a short circuit! Why? v DD = V DD v dd... by deþnition, an ideal battery has v DD = V DD which implies that v dd = 0.

9 Small-Signal Model of Inverter *Finding the small-signal circuit, neglecting capacitors: replace with small-signal model V M v OUT = v out short V _ DD v in _ = V M _ short C L * No backgate effect generator included since v bs = 0 * g m and r o are evaluated at the bias point: V GS = V M and the corresponding I D. g v out v in g m v gs r o _ s

10 Small-Signal Analysis Solving for the small-signal voltage gain -- the slope of the transfer curve at = V M : v out = Ðg v m ( r o ) Ðg m = in A v where we have assumed that << r o, which is reasonable for small λ n The transconductance is a function of the DC drain current, which is in turn a function of through the load line equation: g m 2µ n C ox ( W L)I D 2µ n C ox ( W L) V DD Ð V M = so that A v Why not increase to say 500 kω? The answer lies in the dynamic response of the inverter. Tiny DC drain currents --> very slow transitions Therefore, we want to have a large A v with a large I D...

Digital Electronics. Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region. Positive Logic.

Digital Electronics. Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region. Positive Logic. Digital Electronics Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region Positive Logic Logic 1 Negative Logic Logic 0 Voltage Transition Region Transition

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