電子電路. Memory and Advanced Digital Circuits

Size: px

Start display at page:

Download "電子電路. Memory and Advanced Digital Circuits"

Laurel Heath
6 years ago
Views:

1 電子電路 Memory and Advanced Digital Circuits Hsun-Hsiang Chen ( 陳勛祥 ) Department of Electronic Engineering National Changhua University of Education chenhh@cc.ncue.edu.tw Spring 2010

2 2 Reference Microelectronic Circuits, 5th, 2004 by Sedra/Smith

3 3 Memory and Advanced Digital Circuits Combinational Sequential Two approaches Bi-stable circuit Utilize positive feedback. Storage of charge on a capacitor Refresh, clock. Dynamic sequential circuits.

4 Latches and Flip-Flops Assuming that the input impedance of G 1 is large. Figure 11.1 (a) Basic latch. (b) The latch with the feedback loop opened. (c) Determining the operating point(s) of the latch. 4

5 The SR Flip-Flop It is formed by cross-coupling two NOR gates. Figure 11.2 (a) The set/reset (SR) flip-flop and (b) its truth table. 5

6 CMOS Implementation of SR Flip-Flops Two assumption Transistor Q 5 and Q 6 supply sufficient current to pull the node down to a voltage at least slightly below the threshold of (Q 3,Q 4 )the inverter. The set signal remains high for an interval long enough to cause regeneration to take over the switching process. Figure 11.3 CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by φ. 6

7 7 Example 11.1 The CMOS SR flip-flop in Fig is fabricated in a process technology for which μ n C ox = 2.5μ p C ox =50μA/V 2, V tn = V tp =1, and V DD =5V. The inverters have (W/L) n = 4μm /2μm and (W/L) p =10μm/2μm. The four NMOS transistors in the set-reset circuit have equal ratios. Determine the minimum value required for this W/L ratio to ensure that the flip-flop will switch.

8 8 Figure 11.4 The relevant portion of the flip-flop circuit of Fig for determining the minimum W/L ratios of Q 5 and Q 6 needed to ensure that the flip-flop will switch. Example 11.1 To simplify matters, we assume that the series connection of Q5 and Q6 is approximately equivalent to a single transistor whose W/L is half the W/L of each of Q 5 and Q 6. ( ) ( ) = SD SD tp SGp ox p DS DS tn GSn ox n V V V V L W C V V V V L W C μ μ ( ) ( ) = L W 4 4 and 6 5 = = L W L W

9 A Simpler CMOS Implementation Figure 11.5 A simpler CMOS implementation of the clocked SR flip-flop. This circuit is popular as the basic cell in the design of static random-access memory (SRAM) chips. 9

10 10 Implementations of Flip-Flop Replacing the gates with their CMOS circuit realizations. Results in rather complex circuits. Circuit Design viewpoint Simpler circuits can be found.

11 D Flip-Flop Circuits As the clock goes high, the flip-flop acquires the logic level that existed on the D line just before the rising edge of the clock. Such a flip-flop is said to be Edge triggered Figure 11.6 A block-diagram representation of the D flip-flop. 11

12 A simple implementation The circuit combines the positive-feedback technique of static bistable circuits and the charge-storage technique of dynamic circuits An inherent drawback: during φ, the output of the flip flop simply follows the signal on the D input line. Using the master-slave configuration We are simply using the single MOS transistor as a shorthand notation for a series switch. Figure 11.7 A simple implementation of the D flip-flop. The circuit in (a) utilizes the two-phase nonoverlapping clock whose waveforms are shown in (b). 12

13 A master slave D flip-flop The two clock phase must be nonoverlapping 1. φ 1 is high, φ 2 is low. 2. φ 1 goes low first, ten φ 2 goes high. The nonoverlap interval should be kept reasonably short. Figure 11.8 (a) A master slave D flip-flop. The switches can be, and usually are, implemented with CMOS transmission gates. (b) Waveforms of the two-phase nonoverlapping clock required. 13

14 14 Multivibrator circuits Types of multivibrator Bistable Two stable states Monostable One stable state One quasi-stable state Astable Two quasi-stable state

15 15 A monostable multivibrator Pulse stretcher, or a pulse standardizer A one shot. Figure 11.9 The monostable multivibrator (one-shot) as a functional block, shown to be triggered by a positive pulse. In addition, there are one shots that are triggered by a negative pulse.

16 16 A CMOS Monostable circuit It is composed of two two-input CMOS NOR gates, G1 and G2, a capacitor of capacitance C, and a resistor of resistance R. Figure A monostable circuit using CMOS NOR gates. Signal source v I supplies positive trigger pulses.

17 17 Input Clamping Diode Purpose: To prevent the input voltage signal from rising above the supply voltage VDD (by more than one diode drop) and from falling below ground voltage (by more than one diode drop). Figure (a) Diodes at each input of a two-input CMOS gate. (b) Equivalent diode circuit when the two inputs of the gate are joined together. Note that the diodes are intended to protect the device gates from potentially destructive overvoltages due to static charge accumulation.

18 18 Output equivalent circuits R on ~ a few hundred ohms. Neglecting the propagation delays through G1 and G2. These delays set a lower limit on the pulse width τ, τ > (t p1 +t p2 ) Figure Output equivalent circuit of CMOS gate when the output is (a) low and (b) high.

19 19 A CMOS Monostable circuit Initial condition: G 1 o/p=1, G 2 o/p=0, v I =0, C w/o charge. Trigger pulse applied: G 1 o/p goes 0, G 2 o/p goes 1, then v I goes 0, C begin to charge toward V DD. Figure A monostable circuit using CMOS NOR gates. Signal source v I supplies positive trigger pulses.

20 A CMOS Monostable circuit ΔV 1 = V DD R R + R on Figure Timing diagram for the monostable circuit in Fig

21 A CMOS Monostable Circuit Figure Circuit that applies during the discharge of C (at the end of the monostable pulse interval T). 21

22 Structure: An Astable Circuit Two inverter-connected NOR gates, a resistor, and a capacitor. Assumption: 1. Neglecting the finite output resistance of the CMOS gate 2. Ideal clamping diodes. Figure (a) A simple astable multivibrator circuit using CMOS gates. (b) Waveforms for the astable circuit in (a). The diodes at the gate input are assumed to be ideal and thus to limit the voltage v I1 to 0 and V DD. 22

23 Structure: Connecting an odd number of inverters in a loop. Simplification: Their edges have zero rise and fall times. Period: For a loop consists of N inverters, the period is 2Nt p and frequency 1/ 2Nt p. The Ring Oscillator Figure (a) A ring oscillator formed by connecting three inverters in cascade. (Normally at least five inverters are used.) (b) The resulting waveform. Observe that the circuit oscillates with frequency 1/6t P. 23

24 Semiconductors Memories: types and architecture Computer memory Main memory The most rapidly accessible memory. The instructions in programs are executed. The random-access type. RAM, ROM, Mass storage Serial memory Disks, tapes, 24

25 25 Semiconductors Memories: types and architecture At any moment, memory chips represent the state of the art in packing density and hence integration level. Beginning with the introduction of the 1 K- bit chip in 1970, memory-chip density has quadrupled about every 3 years. At present?

26 Memory-chip Organization The bits on a memory chip are addressable either individually or in groups of 4 to 16. As an example, a 64 M-bit chip. Assume: In out subsequent discussion that all the bits on a memory chip are individually addressable. Figure A 2 M+N -bit memory chip organized as an array of 2 M rows 2 N columns. 26

27 Memory-chip Organization Structure: 1. Cell. 2. Word line row decoder. 3. Bit line column decoder. 4. Sense amplifier. - provide a full swing digital signal. *organize cell in a square or nearly square matrix. As cell number, word line, bit line length, net resistance, capacitance, cell size, cell capacitance. Transient response. - Block partition. Figure A 2 M+N -bit memory chip organized as an array of 2 M rows 2 N columns. 27

28 28 Memory Chip timing Memory access time The time between the initiation of a read operation and the appearance of the output data. Memory cycle time The minimum time allowed between two consecutive memory operation.

29 29 Random-Access Memory (RAM) Cells In order to pack a large number of bits on a chip. Smallest cell size. Minimize power dissipation. Two types of MOS RAM: Static RAMs (SRAM) Dynamic RAMs (DRAM) Both DRAM and SRAM are volatile. Most ROM are of the nonvolatile

30 Static Memory Cell Figure A CMOS SRAM memory cell. 30

31 The Read Operation Assume: the cell is storing a 1. Precharge. Before the read operation begins, the B and B lines are precharged to an intermediate voltage. Between the low and high values. Usually V DD /2 Assume: the cell is storing a 1. Figure Relevant parts of the SRAM cell circuit during a read operation when the cell is storing a logic 1. Note that initially v Q = V DD and v Q = 0. Also note that the B and B lines are usually precharged to a voltage of about V DD /2. However, in Example 11.2, it is assumed for simplicity that the precharge voltage is V DD. 31

The Read Operation Read Operation. During read operation the voltage difference of B and B. Usually, only 0.2 V or so is required for the sense amplifier to detect the presence of 1 in the cell.

32 The Read Operation Read Operation. During read operation the voltage difference of B and B. Usually, only 0.2 V or so is required for the sense amplifier to detect the presence of 1 in the cell. Nondestructive operation Matched Inverter design, inverter threshold at V DD /2. the access Tr 2~3 wider than Q N. Assume: the cell is storing a 1. Figure Relevant parts of the SRAM cell circuit during a read operation when the cell is storing a logic 1. Note that initially v Q = V DD and v Q = 0. Also note that the B and B lines are usually precharged to a voltage of about V DD /2. However, in Example 11.2, it is assumed for simplicity that the precharge voltage is V DD. 32

33 Example 11.2 Process technology: μ n C ox =50μA/V 2, μ p C ox =20μA/V 2, V tn =-V tp =1V, 2φ f =0.6V, γ=0.5v 1/2, V DD =5V. (W/L) n =4/2, (W/L) p =10/2, access transistor (W/L)=10/2, assume cell store 1, capacitance of each bit line=1pf, determine the time required to develop an output voltage of 0.2. assume that B and B lines are charged to V DD. Figure Relevant parts of the SRAM cell circuit during a read operation when the cell is storing a logic 1. Note that initially v Q = V DD and v Q = 0. Also note that the B and B lines are usually precharged to a voltage of about V DD /2. However, in Example 11.2, it is assumed for simplicity that the precharge voltage is V DD. 33

34 34 Example 11.2 I I I = μ C n ox W L 1 2 ( V V ) v v DD t1 4 1 = 50 2 Q 2 1 W = μncox VDD Vt 5 2 L Q 2 ( 5 1) v Q v Q ( v ) 2 Q Δt ( ) V t v = Q Δt = C Δ B I 5 V = = 0.4ns

35 The Write Operation Total Write Delay Time: delay time for (b) + delay time of inverter + word line delay time. Write delay << Read delay, because C B >> C Q Figure Relevant parts of the SRAM circuit during a write operation. Initially, the SRAM has a stored 1 and a 0 is being written. These equivalent circuits apply before switching takes place. (a) The circuit is pulling node Q up toward V DD /2. (b) The circuit is pulling node Q down toward V DD /2. 35

36 The Write Operation Total Write Delay Time: delay time for (b) + delay time of inverter + word line delay time. Write delay << Read delay, because C B >> C Q Figure Relevant parts of the SRAM circuit during a write operation. Initially, the SRAM has a stored 1 and a 0 is being written. These equivalent circuits apply before switching takes place. (a) The circuit is pulling node Q up toward V DD /2. (b) The circuit is pulling node Q down toward V DD /2. 36

37 Dynamic Memory Cell The industry standard One-transistor cell Only one bit line is used (SRAM both B and B) Refresh every 5ms to 10 ms Operation C s is typically 30 ff to 50 ff C B is 30 to 50 times larger Figure The one-transistor dynamic RAM cell. 37

38 38 Figure The one-transistor dynamic RAM cell. Dynamic Memory Cell Reading Operation The bit line is precharged to V DD /2 V CS =V DD -V t (stored 1), V CS =0 (stored 0) Since C B >> C S + Δ + = + V V C C V C V C DD B S DD B CS S 2 ) ( 2 + = Δ 2 DD CS B S S V V C C C V Δ 2 DD CS B S V V C C V Δ t DD B S V V C C V 2 (1) Δ 2 0) ( DD B S V C C V

39 39 Dynamic Memory Cell CS VDD ΔV ( 0) C 2 B ΔV (1) C C S B V 2 DD V t For C B =30C S, V DD =5V, and V t =1.5V ΔV(0)=-83mV and ΔV(1)=33mV In modern chips, V DD =3.3 or less The readout process is destructive

40 Dynamic Memory Cell The change of voltage is detected by sense amplifier and amplified Then restoring the capacitor signal to the proper level (refresh) Periodic refreshing of the entire memory every 5 to 10 ms The interval required to refresh the entire chip is typically less then 2% of the time between refresh cycle (98% for normal operation) Figure A differential sense amplifier connected to the bit lines of a particular column. This arrangement can be used directly for SRAMs (which utilize both the B and B lines). DRAMs can be turned into differential circuits by using the dummy cell arrangement shown in Fig

Sense amplifiers and address The memory peripheral Improving the peripheral performance can results in Denser Faster Dissipate less power decoder Figure 11.

41 Sense amplifiers and address The memory peripheral Improving the peripheral performance can results in Denser Faster Dissipate less power decoder Figure A differential sense amplifier connected to the bit lines of a particular column. This arrangement can be used directly for SRAMs (which utilize both the B and B lines). DRAMs can be turned into differential circuits by using the dummy cell arrangement shown in Fig

42 A differential sense amplifier that employs positive feedback. Directly used in SRAM, the DRAM circuit used through the dummy cell technique The signal difference can range between 30 mv to 500 mv Its output terminal and input terminal are the same The sense amplifier Figure A differential sense amplifier connected to the bit lines of a particular column. This arrangement can be used directly for SRAMs (which utilize both the B and B lines). DRAMs can be turned into differential circuits by using the dummy cell arrangement shown in Fig

The sense amplifier Structure Consists of 2 cross coupling inverter, 2 switches controlled by φ s and 3 switches controlled by φ p for precharge and equalization.

43 The sense amplifier Structure Consists of 2 cross coupling inverter, 2 switches controlled by φ s and 3 switches controlled by φ p for precharge and equalization. Q 1, Q 2 forms an inverter, and another consists of Q 3, Q 4 Q 5, Q 6 act as switches that connect the sense amplifier to ground and V DD only when data sensing action is required. Otherwise, sense amplifier is off. This conserves power. (thousands of sense amplifiers per chip.) Figure A differential sense amplifier connected to the bit lines of a particular column. This arrangement can be used directly for SRAMs (which utilize both the B and B lines). DRAMs can be turned into differential circuits by using the dummy cell arrangement shown in Fig

44 The sense amplifier Terminals x and y are both the input and the output terminals of the amplifier The amplifier is required to detect a small signal appearing between B and B, an to amplify it to provide a full-swing signal at B and B. For instance: the cell is stored 1, then The precharge and equalization circuit When φ p goes higher prior to a read operation, Any voltage difference can result in erroneous interpretation by the sense amplifier Figure A differential sense amplifier connected to the bit lines of a particular column. This arrangement can be used directly for SRAMs (which utilize both the B and B lines). DRAMs can be turned into differential circuits by using the dummy cell arrangement shown in Fig

The sequence during a read operation Precharge Word line activated Sense amplifier activated Figure 11.24 Waveforms of v B before and after the activation of the sense amplifier.

45 The sequence during a read operation Precharge Word line activated Sense amplifier activated Figure Waveforms of v B before and after the activation of the sense amplifier. In a read-1 operation, the sense amplifier causes the initial small increment ΔV(1) to grow exponentially to V DD. In a read-0 operation, the negative ΔV(0) grows to 0. Complementary signal waveforms develop on the B line. 45

Obtaining Differential Operation in Dynamic RAMs Figure 11.

46 Obtaining Differential Operation in Dynamic RAMs Figure An arrangement for obtaining differential operation from the single-ended DRAM cell. Note the dummy cells at the far right and far left. 46

47 The Raw-Address Decoder Figure A NOR address decoder in array form. One out of eight lines (row lines) is selected using a 3-bit address. 47

48 The Column-Address Decoder Figure A column decoder realized by a combination of a NOR decoder and a pass-transistor multiplexer. 48

49 A Tree Decoder Figure A tree column decoder. Note that the colored path shows the transistors that are conducting when A 0 = 1, A 1 = 0, and A 2 = 1, the address that results in connecting B 5 to the data line. 49

50 Read-Only Memory (ROM) Figure A simple MOS ROM organized as 8 words 4 bits. 50

51 Programmable ROMs Figure (a) Cross section and (b) circuit symbol of the floating-gate transistor used as an EPROM cell. 51

52 Shift in I-V Characteristic Figure Illustrating the shift in the i D v GS characteristic of a floating-gate transistor as a result of programming. 52

53 The Floating-Gate Transistor During Programming Figure The floating-gate transistor during programming. 53

54 Emitter-Coupled Logic (ECL) Feature The fastest logic circuit Trs are operated out of Saturation Avoiding storage-time delay Small logic swing Reducing time to charge and discharge the load and parasitic capacitances Using differential pair as a current switch Also known as current mode logic (CML) Figure The basic element of ECL is the differential pair. Here, V R is a reference voltage. 54

55 Emitter-Coupled Logic (ECL) The Basic Principle Biased with a constant current source When v i is greater than V R by about 4 V T, v O1 =V CC -IR C, V O2 =V CC When v i is lower than V R by about 4 V T, v O1 =V CC, V O2 =V CC -IR C V OH =V CC, V OL =V CC -IR C Output logic swing: IR C Figure The basic element of ECL is the differential pair. Here, V R is a reference voltage. 55

Emitter-Coupled Logic (ECL) Additional Remark Differential pair less susceptible to picked-up noise (particular, an interfering signal will tend to affect both sides) Constant current consumption, no

56 Emitter-Coupled Logic (ECL) Additional Remark Differential pair less susceptible to picked-up noise (particular, an interfering signal will tend to affect both sides) Constant current consumption, no supply current spikes The output signal levels are both reference to V CC, Let V CC =0, V OH =0 and V OL =-IR C Need a level shifting to make the output signal levels compatible to the input. Complementary outputs are available, simplified the logic design. Figure The basic element of ECL is the differential pair. Here, V R is a reference voltage. 56

57 57 ECL Families Gate delays Power dissipation DP ECL 10K 2 ns 25 mw 50 pj ECL 100K 0.75 ns 45 mw 30 pj The 10K series is easier to use, the rise and fall times are deliberately made longer, thus reducing signal coupling, or crosstalk.

58 The Basic Gate Circuit =-1.32 Figure Basic circuit of the ECL 10K logic-gate family. 58

59 The Basic Gate Circuit =-1.32 The value of this reference voltage is made to change with the temperature in a predetermined manner to keep the noise margins almost constant. Also, the reference voltage VR is made relatively insensitive to variations in the power supply voltage VEE. Figure Basic circuit of the ECL 10K logic-gate family. 59

60 60 Exercise Figure E11.18

61 Figure The proper way to connect high-speed logic gates such as ECL. Properly terminating the transmission line connecting the two gates eliminates the ringing that would otherwise corrupt the logic signals. (See Section ) 61

62 Voltage Transfer Curve Assume B is low, Q B is off V BE =0.75 at I E =1mA Add 50Ω termination load Figure Simplified version of the ECL gate for the purpose of finding transfer characteristics. 62

63 Voltage Transfer Curve Figure Simplified version of the ECL gate for the purpose of finding transfer characteristics. 63

64 Voltage Transfer Curve Assume that at point x, Q A is conducting 1% of I E I I E E Q Q R A = 99 V BE Q VBE Q = VT ln 99 = 115mV R A V IL = = V Assuming Q A, Q R to be match V IH V = V V = R R IL V IH Figure The OR transfer characteristic v OR versus v I, for the circuit in Fig

Voltage Transfer Curve To Obtain V OL I E = = V R V BE R E Q + V EE 1.32 0.75 + 5.2 0.779 4mA R VC Q 4 0.245 = 0.

65 Voltage Transfer Curve To Obtain V OL I E = = V R V BE R E Q + V EE mA R VC Q = 0. 98V R V OL = V V C QR BE Q = 1.73V Figure The OR transfer characteristic v OR versus v I, for the circuit in Fig

66 Figure Circuit for determining V OH. 66

67 Figure The NOR transfer characteristic, v NOR versus v I, for the circuit in Fig

68 Figure Circuit for finding, v NOR versus v I for the range v I > V IH. 68

69 Figure Equivalent circuit for determining the temperature coefficient of the reference voltage V R. 69

70 Figure Equivalent circuit for determining the temperature coefficient of the reference voltage V R. 70

71 Figure Equivalent circuit for determining the temperature coefficient of V OL. 71

72 Figure Equivalent circuit for determining the temperature coefficient of V OH. 72

73 Figure The wired-or capability of ECL. 73

74 Figure Development of the BiCMOS inverter circuit. (a) The basic concept is to use an additional bipolar transistor to increase the output current drive of each of Q N and Q P of the CMOS inverter. (b) The circuit in (a) can be thought of as utilizing these composite devices. 74

75 Figure (Continued) (c) To reduce the turn-off times of Q 1 and Q 2, bleeder resistors R 1 and R 2 are added. (d) Implementation of the circuit in (c) using NMOS transistors to realize the resistors. (e) An improved version of the circuit in (c) obtained by connecting the lower end of R 1 to the output node. 75

76 Figure Equivalent circuits for charging and discharging a load capacitance C. Note that C includes all the capacitances present at the output node. 76

77 Figure A BiCMOS two-input NAND gate. 77

78 Figure Capture schematic of the two-input ECL gate for Example

79 Figure Circuit arrangement for computing the voltage transfer characteristics of the ECL gate in Fig

Electronic Circuits EE359A

Electronic Circuits EE359A Bruce McNair B206 bmcnair@stevens.edu 201-216-5549 1 Memory and Advanced Digital Circuits - 2 Chapter 11 2 Figure 11.1 (a) Basic latch. (b) The latch with the feedback loop opened.