General Structure of MOS Inverter
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1 General Structure of MOS Inverter Load V i Drive Department of Microelectronics and omputer Science, TUL
2 Digital MOS ircuits Families Digital MOS ircuits PMOS NMOS MOS BiMOS Depletion mode load Enhancement mode load static dynamic Department of Microelectronics and omputer Science, TUL
3 NMOS Gates T L T L V GG T D T D V i L V i L With enhancement mode load With depletion mode load Department of Microelectronics and omputer Science, TUL
4 NMOS Gates with Enhancement Mode Load (V GG -V TL ) 2 (V GG -V TL ) 2 Turn-off 1 1 Turn-on V T D 1. VGG<VDD+VTL - load transistor operates in saturation range 2. VGG VDD+VTL - load transistor operates in non-saturation range.v i t Department of Microelectronics and omputer Science, TUL
5 omparison of NMOS Gates (V GG -V TL ) D R E-N E-S (V GG -V TL ) E-N E-S R D V QL t V QL V T D V i Department of Microelectronics and omputer Science, TUL
6 NMOS Gates - NND and NOR T L Y T L 1 2 Y 1 2 n n Department of Microelectronics and omputer Science, TUL
7 MOS Inverter T L PMOS V i T D L NMOS Department of Microelectronics and omputer Science, TUL
8 MOS Inverter haracteristics B D E I DS =I DSn =I DSp V i V i V Tn V inv +V Tp V Tn V inv +V Tp Department of Microelectronics and omputer Science, TUL
9 Influence of β on Transfer haracteristic of MOS Inverter V inv +V Tp β=10 β=1 β=0.1 /2 V Tn β 1 Department of Microelectronics and omputer Science, TUL
10 Definition of Noise Margin slope= -1 NM H V OH NM H = V OH V IL V OH V IH V IL NM L NM L = V IL V OL V OL V OL 0 V IL V IH Department of Microelectronics and omputer Science, TUL
11 MOS Inverter Delay V i T 2 g4 /2 t dhl t dlh t gd2 db2 V i w db1 T 4 gd1 T 3 /2 T 1 g3 t Department of Microelectronics and omputer Science, TUL
12 alculation of t dhl and t dlh I DN V i T 1 /2 0 t 0 t dhl t V i T 2 I DP /2 0 t 0 t dlh t Department of Microelectronics and omputer Science, TUL
13 General Structure of MOS Gate B Pull-Up Network Y B Pull-Down Network Department of Microelectronics and omputer Science, TUL
14 MOS Pull-Down Networks Y Y B B Y B Y=B Y=+B Y=B+ Department of Microelectronics and omputer Science, TUL
15 MOS Pull-Up Networks B B Y B Y Y Y=B Y=+B Y=B+ Department of Microelectronics and omputer Science, TUL
16 MOS Gates: NND and NOR B Y=B B Y=+B Department of Microelectronics and omputer Science, TUL
17 Transistor Widths in MOS Gates 4µw B 4µw 2µw B 2µw 4µw 2µw Y=B+ D 4µw Y=+B++D 2w w w B w w D w B 2w Department of Microelectronics and omputer Science, TUL
18 Pseudo-NMOS Inverter T L slope=+1 ( =V i ) T D V i L V QL V QL V inv V i Department of Microelectronics and omputer Science, TUL
19 Pseudo-NMOS NND and NOR Gates T L Y T L 1 2 Y 1 2 n n Department of Microelectronics and omputer Science, TUL
20 MOS Transmission Gate in out in out V SS in out Department of Microelectronics and omputer Science, TUL
21 NMOS as Switch V in,ut in -V Tn out V V in SS L ut 0 t Department of Microelectronics and omputer Science, TUL
22 PMOS as Switch V in,ut V in in out ut L V Tp 0 t Department of Microelectronics and omputer Science, TUL
23 Two-Input Multiplexer Y=+B B Department of Microelectronics and omputer Science, TUL
24 Three-State Inverter in out in out in out Department of Microelectronics and omputer Science, TUL
25 D latch D Q B Q D Q Q D Q Department of Microelectronics and omputer Science, TUL
26 D Flip-Flop D master M slave Q D Q Q D M Q Department of Microelectronics and omputer Science, TUL
27 Dynamic Gates φ φ T p φ precharge evaluate Y=+B Y B B Pull-Down Network L V in ut φ T e 0 t φ Department of Microelectronics and omputer Science, TUL
28 "harge sharing" φ= T p Y T 1 L 0V T 2 1 Department of Microelectronics and omputer Science, TUL
29 ascading of Dynamic Gates φ T p1 φ T p2 Y 2 φ φ Y Y 1 T 1 T 2 L2 L1 φ T e1 φ T e2 φ φ Department of Microelectronics and omputer Science, TUL
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Practice 6: CMOS Digital Logic Digital Electronic Circuits Semester A 2012 The MOSFET as a Switch The MOSFET as a Switch We can look at the MOSFET as a Switch, passing the data between the diffusions when
grounded and device for B. Saturation C. Triode
Unit I 1. The gate voltage ( gs ) has value for the operation of n-channel enhancement MOSFET. A. Positive B. Negative. Zero D. One. MOS transistor A. has only one p-n junction B. has only two electrodes.