! Review: Sequential MOS Logic. " SR Latch. " D-Latch. ! Timing Hazards. ! Dynamic Logic. " Domino Logic. ! Charge Sharing Setup.

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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 29, 206 Timing Hazards and Dynamic Logic Lecture Outline! Review: Sequential MOS Logic " SR " D-! Timing Hazards! Dynamic Logic " Domino Logic! Charge Sharing Setup " Dynamic D- 2 Review: Sequential MOS Logic! Level-sensitive device! Positive " Output follows input if CLK high! Negative " Output follows input if CLK low Q = CLK Q + CLK In 4 Register Two Phase Non-Overlapping Clocks! Edge-triggered storage element! Positive edge-triggered " Input sampled on rising CLK edge! Negative edgetriggered " Input sampled on falling CLK edge 5 6

2 CMOS SR NOR2 CMOS SR NAND2 ACTIVE HIGH ACTIVE LOW * * * * * * 7 8 Static CMOS TG D-LATCH 8 Transistors Static CMOS TG D-LATCH 8 Transistors **Transistor level implementation using transmission gates requires fewer transistors When CK = output Q = D, and tracks D until CK = 0, the D- is referred to positive level triggered. When CK to 0, the Q = D is captured, held (or stored) in the. 9 0 D-LATCH Timing Requirements D- Metastability and Synchronization Failures latch, case) 2 2

3 Timing Issues Timing Hazards 3 4 Timing Issues Timing Issues! t su =time data (D) must be valid before CLK edge! t plogic =worst case propagation delay of logic! t c-p =worst case propagation delay of latch! t hold =time data (D) must stay valid after CLK edge! t cdregister =minimum propagation delay of latch! t cdlogic =minimum propagation delay of logic 5 6 Register from Register from Pos Neg 7 8 3

4 Register from Register from Negative edge-triggered Register Positive edge-triggered Register Pos Neg Neg Pos 9 20 CMOS D Edge Triggered Flip-Flop Impact of Non-ideal Clock on D- Operation Negative D- CLK ideal CLK non-ideal CLK t CLK + τ D t Positive D- Positive Edge Triggered D Flip-Flop = Negative D- + Positive D- Negative Edge Triggered D Flip-Flop = Positive D- + Negative D- 2 CLK & CLK CLK & CLK + τ D 22 Two-Phase Clocked D- (non-overlapping) Dynamic Logic ϕ 2 ϕ 2 t t ϕ 2 ϕ

5 Logic Comparison Overview Logic Comparison Overview word bit N2 P P2 A A_b N N3 bit_b N4 DYNAMIC LOGIC GATES: valid logic level are not steady-state op points and depend on temporary storage of charge on parasitic node capacitances. Outputs are generated in response to input voltage levels and a clock. Requires periodic updating or refresh. WL CBL BL M C S DYNAMIC LOGIC GATES: valid logic level are not steady-state op points and depend on temporary storage of charge on parasitic node capacitances. Outputs are generated in response to input voltage levels and a clock. Requires periodic updating or refresh Comparison of Logic Implementations Comparison of Logic Implementations Y Y Ratioed Ratioed Comparison of Logic Implementations Comparison of Logic Implementations Y Y Ratioed Ratioed V DD more robust

6 Dynamic CMOS Precharge Dynamic CMOS Precharge V DD Z CK A M p M e Z Z of C is complete 3 32 Dynamic (Clocked) Logic: Example Comparison of Static and Dynamic Logic ADVANTAGES? DISADVANTAGES? CK = 0 => Z =? CK = => Z =? Comparison of Static and Dynamic Logic Comparison of Static and Dynamic Logic

7 Cascaded Dynamic Logic Cascaded Dynamic Logic Domino Logic Requirements! Single transition " Once transitioned, it is done # like domino falling! All inputs at 0 during precharge " Outputs pre-charged to then inverted to 0 " I.e. Inputs are pre-charge to 0! Non-inverting gates Cascaded Domino CMOS Logic Gates Cascaded Domino CMOS Logic Gates propagating

8 CMOS Dynamic D Charge Leakage Setup D Positive levelsensitive Q C x is usually a parasitic capacitance 44 Comparison CMOS Static & Dynamic D- circuit: Static D- ϕ Data bit stored in bistable-loop when = 0 NOTE: No crosscoupled inverters) Flip-Flop Dynamic D- Data bit stored on C x when CK = V y V T0n,M3 =.0 V; V y = V T0n = V (V GD > V T0p )

9 V y V T0n,M3 =.0 V; V y V T0n,M3 =.0 V; V y = V T0n = V (V GD > V T0p ) V y = V T0n = V (V GD > V T0p ) i.e. V x can drop from V x-max = V DD V TMP to V x-min = 2.55 V due to charge leakage before V Q is effected (i.e. the output changes state) Ideas! Sequential Circuits lead to clocked circuit discipline " Uses state holding element " Prevents " Timing assumptions " (More) complex reasoning about all possible timings! Dynamic/clocked logic " Only build/drive one pulldown network " Fast transition propagation " Domino Logic allows for cascading! Have to worry about charge sharing next time Admin! HW 7 due 3/3 " Design 8 bit adder " Extra Credit: Modify design for optimized delay (Submit online before 4/) " Get up to 0 points added to your Midterm grade