Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 22, 2001

Transcription

1 Microelectronic Devices and Circuits - Spring 21 Lecture 13-1 Lecture 13 - Digital Circuits (II) MOS Inverter Circuits March 22, 21 Contents: 1. NMOS inverter with resistor pull-up (cont.) 2. NMOS inverter with current-source pull-up 3. ComplementaryMOS (CMOS) Inverter Reading assignment: Howe and Sodini, Ch. 5, 5.3

2 Microelectronic Devices and Circuits - Spring 21 Lecture 13-2 Key questions What are the keydesign trade-offs of the NMOS inverter with resistor pull-up? How can one improve upon these trade-offs? What is special about a CMOS inverter?

3 Microelectronic Devices and Circuits - Spring 21 Lecture NMOS inverter with resistor pull-up (cont.) Dynamics pull-down limited bycurrent through transistor [will studyin detail with CMOS] pull-up limited byresistor (t PLH R ) pull-up slowest V IN : LO HI R V OUT : HI LO V IN : HI LO R V OUT : LO HI pull-down pull-up

4 Microelectronic Devices and Circuits - Spring 21 Lecture 13-4 Inverter design issues: noise margins A v R R slow switching g m W big transistor (slow switching at input) Trade-off between speed and noise margin. During pull-up, need: high current for fast switching, but also high resistance for high noise margin. use current source as pull-up.

5 Microelectronic Devices and Circuits - Spring 21 Lecture NMOS inverter with current-source pull-up I-V characteristics of current source: i SUP v SUP i SUP I SUP 1 r oc _ v SUP Equivalent circuit models: i SUP v SUP I SUP roc r oc _ large-signal model small-signal model high current throughout voltage range: i SUP I SUP high small-signal resistance, r oc.

6 Microelectronic Devices and Circuits - Spring 21 Lecture 13-6 NMOS inverter with current-source pull-up: i SUP =I D load line i SUP I SUP V GS = V OUT V GS =V IN V IN V DS V GS =V T Transfer characteristics: V OUT VDD V T V IN High r oc high noise margin

7 Microelectronic Devices and Circuits - Spring 21 Lecture 13-7 Dynamics: i SUP i SUP V IN : LO HI V OUT : HI LO V IN : HI LO V OUT : LO HI pull-down pull-up Faster pull-up because capacitor charged at constant current.

8 Microelectronic Devices and Circuits - Spring 21 Lecture 13-8 PMOS as current-source pull-up I-V characteristics of PMOS: S G IDp D -IDp -IDp saturation VSGp VSGp=-VTp VSDp -VTp VSGp Note: enhancement-mode PMOS has V Tp <. In saturation: I Dp (V SG V Tp ) 2

9 Microelectronic Devices and Circuits - Spring 21 Lecture 13-9 Circuit and load-line diagram of inverter with PMOS current source pull-up: -I Dp =I Dn PMOS load line for V SG = -V B V B V OUT V IN V IN V OUT Transfer function: V OUT NMOS cutoff PMOS triode NMOS saturation PMOS triode NMOS saturation PMOS saturation NMOS triode PMOS saturation VDD V Tn V IN

10 Microelectronic Devices and Circuits - Spring 21 Lecture 13-1 Noise margin: compute V M = V IN = V OUT compute A v (V M ) At V M both transistors saturated: I Dn = W n 2L n µ n C ox (V M V Tn ) 2 And: I Dp = W p 2L p µ p C ox ( V B V Tp ) 2 Then: I Dn = I Dp V M = V Tn µ p W p L p µ n W n L n ( V B V Tp )

11 Microelectronic Devices and Circuits - Spring 21 Lecture Small-signal equivalent circuit model at V M : S2 v sg2 = g mp v sg2 r op - G2 D2 D1 G1 v in v gs1 g mn v gs1 r on v out S1 v in gmn v in r on //r op v out - - A v = g mn (r on //r op )

12 Microelectronic Devices and Circuits - Spring 21 Lecture NMOS inverter with current-source pull-up allows fast switching with high noise margins. But... when V IN =, there is a direct current path between supplyand ground power consumption even if inverter is idling. -I Dp =I Dn PMOS load line for V SG = -V B V B V OUT :LO V IN V IN :HI V OUT Would like to have current source that is itself switchable, i.e., it shuts off when input is high CMOS!

13 Microelectronic Devices and Circuits - Spring 21 Lecture Complementary MOS (CMOS) Inverter Circuit schematic: V IN V OUT Basic operation: V IN = V OUT = V GSn =<V Tn NMOS OFF V SGp = > V Tp PMOS ON V IN = V OUT = V GSn = >V Tn NMOS ON V SGp =< V Tp PMOS OFF No power consumption while idling in anylogic state.

14 Microelectronic Devices and Circuits - Spring 21 Lecture Key conclusions In NMOS inverter with resistor pull-up: trade-off between noise margin and speed. Trade-off resolved using current-source pull-up: use PMOS as current source. In NMOS inverter with current-source pull-up: if V IN = HI, power consumption even if inverter is idling. ComplementaryMOS: NMOS and PMOS switch alternatively no power consumption while idling.