CMOS Analog Circuits

Transcription

1 CMOS Analog Circuits L8B: Common Source Amplifier with Actie Load- (9.8.3) B. Mazhari Dept. of EE, IIT Kanpur

2 Problems with current design in 65k 50/ O -3.3 DD = 3.3 DD f 3dB. Although sufficient Gain can be obtained by cascading seeral such stages, a large drain resistance is difficult if not impossible to fabricate on-chip.. Because of Miller multiplication of gatedrain capacitance, a large gain results in significant deterioration of 3dB frequency. RS( Cgs Cgd ( A )) RD RL( Cgd C d b) A 5@ I 0 A DSQ f 3 db 9.5 MHz f3db MHz for RS 65 k 3. Power supply rejection ratio especially for negatie supply is ery low. 4. Coupling of input signal to the amplifier is problematic if dc bias oltage to the gate has also one terminal grounded.

3 Biasing Problem Bias R D O DD = 3.3 The problem is connecting Bias and in in series. Note that the bias oltage has to be obtained from supply oltage and is referenced to ground (meaning one terminal is ground). Similarly, the input oltage is also referenced to ground. in R D O DD = 3.3 R O The coupling capacitor means that the amplifier cannot be used at dc frequencies. Secondly, and ery low the capacitor (typical in Bias R alue required is ~μf) cannot be implemented in monolithically DD R D 3

4 We saw earlier that although gain as large as ~50 could be obtained with CS amplifier with resistie load, the resistance required was ery large. Such a large resistance can take up too much area if implemented monolithically. A solution to this problem can easily be achieed if we notice that the gain expression is deried through small signal analysis and as a result for a replacement of resistor, we require a deice which offers large small-signal (or incremental) resistance. DD DD R D r o >> bias bias S SS SS We know that a transistor in saturation offers large small-signal resistance and can thus be used as a load element. 4

5 CS Amplifier with Actie Load i x bias g m gs gs g m gs r o x i x x r o DD bias is chosen according to the desired drain current. bias is chosen according to the bias M following expression: S bias M SS ( dc ) bias O GS ( dc ) I DSQ SS bias O TN 5

6 DD bias M G gs g mb bs D S bias M g m gs S ro SS G gs g mb bs D g mb bs ro G D g m gs S in gs g mb bs o r o gmgs S 6

7 G gs g mb bs D r o in G D g mb bs g m gs S o simplification gs ro (g m +g mb ) o r o gmgs g gs S r o o simplification g m in o simplification o g m r o in /(g m +g mb ) r o g m in r r o r o (g m +g mb ) o o gm in{ ro ro } g ( ) m 7

8 DD bias M o g m in r o r o / {+(g m +g mb )r o } M S bias SS For a bias current of 0µA and (W/L) =/: r o r ; 9 0 ; g g ( g g ) r 6 3 o 3 m mb m mb o r o r r ( g g ) r g g m mb o m mb o A gm gm g ( ) m gmb gm For a bias current of 0µA and (W/L) =(W/L) =/ A =-0.7 8

9 Modest amount of gain can be obtained by making the size of drie Tr. much larger than the load transistor A g KP( W L) m IDSQ g ( ) KP( W L) I m DSQ ( W L) ( W L ) 3.3 / 00/ M.367 IDSQ 0 A ; A M Gain remains unchanged as current S increases or decreases. For example, for current of 5µA, gain is

10 DD o bias M r o g m o in /(g m +g mb ) M S bias M SS i x x g m gs gs bias r o x i x r o bias gs i x g g mb bs m gs x x r o i g g x m mb 0

11 DD? x i x r o bias?? DD M S bias M SS bias M S bias SS DD bias bias M x M ro i S bias x SS

12 bias M DD G S g mb bs ro G D g m gs D o M S bias gs s g m gs r o SS S o A g r r m o o g m s r o r o

13 bias M DD A gm ro ro n P I DSQ IDSQ IDSQ KP ( W L) I M S bias N SS DSQ n p G W/L R D O DD = 3.3 A KPN I DSQ W L DD in

14 Example. Biasing bias 3.3 / M / Take Bias current = 0µA I n DSQ ( GSN TN ) 0 AGSNQ.05 Bias.4949 p IDSQ ( SGP TP ) 0 ASGPQ.439 Bias.86 S bias M

15 Biasing is ery sensitie 3.3 I n DSQ ( GSN TN ) ( 3.3 n ) 0 A bias / GSNQ.043 M S bias M / -3.3 Bias p IDSQ ( SGP TP ) ( 3.3 p ) 0ASGPQ.399 Bias.907 A 3% increase in bias oltage bias causes NMOS to go into triode mode. 5

16 . oltage gain and output resistance g A / ; r M mn on / g A/ ; r.54m mp op S -.59 M M / -3.3 A g r r mn on op I DSQ n P n I I DSQ DSQ KP N ( ( W L ) n 69.4 I DSQ n p R r r.5m O on op 6

17 3. Output oltage Swing 3.3 DD satp / -.59 M S M / O (dc) satn max max SS -3.3 omax DD O( dc) ( satp ) HD o max O ( dc) ss ( satn) a /4 (%) o 00 in 5 GSQ T satn This expression needs to be reised because of large swings in these amplifiers 7

18 Distortion: Improed Model bias 3.3 / M / S bias M -3.3 I ( ) DSQ ids GSQ gs T (n DSQ nds) I I i I i i R ds ds O i R gs n ds O DSQ ds DSQ ( ) ( ) dsat n DSQ ds DSQ ( gs ) dsat gs ( ) dsat I R n DSQ O n DSQ Non-linearity is reduced leading to smaller distortion if ξ is significant 8

19 Negatie feedback? + - gs ids ds - i R ds ds O DSQ ( GSQ T ) ( n DSQ) I 9

20 THD (%) ( gs ) 5 0 i 0. ds dsat I DSQ gs ( ) dsat 3 0 I R n DSQ O n DSQ a sin( f t) gs o o in / dsat THD(%) c in dsat c 5for =0; c=6 for =0; 0.; c=858for 8.58 =0 0. 0

21 g m THD(%) c in dsat A g R o in m O in I DSQ RO on op GSQ r r T I n n DSQ omax3 THD c n p Min { ; ; } o max o max o max o max 3

22 S bias bias 3.3 M M / omax DD O( dc) ( satp 0.).67 / o max O ( dc) ss ( satn 0.).85 M THD(%) 4 in from simulations -3.3 dsat THD (% %) Equation y = a + b*x Adj. R-Square alue Standard Error B Intercept E-4 B Slope THD o max3 THD% c o max o max o max o max 3 n Min{ ; ; }.67 p in / dsat Harmonic distortion ti is less of aproblem here

23 / -.59 M / o s. in characteristics has good linearity S M

24 How does the actie stage fare wrt other performance parameters? S Gain / Output Resistance X M -.59 oltage Swing O / 3-dB frequency M -3.3 Noise PSRR Area 4

25 4. Frequency Response Cgdn M / f R C 3 db j j j j R ron rop.5m / C Cdbn Cgdn ( ) Cgdp Cdbp A R S M R RS -3.3 C Cgsn Cgdn ( A ) S A A m dn dp dn dp P P m C ff Cdbn.9 ff Cgdp 0.43 ff Cdbp.3 ff C 34.7 ff; C 4. 4fF gsn f 3dB 8.9 MHz for RS 0 j 3.9 MHz for R M S ff 5

26 5. Noise Analysis / M i thp r op -.59 gs r on S M / S -3.3 i flp o g mn gs i thn i fln i 4 thn i ithn ktgm ethn 4. n / Hz i 4 thn thp ktgmp ethp. n / Hz 3 g 3 gmn mn mn i k F g f ln i f ln e f ln 34. n / AF f C W L g ox eff eff mn kf gmp i f l p f p AF f p f C g ox Weff Leff mn i l e l 84.8 n / Hz@kHz e e e e e 59.8 n / Hz@kHZ ntotal thn thp fln flp 6

27 Replacement of resistor by transistor introduces more noise in the circuit S.907 / -.59 M M / e e e 85.6 n / Hz@kHZ ntotal thp flp -3.3 If PMOS is replaced by a resistor of magnitude r op then r op S M / S 4kT i i thn thr ethn.87 n / Hz r g op Do not think of Load Transistor as simply a resistor of alue r op! There are important differences between a resistor and a transistor that one should be aware7 of mn