QUESTION BANK for Analog Electronics 4EC111 *

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1 OpenStax-CNX module: m QUESTION BANK for Analog Electronics 4EC111 * Bijay_Kumar Sharma This work is produced by OpenStax-CNX and licensed under the Creative Commons Attribution License 4.0 Abstract This is a collection of numerical questions likely to be asked in Final Semester Examination. Questions Bank of 4EC111-Analog Electronics BASIC MOS & BJT ELECTRONICS 1. With the knowledge that µp = O.4µn what must be the relative width of n-channel and p-channel devices if they are to have equal drain currents when operated in the saturation mode with overdrive voltages of the same magnitude? Solution: Figure 1 Cancelling the terms we get: Figure 2 * Version 1.1: Apr 24, :28 am

2 OpenStax-CNX module: m A particular enhancement MOSFET for which V t =1 V and k n W/L = 0.1 ma/v 2 is to be operated in the saturation region. If I D is to be 0.2 ma, nd the required Vgs and the minimum required Vds* for pentode operation.repeat for i d = 0.8 ma. 1. A particular n-channel enhancement MOSFET is measured to have a drain current of 4 ma at V gs = Vds = 5 V and of 1 ma at Vgs = Vds = 3 V. What are the values of kn (W/L) and V t for this device? Solution: There are two equations and two unknowns. simultaneous equations. Hence two unknowns will be calculated from two 1. Consider an n-channel MOSFET with t ox = 20 nm, µn = 650 cm 2 /V, V t = 0.8 V, and W/L = 10. Find the drain current in the following cases: (a) V gs = 5 V and V ds = 1 V (b) V gs = 2 V and V ds = 1.2 V (c) V gs = 5 V and V ds = 0.2 V (d) V gs = V ds = 5 V Solution: Here process transconductance is not known. C OX will have to be calculated using the formula: C OX =ε/t OX where ε = ε 0 ε OX = F/m. Therefore device transconductance is given as follows: Figure 3 We have to determine as to when it is in Triode Region and when it is Pentode region and accordingly the respective equation has to be used: 1. Consider an npn transistor for which β F = 100, α R (inverse current transfer ratio)= 0. 1, and Is = A. (a) If the transistor is operated in the forward active mode with I B = 10 µa and V CB = 1 V, nd V BE, I E, and I E ' (b) Now, operate the transistor in the inverse active mode with a forward-bias voltage V BC equal to the value of V BE found in (a) and with V EB = 1 V(reverse bias). Find Ic, I B, and I E. 1. Consider a transistor for which the base-emitter voltage drop is 0.7 V at 10 ma. What current ows for V BE = 0.5 V? 1. An npn BJT with grounded emitter is operated with V BE = V, at which the collector current is 1µA. A 10 kω resistor connects the collector to a +15V supply. What is the resulting collector voltage Vc? Now, in the above question if a signal applied to

3 OpenStax-CNX module: m the base raises V BE to 705 mv, nd the resulting instantaneous collector current and instantaneous collector voltage using the exponential I C -V BE relationship. For this situation, what are V BE and V C? Calculate the incremental voltage gain v c / v be? BJT- CE,CB and CC. 8. A forward biased BIT operates as a grounded-emitter amplier between a signal source, with a source resistance of 10 kω, connected to the base and a 10Ω load connected as a collector resistance R C. In the corresponding model, gm is 40 ma/v and r is 2.5 kω. Calculate the overall voltage gain ( v ce / v s ). To what value must β be increased to double the overall voltage gain? 10. Analyze the circuit in Figure 1 to determine the voltages at all nodes and the currents in all branches. Assume β F =DC short circuit gain= β fo = incremental short circuit gain at low frequency=100. Figure 4 Figure 1. CE Amplier with two battery biasing 11. Analyze the transistor amplier shown in Figure 2 to determine its voltage gain. Assume β F = DC short circuit gain= β fo = incremental short circuit gain at low frequency =100. In this question there are two Voltage Gains: First is internal voltage gain

4 OpenStax-CNX module: m Figure 5 Second is the overall voltage gain with respect to the source voltage = v s : Figure 6 You have to specify the voltage gain you are using. We will be using the simple Hybrid-π model given in Sedra and Smith.

5 OpenStax-CNX module: m Figure 7 Figure 2. CE Amplier with two battery biasing. An incremental signal generator has been added at the input to get voltage signal amplication. 12. Analyze all the node voltages and branch currents in Figure 3. Assume β F = DC short circuit gain= β fo = incremental short circuit gain at low frequency =100.

6 OpenStax-CNX module: m Figure 8 Figure 3. Emitter Degenerate Amplier with two battery biasing. QUESTIONS FROM DIFFERENTIAL AMPLIFIER 13.THE DIFFERENTIAL AMPLIFIER IN FIG 4 USES TRANSISTOR β F = DC short circuit gain= β fo = incremental short circuit gain at low frequency =100.EVALUATE THE FOLLOWING (a. THE INPUT DIFFERENTIAL RESISTANCE (b. THE OVERALL DIFFERENTIAL VOLTAGE GAIN (vo/vsig) (c. THE WORST CASE COMMON MODE GAIN IF THE TWO COLLECTOR RESISTANCES ARE ACCURATE TO WITHIN ±1% (d. THE CMRR IN db (e. THE INPUT COMMON-MODE RESISTANCE(ASSUMING EARLY VOLTAGE V A =100v)

7 OpenStax-CNX module: m Figure 9 Figure 4.A dierential amplier with current sampling and voltage comparison introduced through Re1=Re2=150ohm By introducing R E1 = R E2 = 150Ω, we have introduced a limited amount of current-series feedback with all its concomitant advantages of improved frequency Band Width, improved linearity and improved dynamic range with less harmonic distortion and higher dierential input impedance. But for all these performance improvements gain has been sacriced. Without R E1 = R E2 = 150Ω the dierential mode gain is: Figure 10

8 OpenStax-CNX module: m With R E1 = R E2 = 150Ω, the symmetrical half circuit is emitter degenerate amplier hence its dierential mode gain = -R C1 /R E1 = FOR AN NMOS DIFFERENTIAL PAIR WITH A COMMON MODE VOLTAGE Vcm applied,as shown in Figure 5, let V DD =V SS =2.5V, k n W /L =3mA/V 2, Vth = 0.7 V, I SS = 0.2mA, R D1 = R D1 =5kohm, and neglect channel length modulation (a. Find Vov and V GS for each transisitor (b. For V CM =0, nd V S,I D1,I D2,V D1,V D2 ; (c. Repeat (b) for V CM = 1V (d. Repeat (b) for V CM = -1V (e. What is the highest value for V CM for which Q1 and Q2 remain in PENTODE REGION(saturation) (f. If current source I SS requires a min. voltage of 0.3 V to operate properly,,what is the lowest value allowed for Source Voltage and hence for V CM. Figure 11 Figure 5. NMOS dierential Amplier. 15. For the dierential amplier of Figure 6, let I EE =1mA, Vcc = 5V,V CM = -2 V, Rc = 3kohm, β=100. Assume that the BJT have V BE = 0.7V at I C =1mA. Find the voltage at the emitter and at the output V C1 =V C2?

9 OpenStax-CNX module: m Figure 12 Figure 6.BJT Dierential Amplier with Common Mode Signal. Solution: Since two half circuits are identical under CM signal therefore the two collector voltages are: Figure 13 The emitter voltage is:

10 OpenStax-CNX module: m Figure Consider the basic dierential circuit in which the transistors have β= 100 and V A = 100V, I EE = 1 ma, R E = 0.5MΩ and R c = 20kΩ Find: (a) the dierential gain to a single-ended output (C) the dierential input resistance (d) the common-mode gain to a single ended output? 17. A dierential amplier using a 600-µA emitter bias current source uses two well-matched transistors but collector load resistors that are mismatched by 10%. What input oset voltage is required to reduce the dierential output voltage to zero? QUESTIONS FROM FEEDBACK. 18. For a particular amplier connected in a feedback loop in which the output voltage is sampled, measurement of the output resistance before and after the loop is connected shows a change by a factor of 80. Is the resistance with feedback higher or lower? What is the value of the loop gain Aβ? If R of is 100 Ω, what is R o without feedback? 19. Negative feedback is to be used to modify the characteristics of a particular amplier for various purposes. Identify the feedback topology to be used if: (a) Input resistance is to be lowered and output resistance raised. (b) Both input and output resistances are to be raised. (c) Both input and output resistances are to be lowered. 20.A series-shunt feedback amplier using an ideal basic voltage amplier operates with v in = 100 mv, v f = 95 my, and v o = 10 V. What are the closed loop gain, closed loop input resistance and closed loop output impednce? 21.A series-shunt feedback amplier employs a basic amplier with input and output resistances each of 100 ohm and gain A 2000 V/V. The feedback factor β = 0. 1 V/V. Find the gain A, the input resistance R if, and the output resistance, R of of the closed-loop amplier? 22.For a particular amplier connected in a feedback loop in which the output voltage is sampled, measurement of the output resistance before and after the loop is connected shows a change by a factor of 80. Is the resistance with feedback higher or lower? What is the value of the loop gain A? If R of is 100 ohm, what is Ro without feedback? 23. A current amplier with a short -circuit current gain of 100 A/A, an input resistance of 100 ohm, and an output resistance of 1000 ohm is connected in a negative-feedback loop employing the shunt-series topology. The feedback network provides a feedback factor β = 0.1 A/A. Lacking complete data about the situation, estimate the current gain, input resistance, and output resistance of the feedback amplier.

11 OpenStax-CNX module: m A negative-feedback amplier has a closed-loop gain Af = 100 and an open loop gain A = 105. What is the feedback Factor If a manufacturing error results in a reduction of A to 103, what closed-loop gain results? What is the percentage change in Af corresponding to this factor of 100 reduction in A? QUESTIONS ON POWER AMPLIFIERS Question 25. Design a Complementary Symmetry Class B Power Amplier to deliver an average power of 20W to a speaker of 8Ω speaker. Determine V CC (V CC is taken as = V m +5V this safety margin avoids the saturation of Q1 and Q2 and suppresses harmonic distortion), V EE, I m, P S, power conversion eciency η and the power rating of Q1 and Q2. Figure 15 Solution: Power transferred to the load: Figure 16 Average power drawn from each supply is P S :

12 OpenStax-CNX module: m Figure 17 Figure 18 For determining the power rating of Q1 and Q2 we must examine the worst case scenario of heat dissipation across the individual transistors. The total maximum power dissipation is: Figure 19

EE105 Fall 2015 Microelectronic Devices and Circuits

EE105 Fall 2015 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 11-1 Transistor Operating Mode in Amplifiers Transistors are biased in flat part of