ECE 442 Solid State Devices & Circuits. 15. Differential Amplifiers
|
|
|
- Josephine Dalton
- 5 years ago
- Views:
Transcription
1 ECE 442 Solid State Devices & Circuits 15. Differential Amplifiers Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois ECE 442 Jose Schutt Aine 1
2 Background Differential Amplifiers The input stage of every op amp is a differential amplifier Immunity to temperature effects Ability to amplify dc signals Well-suited for IC fabrication because (a) they depend on matching of elements (b) they use more components Less sensitive to noise and interference Enable to bias amplifier and connect to other stage without the use of coupling capacitors ECE 442 Jose Schutt Aine 2
3 Differential Amplifiers Practical Considerations Both inputs to a differential amplifier may have different voltages applied to them In the ideal situation with perfectly symmetric stages, the common-mode input would lead to zero output Temperature drifts in each stage are often common-mode signals Power supply noise is a common-mode signal and has little effect on the output signal ECE 442 Jose Schutt Aine 3
4 MOS Differential Pair Assume current source is ideal Transistors should not enter triode region ECE 442 Jose Schutt Aine 4
5 Common-Mode Operation Input voltage v cm to both gates Difference in voltage between the two drains is zero ECE 442 Jose Schutt Aine 5
6 Differential Input Voltage Differential pair responds to differntial input signals by providing corresponding differential output signal between the two drains. ECE 442 Jose Schutt Aine 6
7 MOS Differential Pair Assume current source is ideal v ID =v gs1 -v gs2 Output is collected as v D2 -v D1 ECE 442 Jose Schutt Aine 7
8 MOS Differential Pair - If v ID is positive, v D2 -v D1 is positive v ID >0 v gs1 >v gs2 I D1 > I D2 v D1 lower voltage point than v D2 For proper operation, MOSFETS should not enter triode region ECE 442 Jose Schutt Aine 8
9 DC Analysis IRD VD 1 VDD 2 VD2 VDD I CoxW 2 I D ID VGS VT 2 2L IR 2 D V GS LI VT VSQ VT CoxW LI C W ox ECE 442 Jose Schutt Aine 9
10 Incremental Analysis 1 1 vg1 vcm v v id 2 v v 2 2 v g R ' o1 m D Neglecting the body effect v 2 in v g R ' o2 m D g cm id v 2 in R R r ' D D out A v v g R o2 o1 ' D m D vin ECE 442 Jose Schutt Aine 10
11 Frequency Response When driven by a low-impedance signal source, the upper corner frequency is determined by the output circuit f high 1 2C R out ' D ECE 442 Jose Schutt Aine 11
12 Common-Mode Rejection Ratio vo 1 vo2 RD v 1 icm vicm 2R g m SS Assume R SS >> 1/g m ECE 442 Jose Schutt Aine 12
13 Common-Mode Rejection Ratio (a) For single-ended output: v v R v v 2R o1 o2 D icm icm SS RD 1 A, A g R 2R 2 cm d m D SS CMRR A A d cm g R m SS ECE 442 Jose Schutt Aine 13
14 Common-Mode Rejection Ratio (b) For differential output: A cm v v o2 o1 0 icm v A v v g R o2 o1 d m D vid CMRR ECE 442 Jose Schutt Aine 14
15 BJT Differential Pair Assume perfect match between the devices and symmetry in the circuit ECE 442 Jose Schutt Aine 15
16 Rin 2 r Base currents: BJT Differential Pair i in i v 2 b1 in r v 2 R r R r R in ib 2 r ' C out1 c1 out2 c2 R R R vin 2 c1 c2 C r ECE 442 Jose Schutt Aine 16
17 BJT Differential Pair Incremental Model ' ' ' vr in gr m C vo 1 gmv1rc gmrc vin r 2 ' ' ' vr in gr m C vo2 gmv 2RC gmrc vin r 2 ' A g R Single-ended gain of first stage: S1 m C Double-ended differential gain (with v out =v o2 -v o1 ): A g R ' ' ' gmrc m C ' RC D gmrc 2 2 r ECE 442 Jose Schutt Aine 17
18 BJT Differential Pair General R R R B1 B2 B R R R C1 C2 C R in RB RE 2r A D ' RC R 1 r R E B ECE 442 Jose Schutt Aine 18
19 Differential Amplifiers - Observations Observations The differential pair attenuates the input signal of each stage by a factor of one-half cutting the gain of each stage by one-half The double-ended output causes the two singleended gains to be additive Thus, the voltage gain of a perfectly matched differential stage is equal to that of a single stage ECE 442 Jose Schutt Aine 19
20 Remarks on Differential Amplifiers 1. In many applications, the differential amplifier is not fed in a complementary fashion 2. Rather, the input signal may be applied to one of the input terminals while the other terminal is grounded 3. In this case, the signal voltage at the emitters will not be zero and thus the resistor R EE will have an effect on the operation 4. However, if R EE is large (R EE >> r e ) as is usually the case, v id will still divide equally between the 2 junctions 5. The operation of the differential amplifier will still be almost identical to that of the symmetrical feed and the CE equivalence can still be employed ECE 442 Jose Schutt Aine 20
21 Common Mode R R R C2 C C R C1 R C Can show that v c1 v icm RC 2R EE r e v c2 v icm R C 2R EE R r e C ECE 442 Jose Schutt Aine 21
22 BJT Diff Pair - Common Mode v v v v o c1 c2 icm RC 2R r EE e A cm RC R 2R r 2R EE e EE C A cm R 2R C EE R R C C ECE 442 Jose Schutt Aine 22
23 Example - I =100 Collector resistance accurate within 1% Early voltage = 100V ECE 442 Jose Schutt Aine 23
24 Emitter current in both transistors is: 0.5 ma r e VT 25 mv 50 I 0.5 ma E R 2 1 r R k id e E Example I (cont ) vid Rid 40 v R R 5540 sig sig id 0.8 v v o id Total resistance in the collectors Total resistance in the emitters ECE 442 Jose Schutt Aine 24
25 Example - I (cont ) vo 2RC 210 v 2 r R id e E 50 Overall differential gain: A d vo vid vo v v v sig sig id A cm common-mode gain R 2R C EE R R C C Where R C is the worst case variation in collector resistance ECE 442 Jose Schutt Aine 25
26 Example I (cont ) A cm Common-Mode Rejection ratio CMRR CMRR 20 log A A d cm CMRR log db ECE 442 Jose Schutt Aine 26
27 r o Example I (cont ) Input common-mode resistance: R icm VA k I /2 0.5 r 1 o R icm REE k k 6.7 M 2 ECE 442 Jose Schutt Aine 27
28 Example - II In the circuit shown, the dc bias current is 4 ma. If = 0.993, R B1 = R B2 = R B3 = 1,000, R E = 30, R C = 1.6 k, V CC = 10 V, and V BE(on) = 0.7 V, (a) Calculate the dc collector currents (b) Calculate the dc or quiescent collector voltages (c) Calculate the maximum peak value of vout before serious distortion results (d) Calculate the incremental differential voltage gain of the circuit (e) If the base resistor of Q2 is changed to R B2 = 400, calculate the dc collector current through each device ECE 442 Jose Schutt Aine 28
29 Example - II ECE 442 Jose Schutt Aine 29
30 Example - II (a) Assuming perfect match between Q1 and Q2, DC bias current will split equally I E1 = I E2 = 2mA. I C =I E =1.986 ma (b) The quiescent collector voltages will equal V I R V CC C C (c) Maximum collector voltage is 10 V (at cutoff) minimum is 0 V (at saturation).therefore, positive peak voltage is = 3.18 V, and negative peak is 6.82 V p-p voltage = 6.36 V ECE 442 Jose Schutt Aine 30
31 Example - II (d) The incremental differential voltage gain of the circuit is defined as: Calculate r e and A D v v v v v out o2 o1 in in r e I 2 E ECE 442 Jose Schutt Aine 31
32 AD Example - II Applying the gain equation and assuming r out >> 1.6 k gives V / V (e) The voltage at the node above the dc current source can be found from V I R V 1 I R 1 B1 B1 BE( on) B1 E V I R V 1 I R 2 B2 B2 BE( on) B2 E ECE 442 Jose Schutt Aine 32
33 Example - II Effects of non-balance ECE 442 Jose Schutt Aine 33
34 Example - II 1 I 1 I 4mA B1 B2 I B A I B A The corresponding emitter and collector currents are I E ma I E ma IC ma IC ma The two quiescent collector voltages are no longer equal, resulting in a nonzero quiescent output voltage VCQ V VCQ V ECE 442 Jose Schutt Aine 34
35 Example - II V V 2 V V outq CQ CQ Nonzero quiescent voltage serious consequences when this stage is followed by additional gain stages, creating an output offset voltage when the inputs are shorted together ECE 442 Jose Schutt Aine 35
36 Nonideal Characteristics Input offset voltage of MOS differential pair Mismatch can result in a dc output voltage V o (output dc offset voltage) V os =V o /A d is input offset voltage ECE 442 Jose Schutt Aine 36
37 Nonideal Characteristics If V os is applied (differentially) at the input, a zero voltage difference should result at the output Factors contributing to dc offset voltage 1. Mismatch in load resistance 2. Mismatch in W/L 3. Mismatch in V T V os 2 V / ov RD V W L ov V W / L 2 T 2 ECE 442 Jose Schutt Aine 37
38 Input Offset Voltage for BJT Diff Pair Offset results from 1. Mismatch in RC s 2. Mismatch in 3. Mismatch in junction area V os V T 2 2 R C I S R I C S ECE 442 Jose Schutt Aine 38
39 Offset Current for BJT Diff Amp In a perfectly symmetric differential pair, the 2 input terminals carry equal dc current to support bias I /2 IB 1 IB2 1 Mismatches (primarily from ) make the 2 input dc currents unequal I I I I os B1 B2 os IB ECE 442 Jose Schutt Aine 39
40 Differential-to-Single-Ended Conversion - Beyond first stage, signal can be converted from differential to single-ended - Simply ignore the drain current in Q 1 and eliminate its drain resistor ECE 442 Jose Schutt Aine 40
41 Differential-to-Single-Ended Conversion Limitations Factor of 2 (6 db) is lost in the gain if drain current of Q 1 is not used Much better approach consists of using drain current of Q 1 Active load approach allows to perform conversion without loss of gain by making use of drain current in Q 1 ECE 442 Jose Schutt Aine 41
42 MOS Differential Amp with Active Load Replacing drain resistances with current sources, results in much higher voltage gain and savings in chip area in diff amp ECE 442 Jose Schutt Aine 42
43 MOS Differential Amp - Equilibrium ECE 442 Jose Schutt Aine 43
44 MOS Differential Amp with Active Load Current mirror action makes it possible to convert the signal to single-ended form without loss of gain. The differential gain is: v A g r r o d m o2 o4 vid If r r r o2 o4 o A d 1 2 g r m o ECE 442 Jose Schutt Aine 44
45 MOS Differential Amp with Active Load The active-loaded MOS differential amplifier has a low common-mode gain high CMRR The common-mode gain is: A cm vo 1 ro4 v 2R 1 g r icm SS m3 o3 Usually, g r 1 and r r A cm m3 o3 o3 o4 2g 1 R m3 SS R SS is internal impedance of current source ECE 442 Jose Schutt Aine 45
46 MOS Differential Amp with Active Load Since R SS is large, A cm will be small A 2 d CMRR gm ro2 ro4 gm3rss A cm If r r r and g g o2 o4 o m3 m CMRR g mro gmrss ECE 442 Jose Schutt Aine 46
47 BJT Differential Amp with Active Load Current mirror & active load Differential stage ECE 442 Jose Schutt Aine 47
48 Active Loaded BJT Pair Incremental Model Virtual ground develops at common-emitter terminal ECE 442 Jose Schutt Aine 48
49 BJT Differential Amp with Active Load Output resistance is parallel equivalent of the output resistance of the differential pair and the output resistance of the current mirror The differential gain is: v A g r r o d m o2 o4 vid If r r r A o2 o4 o d 1 2 g r m o The differential input impedance is: R id 2 r ECE 442 Jose Schutt Aine 49
50 BJT Differential Amp with Active Load The active-loaded BJT differential amplifier has a low common-mode gain high CMRR The common-mode gain is: A cm v v o icm r R 3 o4 EE It is assumed that g g, m3 m4 and r r and r r, r 4 3 o3 3 4 R EE is internal impedance of current source ECE 442 Jose Schutt Aine 50
51 BJT Differential Amp with Active Load A CMRR g r r A d 3 EE m o2 o4 cm R ro 4 If r r r o2 o4 o CMRR 1 3gmR 2 EE For large CMRR, bias current source should have large output resistance R EE ECE 442 Jose Schutt Aine 51
52 Frequency Response of MOS Diff Amp Resistively Loaded 1. Resistance R SS is between node S and ground 2. Capacitance C SS is between node S and ground 3. C SS includes C db, C gd, and C sb ECE 442 Jose Schutt Aine 52
53 Frequency Response Differential Half Gain function of differential half will be identical to that of common-source amplifier ECE 442 Jose Schutt Aine 53
54 Frequency Response Common-Mode C SS /2 will form dominant real axis zero at much lower frequency Zero dominates frequency dependence of A cm Common-mode gain is found by analyzing the effect of a mismatch R D in R D ECE 442 Jose Schutt Aine 54
55 Frequency Response Common-Mode R D R D A () s 1sC R 2RSS RD cm SS SS A cm picks up a zero on the negative real axis of the complex s-plane. The frequency is Z Z 1 C R SS SS f Z 1 2C R SS SS ECE 442 Jose Schutt Aine 55
56 Frequency Response Common-Mode Gain ECE 442 Jose Schutt Aine 56
57 Frequency Response Differential Gain ECE 442 Jose Schutt Aine 57
58 Frequency Response CMRR ECE 442 Jose Schutt Aine 58
59 Frequency Response Actively Loaded MOS C C C C C C m gd1 db1 db3 gs3 gs4 C C C C C C L gd2 db2 gd4 db4 load Capacitance at input node Capacitance at output node ECE 442 Jose Schutt Aine 59
60 Frequency Response Actively Loaded MOS Cm 1 s v 1 o 2g m3 Ad() s gmro vid 1 sc C LRo m 1 s g 1 m3 First pole: fp 1 2C R Second pole: Zero at: f P2 L o g g 2 C 2 2C m3 m3 f Z m 2g 2C m3 m f T gs3 ECE 442 Jose Schutt Aine 60 f T /2 Mirror pole and zero occur at very high frequencies
61 Actively Loaded MOS - Transconductance ECE 442 Jose Schutt Aine 61
62 CMOS OP Amp Example In the differential amplifier shown, Q 1 and Q 2 form the differential pair while the current source transistors Q 4 and Q 5 form the active loads for Q 1 and Q 2 respectively. The dc bias circuit that establishes an appropriate dc voltage at the drains of Q 1 and Q 2 is not shown. The following specifications are desired: differential gain A d = 80V/V, I REF = 100 A, the dc voltage at the gates of Q 6 and Q 3 is +1.5V; the dc voltage at the gates of Q 7, Q 4 and Q 5 is 1.5V. The technology available is specified as follows: n C ox =3 p C ox = 90A/V 2 ; V tn = V tp =0.7V, V An = V Ap = 20V. Specify the required value of R and the W/L ratios for all transistors. Also, specify I D and V GS at which each transistor is operating. For dc bias calculations, you may neglect channel-length modulation. Fill in the entries in the table provided to show your results. ECE 442 Jose Schutt Aine 62
63 CMOS OP Amp Example ECE 442 Jose Schutt Aine 63
64 CMOS OP Amp Example 1.5 ( 1.5) 3V I REF 100 A R 30k R 0.1mA Drain currents are determined by symmetry and inspection V GS values are also determined by inspection for all transistors except Q 1 and Q 2. To determine V GS for Q 1 and Q 2, we do the following: the equivalent load resistance will consist of r o1 in parallel with r o4 for Q 1 and r o2 in parallel with r o5 for Q 5. Since the r o s are equal, this corresponds to r o /2. We have: ro 2Ad 280 gm Ad gm 0.4 ma / V 2 r 400k o ECE 442 Jose Schutt Aine 64
65 CMOS OP Amp Example g m 2ID 2ID Vov V g 0.4 ov Take polarity into account for PMOS m 0.25 V GS 1, VT 0.95 To find W/L ratios, use W 2 W 2I D ID Cox ( VGS VT) 2 L L C ( V V ) ox GS T taking into account PMOS and NMOS devices separately 2 ECE 442 Jose Schutt Aine 65
66 CMOS OP-AMP DESIGN TABLE Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Units C ox A/V 2 I D A V GS V W/L ECE 442 Jose Schutt Aine 66
67 2-Stage CMOS Op Amp ECE 442 Jose Schutt Aine 67
68 2-Stage CMOS Op Amp Two-stage configuration with two power supplies which can range from +/- 2.5 V for 0.5 m technology to +/- 0.9 V for 0.18 m technology. I REF is generated either externally or using on-chip CKT. Current mirror formed by Q 5 -Q 8 supplies differential pair Q 1 -Q 2 with bias current. The W/L of Q 5 is selected to control I. The diff pair is actively loaded by current mirror Q 3 -Q 4 ECE 442 Jose Schutt Aine 68
69 2-Stage CMOS Op Amp Second stage is Q6 which is a CS amplifier for which Q7 is the current source. A capacitor Cc is included for negative feedback to enhance the Miller effect through Q6 compensation. This op amp does not have a low output impedance and is thus not suited for driving a lowimpedance load. The W/L ratios are given and listed below: Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 W/L 20/0.8 20/0.8 5/0.8 5/0.8 40/0.8 10/0.8 40/0.8 40/0.8 Let I 90 A, V 0.7 V, V 0.8V REF tn tp C 160 A/ V, C 40 A/ V 2 2 n ox p ox ECE 442 Jose Schutt Aine 69
70 2-Stage CMOS Op Amp V for all devices 10 V, V V 2.5V A DD SS Voltage Gain A g r r First stage: 1 m1 o2 o4 Since Q 8 and Q 5 are matched, I = I REF, Q 1, Q 2, Q 3 and Q 4 will have I/2 = 45 A. I Q7 =I REF = 90 A = I Q6 Let V GS -V T = V ov (overdrive voltage) ECE 442 Jose Schutt Aine 70
71 2-Stage CMOS Op Amp 1 2 From I C W / L V 2 D ox ov We find V ov for each transistor. Transconductance is: g m 2I D V ov r o V I A D ECE 442 Jose Schutt Aine 71
72 2-Stage CMOS Op Amp Voltage Gain Gain for first stage: A A g r r 1 m1 o2 o / V V A g r r Gain for second stage: A / 2 m6 o6 o7 V V Overall dc open loop gain is (-33.3)(-33.3) = 1109 V/V 20 log1109 = 61 db ECE 442 Jose Schutt Aine 72
73 2-Stage Op Amp Design Table Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 W/L 20/0.8 20/0.8 5/0.8 5/0.8 40/0.8 10/0.8 40/0.8 40/0.8 I D (A) V ov (v) V GS (v) g m (ma/v) r o (k) ECE 442 Jose Schutt Aine 73
74 2-Stage Op Amp Frequency Response Incremental Circuit G g g m1 m1 m2 R r r, C C C C C C 1 o2 o4 1 gd4 db4 gd2 db2 gs6 ECE 442 Jose Schutt Aine 74
75 2-Stage Op Amp Frequency Response G g m2 m6 R r r, C C C C C 2 o6 o7 2 db6 db7 gd7 L C is the load capacitance (usually large) C C L 2 1 V G G sc RR o V 1sAs B id m1 m2 C ECE 442 Jose Schutt Aine 75
76 2-Stage Op Amp Frequency Response A CR CR C G RR R R C m B CC C C C RR 1 2 C Transmission zero at s = s Z with Z G C m2 C Two poles that are the root of the denominator 1 Gm p1 RC 1 CGm2R 2 p2 2 C 2 ECE 442 Jose Schutt Aine 76
ECE 546 Lecture 12 Integrated Circuits
ECE 546 Lecture 12 Integrated Circuits Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine 1 Integrated Circuits IC Requirements
Solid State Devices & Circuits. 18. Advanced Techniques
ECE 442 Solid State Devices & Circuits 18. Advanced Techniques Jose E. Schutt-Aine Electrical l&c Computer Engineering i University of Illinois jschutt@emlab.uiuc.edu 1 Darlington Configuration - Popular
Chapter 8 Differential and Multistage Amplifiers
1 Chapter 8 Differential and Multistage Amplifiers Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: Active-Loaded Differential Pair 4.
Chapter 12 Opertational Amplifier Circuits
1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded cascode circuit.
Microelectronic Circuits II. Ch 10 : Operational-Amplifier Circuits
Microelectronic Circuits II Ch 0 : Operational-Amplifier Circuits 0. The Two-stage CMOS Op Amp 0.2 The Folded-Cascode CMOS Op Amp CNU EE 0.- Operational-Amplifier Introduction - Analog ICs : operational
CHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS
CHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS Chapter Outline 8.1 The CMOS Differential Pair 8. Small-Signal Operations of the MOS Differential Pair 8.3 The BJT Differential Pair 8.4 Other Non-ideal
F9 Differential and Multistage Amplifiers
Lars Ohlsson 018-10-0 F9 Differential and Multistage Amplifiers Outline MOS differential pair Common mode signal operation Differential mode signal operation Large signal operation Small signal operation
Applied Electronics II
Applied Electronics II Chapter 2: Differential Amplifier School of Electrical and Computer Engineering Addis Ababa Institute of Technology Addis Ababa University Daniel D./Abel G. April 4, 2016 Chapter
Electronic Circuits EE359A
Electronic Circuits EE359A Bruce McNair B206 bmcnair@stevens.edu 201-216-5549 Lecture 12 1 MOSFET vs. BJT current-voltage characteristic 1.5 10 3 i C ( v) i D ( v) 1 10 3 500 0 2 4 6 8 10 v The drain current
The Differential Amplifier. BJT Differential Pair
1 The Differential Amplifier Asst. Prof. MONTREE SRPRUCHYANUN, D. Eng. Dept. of Teacher Training in Electrical Engineering, Faculty of Technical Education King Mongkut s nstitute of Technology North Bangkok
Building Blocks of Integrated-Circuit Amplifiers
Building Blocks of ntegrated-circuit Amplifiers 1 The Basic Gain Cell CS and CE Amplifiers with Current Source Loads Current-source- or active-loaded CS amplifier Rin A o R A o g r r o g r 0 m o m o Current-source-
EE 140 / EE 240A ANALOG INTEGRATED CIRCUITS FALL 2015 C. Nguyen PROBLEM SET #7
Issued: Friday, Oct. 16, 2015 PROBLEM SET #7 Due (at 8 a.m.): Monday, Oct. 26, 2015, in the EE 140/240A HW box near 125 Cory. 1. A design error has resulted in a mismatch in the circuit of Fig. PS7-1.
QUESTION BANK for Analog Electronics 4EC111 *
OpenStax-CNX module: m54983 1 QUESTION BANK for Analog Electronics 4EC111 * Bijay_Kumar Sharma This work is produced by OpenStax-CNX and licensed under the Creative Commons Attribution License 4.0 Abstract
4. Differential Amplifiers. Electronic Circuits. Prof. Dr. Qiuting Huang Integrated Systems Laboratory
4. Differential Amplifiers Electronic Circuits Prof. Dr. Qiuting Huang Integrated Systems Laboratory Differential Signaling Basics and Motivation Transmitting information with two complementary signals
UNIT-1 Bipolar Junction Transistors. Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press
UNIT-1 Bipolar Junction Transistors Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press Figure 6.1 A simplified structure of the npn transistor. Microelectronic Circuits, Sixth
LECTURE 19 DIFFERENTIAL AMPLIFIER
Lecture 19 Differential Amplifier (6/4/14) Page 191 LECTURE 19 DIFFERENTIAL AMPLIFIER LECTURE ORGANIZATION Outline Characterization of a differential amplifier Differential amplifier with a current mirror
Chapter 15 Goals. ac-coupled Amplifiers Example of a Three-Stage Amplifier
Chapter 15 Goals ac-coupled multistage amplifiers including voltage gain, input and output resistances, and small-signal limitations. dc-coupled multistage amplifiers. Darlington configuration and cascode
Lecture 030 ECE4430 Review III (1/9/04) Page 030-1
Lecture 030 ECE4430 Review III (1/9/04) Page 0301 LECTURE 030 ECE 4430 REVIEW III (READING: GHLM Chaps. 3 and 4) Objective The objective of this presentation is: 1.) Identify the prerequisite material
Chapter 10 Differential Amplifiers
Chapter 10 Differential Amplifiers 10.1 General Considerations 10.2 Bipolar Differential Pair 10.3 MOS Differential Pair 10.4 Cascode Differential Amplifiers 10.5 Common-Mode Rejection 10.6 Differential
Chapter 4 Single-stage MOS amplifiers
Chapter 4 Single-stage MOS amplifiers ELEC-H402/CH4: Single-stage MOS amplifiers 1 Single-stage MOS amplifiers NMOS as an amplifier: example of common-source circuit NMOS amplifier example Introduction
Objectives The purpose of this lab is build and analyze Differential amplifiers based on NMOS transistors (or NPN transistors).
1 Lab 03: Differential Amplifiers (MOSFET) (20 points) NOTE: 1) Please use the basic current mirror from Lab01 for the second part of the lab (Fig. 3). 2) You can use the same chip as the basic current
ECEN 474/704 Lab 6: Differential Pairs
ECEN 474/704 Lab 6: Differential Pairs Objective Design, simulate and layout various differential pairs used in different types of differential amplifiers such as operational transconductance amplifiers
Operational Amplifiers
CHAPTER 9 Operational Amplifiers Analog IC Analysis and Design 9- Chih-Cheng Hsieh Outline. General Consideration. One-Stage Op Amps / Two-Stage Op Amps 3. Gain Boosting 4. Common-Mode Feedback 5. Input
Field Effect Transistors
Field Effect Transistors LECTURE NO. - 41 Field Effect Transistors www.mycsvtunotes.in JFET MOSFET CMOS Field Effect transistors - FETs First, why are we using still another transistor? BJTs had a small
Integrated Circuit Amplifiers. Comparison of MOSFETs and BJTs
Integrated Circuit Amplifiers Comparison of MOSFETs and BJTs 17 Typical CMOS Device Parameters 0.8 µm 0.25 µm 0.13 µm Parameter NMOS PMOS NMOS PMOS NMOS PMOS t ox (nm) 15 15 6 6 2.7 2.7 C ox (ff/µm 2 )
CS and CE amplifiers with loads:
CS and CE amplifiers with loads: The Common-Source Circuit The most basic IC MOS amplifier is shown in fig.(1). The source of MOS transistor is grounded, also the drain resistor RD replaced by a constant-current
Applied Electronics II
Applied Electronics II Chapter 3: Operational Amplifier Part 1- Op Amp Basics School of Electrical and Computer Engineering Addis Ababa Institute of Technology Addis Ababa University Daniel D./Getachew
Radivoje Đurić, 2015, Analogna Integrisana Kola 1
OTA-output buffer 1 According to the types of loads, the driving capability of the output stages differs. For switched capacitor circuits which have high impedance capacitive loads, class A output stage
TWO AND ONE STAGES OTA
TWO AND ONE STAGES OTA F. Maloberti Department of Electronics Integrated Microsystem Group University of Pavia, 7100 Pavia, Italy franco@ele.unipv.it tel. +39-38-50505; fax. +39-038-505677 474 EE Department
Differential Amplifier : input. resistance. Differential amplifiers are widely used in engineering instrumentation
Differential Amplifier : input resistance Differential amplifiers are widely used in engineering instrumentation Differential Amplifier : input resistance v 2 v 1 ir 1 ir 1 2iR 1 R in v 2 i v 1 2R 1 Differential
Course Number Section. Electronics I ELEC 311 BB Examination Date Time # of pages. Final August 12, 2005 Three hours 3 Instructor
Course Number Section Electronics ELEC 311 BB Examination Date Time # of pages Final August 12, 2005 Three hours 3 nstructor Dr. R. Raut M aterials allowed: No Yes X (Please specify) Calculators allowed:
Advanced Operational Amplifiers
IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage
HOME ASSIGNMENT. Figure.Q3
HOME ASSIGNMENT 1. For the differential amplifier circuit shown below in figure.q1, let I=1 ma, V CC =5V, v CM = -2V, R C =3kΩ and β=100. Assume that the BJTs have v BE =0.7 V at i C =1 ma. Find the voltage
EE105 Fall 2015 Microelectronic Devices and Circuits
EE105 Fall 2015 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 11-1 Transistor Operating Mode in Amplifiers Transistors are biased in flat part of
BJT Amplifier. Superposition principle (linear amplifier)
BJT Amplifier Two types analysis DC analysis Applied DC voltage source AC analysis Time varying signal source Superposition principle (linear amplifier) The response of a linear amplifier circuit excited
Analog Integrated Circuit Configurations
Analog Integrated Circuit Configurations Basic stages: differential pairs, current biasing, mirrors, etc. Approximate analysis for initial design MOSFET and Bipolar circuits Basic Current Bias Sources
SAMPLE FINAL EXAMINATION FALL TERM
ENGINEERING SCIENCES 154 ELECTRONIC DEVICES AND CIRCUITS SAMPLE FINAL EXAMINATION FALL TERM 2001-2002 NAME Some Possible Solutions a. Please answer all of the questions in the spaces provided. If you need
Lecture 13 Date:
Lecture 13 Date: 9.09.016 Common Mode Rejection Ratio NonIdealities in Differential mplifier Common Mode Rejection Ratio (CMRR) Differential input amplifiers are devices/circuits that can input and amplify
BJT Circuits (MCQs of Moderate Complexity)
BJT Circuits (MCQs of Moderate Complexity) 1. The current ib through base of a silicon npn transistor is 1+0.1 cos (1000πt) ma. At 300K, the rπ in the small signal model of the transistor is i b B C r
Preliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B
Preliminary Exam, Fall 2013 Department of Electrical and Computer Engineering University of California, Irvine EECS 170B Problem 1. Consider the following circuit, where a saw-tooth voltage is applied
Microelectronics Part 2: Basic analog CMOS circuits
GBM830 Dispositifs Médicaux Intelligents Microelectronics Part : Basic analog CMOS circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim!! http://www.cours.polymtl.ca/gbm830/! mohamad.sawan@polymtl.ca!
ECE315 / ECE515 Lecture 8 Date:
ECE35 / ECE55 Lecture 8 Date: 05.09.06 CS Amplifier with Constant Current Source Current Steering Circuits CS Stage Followed by CG Stage Cascode as Current Source Cascode as Amplifier ECE35 / ECE55 CS
Design and Simulation of Low Voltage Operational Amplifier
Design and Simulation of Low Voltage Operational Amplifier Zach Nelson Department of Electrical Engineering, University of Nevada, Las Vegas 4505 S Maryland Pkwy, Las Vegas, NV 89154 United States of America
Unit 3: Integrated-circuit amplifiers (contd.)
Unit 3: Integrated-circuit amplifiers (contd.) COMMON-SOURCE AND COMMON-EMITTER AMPLIFIERS The Common-Source Circuit The most basic IC MOS amplifier is shown in fig.(1). The source of MOS transistor is
Chapter 11. Differential Amplifier Circuits
Chapter 11 Differential Amplifier Circuits 11.0 ntroduction Differential amplifier or diff-amp is a multi-transistor amplifier. t is the fundamental building block of analog circuit. t is virtually formed
GATE SOLVED PAPER - IN
YEAR 202 ONE MARK Q. The i-v characteristics of the diode in the circuit given below are : v -. A v 0.7 V i 500 07 $ = * 0 A, v < 0.7 V The current in the circuit is (A) 0 ma (C) 6.67 ma (B) 9.3 ma (D)
Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier
Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in double-ended
Building Blocks of Integrated-Circuit Amplifiers
CHAPTER 7 Building Blocks of Integrated-Circuit Amplifiers Introduction 7. 493 IC Design Philosophy 7. The Basic Gain Cell 494 495 7.3 The Cascode Amplifier 506 7.4 IC Biasing Current Sources, Current
UNIT II MIDBAND ANALYSIS OF SMALL SIGNAL AMPLIFIERS
UNIT II MIDBAND ANALYSIS OF SMALL SIGNAL AMPLIFIERS CE, CB and CC amplifiers. Method of drawing small-signal equivalent circuit. Midband analysis of various types of single stage amplifiers to obtain gain,
Metal-Oxide-Silicon (MOS) devices PMOS. n-type
Metal-Oxide-Silicon (MOS devices Principle of MOS Field Effect Transistor transistor operation Metal (poly gate on oxide between source and drain Source and drain implants of opposite type to substrate.
55:041 Electronic Circuits
55:041 Electronic Circuits Mosfet Review Sections of Chapter 3 &4 A. Kruger Mosfet Review, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width 1 10-6 m or less Thickness 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor
55:041 Electronic Circuits
55:041 Electronic Circuits MOSFETs Sections of Chapter 3 &4 A. Kruger MOSFETs, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width = 1 10-6 m or less Thickness = 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor
Course Outline. 4. Chapter 5: MOS Field Effect Transistors (MOSFET) 5. Chapter 6: Bipolar Junction Transistors (BJT)
Course Outline 1. Chapter 1: Signals and Amplifiers 1 2. Chapter 3: Semiconductors 3. Chapter 4: Diodes 4. Chapter 5: MOS Field Effect Transistors (MOSFET) 5. Chapter 6: Bipolar Junction Transistors (BJT)
V o. ECE2280 Homework #1 Fall Use: ignore r o, V BE =0.7, β=100 V I = sin(20t) For DC analysis, assume that the capacitors are open
ECE2280 Homework #1 Fall 2011 1. Use: ignore r o, V BE =0.7, β=100 V I = 200.001sin(20t) For DC analysis, assume that the capacitors are open (a) Solve for the DC currents: a. I B b. I E c. I C (b) Solve
EE LINEAR INTEGRATED CIRCUITS & APPLICATIONS
UNITII CHARACTERISTICS OF OPAMP 1. What is an opamp? List its functions. The opamp is a multi terminal device, which internally is quite complex. It is a direct coupled high gain amplifier consisting of
ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers
ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic
ECE315 / ECE515 Lecture 7 Date:
Lecture 7 ate: 01.09.2016 CG Amplifier Examples Biasing in MOS Amplifier Circuits Common Gate (CG) Amplifier CG Amplifier- nput is applied at the Source and the output is sensed at the rain. The Gate terminal
EE 435. Lecture 6: Current Mirrors Signal Swing
EE 435 ecture 6: Current Mirrors Signal Swing 1 Review from last lecture: Where we are at: Basic Op Amp Design Fundamental Amplifier Design Issues Single-Stage ow Gain Op Amps Single-Stage High Gain Op
Improving Amplifier Voltage Gain
15.1 Multistage ac-coupled Amplifiers 1077 TABLE 15.3 Three-Stage Amplifier Summary HAND ANALYSIS SPICE RESULTS Voltage gain 998 1010 Input signal range 92.7 V Input resistance 1 M 1M Output resistance
Chapter 13: Introduction to Switched- Capacitor Circuits
Chapter 13: Introduction to Switched- Capacitor Circuits 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4 Switched-Capacitor Integrator 13.5 Switched-Capacitor
2.5 V, k' n. W/L = 3 maa^2, V tn. and V as. = 0, find v s. = +1 V. (d) Repeat (b) for v c u. = -1 V. (e) What is the highest value of v CM
774 CHAPTER 7 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS PROBLEMS 775 S With the two input terminals connected to a suitable dc voltage V cu, the bias current 7 of a perfectly symmetrical differential pair
UNIT I BIASING OF DISCRETE BJT AND MOSFET PART A
UNIT I BIASING OF DISCRETE BJT AND MOSFET PART A 1. Why do we choose Q point at the center of the load line? 2. Name the two techniques used in the stability of the q point.explain. 3. Give the expression
Lecture #2 Operational Amplifiers
Spring 2015 Benha University Faculty of Engineering at Shoubra ECE-322 Electronic Circuits (B) Lecture #2 Operational Amplifiers Instructor: Dr. Ahmad El-Banna Agenda Introduction Op-Amps Input Modes and
Week 9a OUTLINE. MOSFET I D vs. V GS characteristic Circuit models for the MOSFET. Reading. resistive switch model small-signal model
Week 9a OUTLINE MOSFET I vs. V GS characteristic Circuit models for the MOSFET resistive switch model small-signal model Reading Rabaey et al.: Chapter 3.3.2 Hambley: Chapter 12 (through 12.5); Section
The Common Source JFET Amplifier
The Common Source JFET Amplifier Small signal amplifiers can also be made using Field Effect Transistors or FET's for short. These devices have the advantage over bipolar transistors of having an extremely
COMPARISON OF THE MOSFET AND THE BJT:
COMPARISON OF THE MOSFET AND THE BJT: In this section we present a comparison of the characteristics of the two major electronic devices: the MOSFET and the BJT. To facilitate this comparison, typical
Lecture 240 Cascode Op Amps (3/28/10) Page 240-1
Lecture 240 Cascode Op Amps (3/28/10) Page 2401 LECTURE 240 CASCODE OP AMPS LECTURE ORGANIZATION Outline Lecture Organization Single Stage Cascode Op Amps Two Stage Cascode Op Amps Summary CMOS Analog
Index. Small-Signal Models, 14 saturation current, 3, 5 Transistor Cutoff Frequency, 18 transconductance, 16, 22 transit time, 10
Index A absolute value, 308 additional pole, 271 analog multiplier, 190 B BiCMOS,107 Bode plot, 266 base-emitter voltage, 16, 50 base-emitter voltages, 296 bias current, 111, 124, 133, 137, 166, 185 bipolar
Lecture 16: Small Signal Amplifiers
Lecture 16: Small Signal Amplifiers Prof. Niknejad Lecture Outline Review: Small Signal Analysis Two Port Circuits Voltage Amplifiers Current Amplifiers Transconductance Amps Transresistance Amps Example:
EE105 Fall 2015 Microelectronic Devices and Circuits Multi-Stage Amplifiers. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)
EE105 Fall 2015 Microelectronic Devices and Circuits Multi-Stage Amplifiers Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) Differential & Common Mode Signals Why Differential? Differential
ELC224 Final Review (12/10/2009) Name:
ELC224 Final Review (12/10/2009) Name: Select the correct answer to the problems 1 through 20. 1. A common-emitter amplifier that uses direct coupling is an example of a dc amplifier. 2. The frequency
Week 12: Output Stages, Frequency Response
ELE 2110A Electronic Circuits Week 12: Output Stages, Frequency esponse (2 hours only) Lecture 12-1 Output Stages Topics to cover Amplifier Frequency esponse eading Assignment: Chap 15.3, 16.1 of Jaeger
ECEN 5008: Analog IC Design. Final Exam
ECEN 5008 Initials: 1/10 ECEN 5008: Analog IC Design Final Exam Spring 2004 Instructions: 1. Exam Policy: Time-limited, 150-minute exam. When the time is called, all work must stop. Put your initials on
ECE315 / ECE515 Lecture 5 Date:
Lecture 5 ate: 20.08.2015 MOSFET Small Signal Models, and Analysis Common Source Amplifier Introduction MOSFET Small Signal Model To determine the small-signal performance of a given MOSFET amplifier circuit,
EE311: Electrical Engineering Junior Lab, Fall 2006 Experiment 4: Basic MOSFET Characteristics and Analog Circuits
EE311: Electrical Engineering Junior Lab, Fall 2006 Experiment 4: Basic MOSFET Characteristics and Analog Circuits Objective This experiment is designed for students to get familiar with the basic properties
Common mode rejection ratio
Common mode rejection ratio Definition: Common mode rejection ratio represents the ratio of the differential voltage gaina d tothecommonmodevoltagegain,a cm : Common mode rejection ratio Definition: Common
Integrated Circuit: Classification:
Integrated Circuit: It is a miniature, low cost electronic circuit consisting of active and passive components that are irreparably joined together on a single crystal chip of silicon. Classification:
Lecture 34: Designing amplifiers, biasing, frequency response. Context
Lecture 34: Designing amplifiers, biasing, frequency response Prof J. S. Smith Context We will figure out more of the design parameters for the amplifier we looked at in the last lecture, and then we will
Lecture 13. Biasing and Loading Single Stage FET Amplifiers. The Building Blocks of Analog Circuits - III
Lecture 3 Biasing and Loading Single Stage FET Amplifiers The Building Blocks of Analog Circuits III In this lecture you will learn: Current biasing of circuits Current sources and sinks for CS, CG, and
Differential Amplifier Design
Differential Amplifier Design Design with ideal current source bias. Differential and common mode gain results Add finite output resistance to current source. Replace ideal current source with current
Experiments #6. Differential Amplifier
Experiments #6 Differential Amplifier 1) Objectives: To understand the DC and AC operation of a differential amplifier. To measure DC voltages and currents in differential amplifier. To obtain measured
Lecture 20 Transistor Amplifiers (II) Other Amplifier Stages. November 17, 2005
6.012 Microelectronic Devices and Circuits Fall 2005 Lecture 20 1 Lecture 20 Transistor Amplifiers (II) Other Amplifier Stages November 17, 2005 Contents: 1. Common source amplifier (cont.) 2. Common drain
INTRODUCTION TO ELECTRONICS EHB 222E
INTRODUCTION TO ELECTRONICS EHB 222E MOS Field Effect Transistors (MOSFETS II) MOSFETS 1/ INTRODUCTION TO ELECTRONICS 1 MOSFETS Amplifiers Cut off when v GS < V t v DS decreases starting point A, once
d. Why do circuit designers like to use feedback when they make amplifiers? Give at least two reasons.
EECS105 Final 5/12/10 Name SID 1 /20 2 /30 3 /20 4 /20 5 /30 6 /40 7 /20 8 /20 Total 1. Give a short answer to each question a. Your friend from Stanford says that he has designed a three-stage high gain
EE 501 Lab 4 Design of two stage op amp with miller compensation
EE 501 Lab 4 Design of two stage op amp with miller compensation Objectives: 1. Design a two stage op amp 2. Investigate how to miller compensate a two-stage operational amplifier. Tasks: 1. Build a two-stage
Objectives The purpose of this lab is build and analyze Differential amplifier based on NPN transistors.
1 Lab 03: Differential Amplifier Total 30 points: 20 points for lab, 5 points for well-organized report, 5 points for immaculate circuit on breadboard NOTES: 1) Please use the basic current mirror from
Analysis and Design of Analog Integrated Circuits Lecture 18. Key Opamp Specifications
Analysis and Design of Analog Integrated Circuits Lecture 8 Key Opamp Specifications Michael H. Perrott April 8, 0 Copyright 0 by Michael H. Perrott All rights reserved. Recall: Key Specifications of Opamps
Low Voltage Power Supply Current Source
ECE 607(Edgar Sanchez-Sinencio) Low Voltage Power Supply Current Source A M S C Simple implementation of a current source in many applications including a tail current yields a low output impedance. Cascode
d. Can you find intrinsic gain more easily by examining the equation for current? Explain.
EECS140 Final Spring 2017 Name SID 1. [8] In a vacuum tube, the plate (or anode) current is a function of the plate voltage (output) and the grid voltage (input). I P = k(v P + µv G ) 3/2 where µ is a
Electronic Circuits II - Revision
Electronic Circuits II - Revision -1 / 16 - T & F # 1 A bypass capacitor in a CE amplifier decreases the voltage gain. 2 If RC in a CE amplifier is increased, the voltage gain is reduced. 3 4 5 The load
Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem
Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem A report Submitted to Canopus Systems Inc. Zuhail Sainudeen and Navid Yazdi Arizona State University July 2001 1. Overview
ECE 2C Final Exam. June 8, 2010
ECE 2C Final Exam June 8, 2010 Do not open exam until instructed to. Closed book: Crib sheet and 2 pages personal notes permitted There are 4 problems on this exam, and you have 3 hours. Use any and all
Nonlinear Macromodeling of Amplifiers and Applications to Filter Design.
ECEN 622(ESS) Nonlinear Macromodeling of Amplifiers and Applications to Filter Design. By Edgar Sanchez-Sinencio Thanks to Heng Zhang for part of the material OP AMP MACROMODELS Systems containing a significant
Basic OpAmp Design and Compensation. Chapter 6
Basic OpAmp Design and Compensation Chapter 6 6.1 OpAmp applications Typical applications of OpAmps in analog integrated circuits: (a) Amplification and filtering (b) Biasing and regulation (c) Switched-capacitor
Voltage Biasing Considerations (From the CS atom toward the differential pair atom) Claudio Talarico, Gonzaga University
Voltage Biasing Considerations (From the CS atom toward the differential pair atom) Claudio Talarico, Gonzaga University Voltage Biasing Considerations In addition to bias currents, building a complete
Chapter 7 Building Blocks of Integrated Circuit Amplifiers: Part D: Advanced Current Mirrors
1 Chapter 7 Building Blocks of Integrated Circuit Amplifiers: Part D: Advanced Current Mirrors Current Mirror Example 2 Two Stage Op Amp (MOSFET) Current Mirror Example Three Stage 741 Opamp (BJT) 3 4
ECE 442 Solid State Devices & Circuits. 11. Operational Amplifiers
ECE 442 Solid State Devices & Circuits. Operational mplifiers Jose E. Schutt-ine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 442 Jose Schutt ine Operational mplifiers
EE 230 Fall 2006 Experiment 11. Small Signal Linear Operation of Nonlinear Devices
EE 230 Fall 2006 Experiment 11 Small Signal Linear Operation of Nonlinear Devices Purpose: The purpose of this laboratory experiment is to investigate the use of small signal concepts for designing and
EE 330 Laboratory 8 Discrete Semiconductor Amplifiers
EE 330 Laboratory 8 Discrete Semiconductor Amplifiers Fall 2017 Contents Objective:... 2 Discussion:... 2 Components Needed:... 2 Part 1 Voltage Controlled Amplifier... 2 Part 2 Common Source Amplifier...
Chapter 4: Differential Amplifiers
Chapter 4: Differential Amplifiers 4.1 Single-Ended and Differential Operation 4.2 Basic Differential Pair 4.3 Common-Mode Response 4.4 Differential Pair with MOS Loads 4.5 Gilbert Cell Single-Ended and