1 IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage opamps in many commercial ICs Modern opamps gaining in popularity Advanced current mirrors Folded-cascode opamps Current-mirror opamps Fully-differential opamps: better noise rejection Current-feedback opamps: large gain-bandwidth product
2 IsLab Analog Integrated Circuit Design OPA2-2 Wide-Swing Cascode Current Mirrors Output-impedance degradation by short-channel effects R o enhancement by cascoding: limits signal swing Q 4 lowers V DS of Q 3 to match to V DS of Q 2 : I o = I i Q 2 and Q 3 biased at the edge of the active region. Effective gate-source voltages for = I i = I o = I D3 2I D3 V eff = V eff2 = V eff3 = µ n C ox (W/L) V eff5 = (n 1)V eff, V eff1 = V eff4 = nv eff V G1 = V G4 = V G5 V eff5 V tn = (n 1)V eff V tn IsLab Analog Integrated Circuit Design OPA2-3 A wide-swing cascode current mirror with two-transistor diode-connected circuit (whose input resistance 1/g m ) I i I o = I i W (n 1) 2 L Q 4 W n 2 L W L Q 1 V o 0.4 V Q 3 Q 2
3 IsLab Analog Integrated Circuit Design OPA2-4 Minimum allowable output voltage for n = 1 V DS2 = V DS3 = V G5 V GS1 = V G5 (V eff1 V tn ) = V eff V o V eff1 V DS2 = (n 1)V eff = 2V eff V To ensure that all transistors are in the active region V DS4 = V G3 V DS3 = (V eff V tn ) V eff = V tn > V eff4 = nv eff V tn > nv eff V Take (W/L) 5 smaller to bias Q 2 and Q 3 with slightly larger V DS than the minimum no sharp boundary between linear and active regions, body effect of Q 1 and Q 4 (V SB > 0, V t1, V GS1, V DS2 ) V DS2 V eff ( ) V L 2 = 2.5λ and L 1 = 4λ (twice L min ) to reduce short-channel effects (V DS2 < V DS1 ) and maximize the pole frequency (ω p2 1/L, 1/L 2 ) IsLab Analog Integrated Circuit Design OPA2-5 Wide-Swing Constant-g m Bias Circuit Minimizes most of second-order imperfections caused by the finite-output impedance without greatly restricting signal swings. n-channel wide-swing cascode current mirror: Q 1 p-channel wide-swing cascode current mirror: Q 6 Q 10 Cascode bias circuit: Q 11 Q 14 Start-up circuit: Q 15 Q 18 This bias circuit for stabilized g m s allows the performance of realized opamps to be accurately predicted using moderately simple equations. This constant-g m bias circuit had been realized and verified for a 0.8-µm CMOS technology, and is very important in analog design.
4 IsLab Analog Integrated Circuit Design OPA2-6 A wide-swing constant-g m bias circuit: small W/L for Q 18 Q 7 Q 11 Q 8 V bp Q 6 Q 12 Q 10 Q 18 Q 9 V cp Q 16 Q 15 Q 1 Q 4 Q 13 Q 17 V cn Q 2 R B 5 kω Q 3 Q 14 V bn IsLab Analog Integrated Circuit Design OPA2-7 Enhanced Output-Impedance Mirrors Cascode current mirror with regulated cascode transistor to increase output resistance R o gain boosting Basic idea is to use a negative feedback amplifier to keep V DS of Q 2 as stable as possible I o is less sensitive to the output signal. R o = [g m1 r ds1 (1 A) 1]r ds2 r ds1 g m1 r ds1 r ds2 (1 A) Practical limitation of R o by a parasitic conductance between the drain of Q 1 and its substrate due to short-channel effects substrate current by impact ionization Reduced enhancement for bipolar transistors due to the base current Need for local compensation capacitors to prevent ringing and substantial increase of settling time for large signal transients
5 IsLab Analog Integrated Circuit Design OPA2-8 An enhanced output-impedance current mirror R o I i V B A Q 1 Av ds2 v gs1 g m1 v gs1 r ds1 Q 3 Q 2 r ds2 Circuit equations for regulated cascode current mirror: R o = v t /i t v gs1 = Av ds2 v ds2 = (1 A)v ds2 = (1 A)r ds2 i t i t = g m1 v gs1 (v t r ds2 i t )/r ds1 v t = (r ds1 r ds2 )i t g m1 r ds1 v gs1 = [r ds1 r ds2 (1A)g m1 r ds1 r ds2 ]i t IsLab Analog Integrated Circuit Design OPA2-9 Säckinger Realization of Enhanced R o Mirrors The feedback amplifier is realized by CS amplifiers: A g m3 r ds3 /2 gm3 r ds3 R o = (g m1 r ds1 )r ds2 = g m1g m3 r ds1 r ds2 r ds3 2 2 The signal swing is significantly reduced due to the feedback amplifier. V DS5 V DS2 = V GS3 = V eff3 V tn V eff2 I i 2 1 I o Q 4 Q 1 Q 6 Q 3 Q 2
6 IsLab Analog Integrated Circuit Design OPA2-10 Wide-Swing Current Mirror with Enhanced R o Diode-connected transistors Q 4 and Q 8 are used as dc level shifters. All transistors are biased with the same current density and the same V eff except for Q 3 and Q 7 : V eff = 2I D /µ n C ox (W/L) I i = 7, V eff3 = V eff7 = 2V eff V DS2 = V G3 V GS4 = (2V eff V tn ) (V eff V tn ) = V eff Power dissipation of this mirror with the shown W/L values would be almost doubled over that of a classical cascode mirror. Power dissipation can be reduced at the expense of speed by biasing the enhancement circuitry (Q 3, Q 4, Q 7, Q 8 ) at lower current density. IsLab Analog Integrated Circuit Design OPA2-11 A wide-swing current mirror with enhanced output impedance I i I o Q 1 70 Q 7 Q 8 Q 4 Q Q 6 Q
7 IsLab Analog Integrated Circuit Design OPA2-12 A modified version of wide-swing enhanced output-impedance mirror: slightly mismatching, but less area, instability, and power dissipation Bias circuit I i 4 I o = I i V cn Q 1 70 Q 4 Q Q 7 Q 6 Q IsLab Analog Integrated Circuit Design OPA2-13 Folded-Cascode Opamp Modern CMOS opamps are designed to drive only capacitive loads. No voltage buffer higher speed and larger signal swing. Only a single high-impedance node at the output of an opamp. The admittance at all other node is on the order of g m. The speed of the opamp is maximized by having all internal node of low impedance reduced voltage signals and large current signals current-mode opamps (ω H 1/ τ i = 1/ R io C i ). The compensation is usually achieved by the load capacitance: larger, more stable but slower. These opamps = operational transconductance amplifiers (OTAs)
8 IsLab Analog Integrated Circuit Design OPA2-14 Q 1, Q 2 = differential transistors, Q 6 = cascode transistors dc level shifters A single stage with a high gain of 3000 due to the high output resistance by cascoding Q 7 Q 10 = Wilson, cascode, or wide-swing current mirror Q 12, Q 13 = clamp transistors: to increase the slew rate and recover quickly from slewing as clamping the drain voltages of Q 1 and Q 2 Dominant pole compensation by or an additional capacitor Lead compensation by a resistor placed in series with Bias current of cascode transistors is derived by a current subtraction 1, 2 from the same bias circuit using replication principle IsLab Analog Integrated Circuit Design OPA2-15 A folded-cascode operational amplifier with clamp transistors Q 12 Q 11 Q 3 Q 4 Q 13 1 Q 14 Q 6 V o V i Q 1 Q 2 V i Q 15 2 Q 7 V B Q 8 Q 16 Q 17 Q 9 Q 10
9 IsLab Analog Integrated Circuit Design OPA2-16 Small Signal Analysis Two signal paths have slightly different transfer functions due to poles and zeros caused by the current mirror. For an nmos mirror, a pole-zero doublet occurs at frequencies greater than ω ta and can be ignored. Ignoring HF poles and zeros (ω p2 ω ta ) and assuming that g m5 and g m6 are much larger than g ds3 and g ds4, the transfer function is given by A V = V o g m1 Z L (s) = g m1r o R o = g mrd 2 g «mrd 2 V i 1 sr o 3 2 The unity-gain frequency of the opamp ω ta g p m1 2ID1 µ n C ox (W/L) 1 = Maximizing g m1 maximizes the unity-gain bandwidth ω ta for the given load capacitance (dominant pole). IsLab Analog Integrated Circuit Design OPA2-17 g m1 is maximized by using wide nmost and larger bias current than that of cascode and mirror MOSTs of the output node maximizes R o and dc gain, better thermal noise performance (v 2 n = 4kT 2 3g m ) A practical upper limit on the ratio of I D1 to I D5 might be around 4 due to biasing by current subtraction. Lead compensation by a resistor R C : chosen to place a zero at 1.2ω ta A V = g m1 1/R o 1/(R C 1/s ) g m1(1 sr C ) s The second poles are primarily due to the time constants introduced by the resistances and parasitic capacitances at the sources of the p-channel cascode transistors: C s6, R s6 = 1 g m6 (1 R L /r ds6 )
10 IsLab Analog Integrated Circuit Design OPA2-18 Slew Rate A large differential input voltage Q 1 to be turned on hard, Q 2 to be turned off I D4 will be directed through Q 6 into. SR = I D4 Since designing 2 > I D3, both Q 1 and the current source 2 will go into the triode region: I D3 = I D1 = I D17. The source and drain voltage of Q 1 approaches V SS to decrease 2. When coming out of slewing, the source and drain voltage of Q 1 must slew back to a voltage close to V DD. This additional slewing time greatly increases the transient times and the distortion for switched-capacitor applications. IsLab Analog Integrated Circuit Design OPA2-19 Clamp transistors Q 12, Q 13 are turned off during normal operation. Their main purpose is to clamp the drain voltages of Q 1 or Q 2 so they don t change as much during slewing. A second effect dynamically increases the bias currents of Q 3 and Q 4 during slewing. Q 12 conducts with the current coming from Q 11. The current increase in Q 11 causes the currents in Q 3 and Q 4 to also increase until the sum of the currents Q 3 and Q 12 is equal to 2. The increase in bias current of Q 4 results in an increase of the maximum current available for charging.
11 IsLab Analog Integrated Circuit Design OPA2-20 Current-Mirror Opamp Another popular opamp for driving on-chip capacitive loads All nodes are low impedance except for the output node. A reasonable overall gain can be achieved by using good current mirrors with high output impedance. Approximate transfer function for current gain K Unity-gain frequency A V = V o V i = Kg m1 Z L (s) = Kg m1r o 1 sr o ω ta Kg m1 = K 2ID1 µ n C ox (W/L) 1 IsLab Analog Integrated Circuit Design OPA2-21 A current-mirror opamp with wide-swing cascode current mirrors: I D12 = KI D11 = KI D1 = K /2 Q 6 V B2 Q 7 V B2 Q 8 Q 3 Q 4 Q 9 Q 10 V B1 V o V i Q 1 Q 2 V i Q 11 Q 12 Q 13 Q 14
12 IsLab Analog Integrated Circuit Design OPA2-22 Total current is known for a given power-supply voltages and P D. I t = (3 K)I D1 = P D /(V DD V SS ) For larger values of K, the opamp transconductance G m Kg m1 is larger, ω ta is also larger if not limited by high-frequency poles, and the dc gain A 0 is larger for fixed I t. ω ta = Kg m1 G m = K 3 K 2It µ n C ox (W/L) 1 R o g m10r 2 ds10 2 = = 2KID1 µ p C ox K(W/L) 1 2 2µp C ox (W/L) 1 2 V 2 A K(I D1 ) 3/2 V 2 A (KI D1 ) 2 A 0 = Kg m1 R o = (3 K) µ n µ p C ox (W/L) 1 V 2 A I t IsLab Analog Integrated Circuit Design OPA2-23 A practical upper limit on K might be around five. The important nodes to determine the nondominant poles are the drain of Q 1 primarily, and the drains of Q 2 and Q 9 secondly. For given I t, increasing K (I D1, W 8 ) increases the time constant of these nodes. The second pole moves to lower frequencies. For high speed operation, K might be taken as small as one. K = 2 might be a reasonable compromize for general purpose. Slew rate of the current-mirror opamp SR = K For K = 4, 4/5 of the total bias current will be available for charging or discharging during slewing 4 /( ).
13 IsLab Analog Integrated Circuit Design OPA2-24 This result gives a current-mirror opamp superior slew rates even when compared to a folded-cascode opamp with clamp transistors. No large voltage transients due to low impedance nodes. For the larger bandwidth and slew rate, the current-mirror opamp is usually preferred over a folded-cascode opamp. However, CMO will suffer from larger thermal noise (smaller g m ) because input transistors are biased at a lower proportion of I t. Example 6.3: analysis for transistor sizes given in Table 6.2 (1) K = 2, I D1 = I t /(3 K) = (P D /5)/5 = 80 µa (2) g m1 = 2I D1 µ n C ox (W/L) 1 = 1.7 ma/v (3) f ta = Kg m1 /2π = 54 MHz (4) SR = K / = K2I D1 / = 32 V/µs IsLab Analog Integrated Circuit Design OPA2-25 Linear Settling Time Time constant for linear settling time: affected by both the feedback factor β and the effective load capacitance, 0.1% t s = 7τ τ = 1 ω 3dB = 1 βω ta, ω ta = g m1 C C, g m1, Kg m1 Feedback factor by return ratio analysis: C C = compensation capacitance, C p = input capacitance of opamp (parasitic switch) β = 1/s(C 1 C p ) 1/s(C 1 C p ) 1/sC 2 = C 2 C 1 C 2 C p Effective load capacitance: C i = input capacitance of the next stage = C i C C C 2(C 1 C p ) C 1 C 2 C p
14 IsLab Analog Integrated Circuit Design OPA2-26 Fully Differential Opamps Balanced circuits: symmetric and differential inputs and outputs Rejection of common-mode noise from the substrate and switches But can not reject a differential noise by voltage-dependent nonlinearities that cause more noise to feed into one signal path than the other. One drawback is that a common-mode feedback circuit must be added. The design of a good CMFB circuit is not trivial: the speed performance comparable to the differential path, the limitation of continuous-time CMFB circuits on maximum allowable signal, the glitch injection and increase of load capacitance for switched-capacitor CMFB circuits. Slew-rate reduction due to fixed-bias currents in output current mirror Regardless of limitations, differential designs are becoming more popular. IsLab Analog Integrated Circuit Design OPA2-27 Fully Differential Folded-Cascode Opamp Cascode current sources: Q 7 and Q 8, Q 9 and Q 10 The CMFB circuit will detect the average of two output signals. The negative slew rate is limited by the bias currents of Q 9 or Q 10. Clamp transistors Q 11, Q 12 to minimize transient voltage changes. Drain nodes of the input devices will be responsible for the second pole each signal path consists of only this and output nodes. The complementary topology with nmos as cascode transistor is often a reasonable choice for high-speed designs. But the dc gain would become smaller due to the input transistors of pmos.
15 IsLab Analog Integrated Circuit Design OPA2-28 A fully differential folded-cascode opamp Q 11 V B1 Q 12 Q 3 Q 4 V B2 Q 6 V i Q 1 Q 2 V i V o Q 7 V B3 Q 8 CMFB circuit V B4 Q 13 Q 9 Q 10 IsLab Analog Integrated Circuit Design OPA2-29 Fully Differential Current-Mirror Opamp Topology selection: whether the dc gain or bandwidth is more important, whether or second pole is limiting the bandwidth. nmos input transistors: larger dc gain, lower thermal noise. pmos input transistors: larger bandwidth, lower 1/f noise. For a general-purpose fully differential opamp: large pmos input transistors, a current gain of K = 2, and wide-swing enhanced output-impedance cascode mirrors and current sources. The negative slew rate is limited by the bias currents of Q 13 or Q 14. It is possible to modify the designs to improve slew rate at the expense of small-signal performances using additional circuitry.
16 IsLab Analog Integrated Circuit Design OPA2-30 A fully differential current-mirror opamp Q 6 V B2 Q 7 V B2 Q 8 Q 3 Q 4 Q 9 Q 10 V o V i Q 1 Q 2 V i Q 11 V B1 Q 12 CMFB circuit Q 13 Q 14 IsLab Analog Integrated Circuit Design OPA2-31 Alternative Fully Differential Opamps A fully differential current-mirror opamp with bidirectional output drive: four current mirrors having two outputs for sourcing and sinking. For a large differential input, the current going into V o will be K, and the current being sinked from V o will also be K due to other mirror. A class AB fully differential current-mirror opamp: low power, two differential pairs connected in parallel, a differential pair Q 3, Q 4, a level shifter (Q 1 : source follower, Q 2 : diode), small (class AB). For a large differential input voltage, the pair Q 3, Q 4 turns off, while the current through the pair Q 7, Q 8 increases dynamically due to a lowered gate voltage of Q 7 a very large slew-rate performance, but a major problem for low supply voltage due to V CM 2V GS V eff = 2V t 3V eff Level shifters noise increase, lowering second poles by parasitics
17 IsLab Analog Integrated Circuit Design OPA2-32 A fully differential current-mirror opamp with bidirectional output drive: the CMFB circuit is not shown. K : 1 1 : K 1 : 1 1 : 1 V i Q 1 Q 2 V i V o V o K : 1 1 : K IsLab Analog Integrated Circuit Design OPA2-33 A class AB fully differential opamp: the CMFB circuit is not shown. K : 1 1 : K Q 1 V i Q 8 Q 4 V i V o Q 2 Q 3 Q 7 Q 6 V o K : 1 1 : K
18 IsLab Analog Integrated Circuit Design OPA2-34 A fully differential opamp composed of two single ouput opamps v i Av i v o v i Av i v o Single output Differential output v i Av i v o v i v o Balanced differential output Implementation IsLab Analog Integrated Circuit Design OPA2-35 A fully differential opamp having rail-to-rail ICMR: G m < 15% I 2 M 2 I 3 I 3 V bp Q 6 Q 9 Q 10 V B1 Q 1 Q 2 Q 3 Q 4 V i V o V o V i V B2 Q 7 Q 8 M 1 V bn I 1 I 4 I 4
19 IsLab Analog Integrated Circuit Design OPA2-36 Common-Mode Feedback Circuits The CMFB circuitry is often the most difficult part of the opamp to design two approaches (continuous time, switched capacitor) Continuous-time approach: limitation on signal swing, dependence of CM voltage V CM on signal due to finite CMRR, circuit nonlinearity, and device mismatch unstability of common-mode loop For input differential signal V d, I D1 = I D3 and I D2 = I D4 assuming V CM (V o V o )/2 = 0, CMRR = (I D depends only on V d ) I D5 = I D2 I D3 = ( /2 I) ( /2 I) = Thus I D5 will not change even when large differential signal voltages are present. If V C is used to control the bias voltages of the output stage, the bias currents in the output stage will be independent of whether the input differential signal is present or not. IsLab Analog Integrated Circuit Design OPA2-37 A continuous-time CMFB circuit: V CM = 0, V C = control voltage V o Q 1 Q 2 Q 3 Q 4 V o V C Q 6
20 IsLab Analog Integrated Circuit Design OPA2-38 If a positive CM voltage is present, this voltage will cause both I D2 and I D3 to increase, which causes V C to increase. This voltage will increase the current of nmos current sources at the output stage, which will cause the CM voltage to decrease and return to zero. A modified CMFB circuit having twice the common-mode gain and 0.01% linearity. If a positive common-mode voltage is present, the drain current of will be 4 I instead of 2 I. A alternative continuous-time CMFB circuit: less signal swing due to dc level shift, more difficult to compensate owing to additional nodes. The phase margin and step response of the common-mode loop should be verified by simulation for unstability by CM signals. Designing continuous-time CMFB circuits that are both linear and operate with low supply voltage is an area of continuing research. IsLab Analog Integrated Circuit Design OPA2-39 A modified CMFB circuit having twice the common-mode gain V o Q 1 Q 2 Q 3 Q 4 V o V C Q 7 Q 6
21 IsLab Analog Integrated Circuit Design OPA2-40 A continuous-time CMFB circuit with accurate output balancing: V CM = V BAL, linear detection of V CM by two identical resistors V GS1 = V GS2 V o Q 1 Q 2 V o 20 kω 20 kω 1.5 pf 1.5 pf V ref Q 3 Q 4 V A V A = V CM V GS1 V C Q 6 V ref = V BAL V GS1 V BAL = 0, V o = V o IsLab Analog Integrated Circuit Design OPA2-41 A Switched-Capacitor CMFB Circuit Use for larger output signal swing and linear detection of V CM Capacitors C C generate the average V CM of the output voltages. This circuit acts like a simple RC low-pass filter having a dc input signal V B : in steady state v C = V CM V B, C S = ( )C C V R φ 1 φ 2 v o v o φ 2 φ 1 V R V B v 1 C S v 2 C C v 3 C C v 4 C S M 1 v C
22 IsLab Analog Integrated Circuit Design OPA2-42 Analysis of Switched-Capacitor CMFB Circuit Analysis by conservation of charge: q(φ 1 ) = q(φ 2 ) Phase φ 1 : v 1 = v 4 = V B V R, v C = v o v 2 = v o v 3 Phase φ 2 : short (v 1 = v 2, v 3 = v 4 ), steady state (v 2 = v 2, v 3 = v 3) C S v 1 C C v 2 C C v 3 C S v 4 = C S v 1 C C v 2 C C v 3 C S v 4 2C S (V B V R ) C C (v 2 v 3 ) = (C C C S )(v 2 v 3 ) v 2 v 3 = 2(V B V R ), v C = v o v 2, v C = v o v 3 v C = v o v o 2 v C = v o v o 2 V B V R V CM V B V R V B V R V CM V B V R IsLab Analog Integrated Circuit Design OPA2-43 Current-Feedback Opamps Popular recently in high gain and high speed applications using complementary bipolar technology CMOS technology Feedback gain can be changed without significantly affecting loop gain a single compensation capacitor can be used irrespective of gain. The input signal v i is applied to a high-impedance input, while a feedback current i f connects to a low-impedance node v n. The voltage v n is equal to the input signal v i due to the class-ab unity-gain buffer of Q 1, Q 2, and two diodes for biasing. Because R o is very large, a small feedback current i f results in a large output voltage v o i f 0 for a finite output voltage.
23 IsLab Analog Integrated Circuit Design OPA2-44 A current-feedback opamp: v i v n, i f 0 I R i f /2 v i I R Q 1 1 : 1 v n i f C C R o 1 v o R 2 i f R 1 I R Q 2 1 : 1 I R i f /2 IsLab Analog Integrated Circuit Design OPA2-45 Voltage gain: i f 0, v i v n = v o R 1 /(R 1 R 2 ) v o v i = R 1 R 2 R 1 = 1 R 2 R 1 Loop gain: breaking the loop and injecting a test signal v t at the top of R 2 (i f = v t /R 2 for v i = 0) loop gain is independent of R 1 Aβ v o = i f v o = 1 1 = R o/r 2 v t v t i f R 2 sc C 1/R o 1 sr o C C vi =0 Unity-gain frequency of the loop gain Aβ: ω t 1/R 2 C C Transfer function: i f = (v o v i )/R 2 v i /R 1, v o = i f (R o C C ) i f = v i (R 1 R 2 ) R 1 R 2 R 1 R o /(1 sr o C C ), v o = i fr o 1 sr o C C A f (s) = v o v i = i f v i v o i f = (R 1 R 2 )R o (R 2 R o )R sc C (R 2 R o )
24 IsLab Analog Integrated Circuit Design OPA2-46 Bandwidth: R o g m r 2 o/4 R 2 A f (s) R 1 R 2 R sr 2 C C, ω 3dB = 1 R 2 C C = ω t The various closed-loop gains can be realized by changing R 1 without affecting the unity-gain frequency or the closed-loop stability. This independence of gain on stability does not occur for voltagefeedback amplifiers: A f (s) 1/β(1 s/βω ta ), ω t = βg m /C C Limitations: R 1 1/(g m1 g m2 ), use of a purely resistive feedback network, but difficult to compensate if reactive components are used in the feedback network, noiser for Darlington-pair input stage. Regardless of these limitations, CFOs exhibit excellent high-frequency characteristics and are quite popular in many video and telecommunications applications. IsLab Analog Integrated Circuit Design OPA2-47 Homework & Project Problems: 6.1, 6.2, 6.7, 6.10, Design a fully-differential CMOS operational amplifier for the following specifications. Performances Specifications Performances Specifications Power supply ±2.5 V Input CMR ±1 V 0.5 pf Output swing ±1 V DC gain 60 db Settling time 15 ns The design objective is minimizing the power dissipation. Explain why you chose your architecture over alternatives. Draw a circuit schematic with all device sizes. Include the design procedure and the calculation of design parameters. Provide simulation results for verification.