SAMPLE FINAL EXAMINATION FALL TERM

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1 ENGINEERING SCIENCES 154 ELECTRONIC DEVICES AND CIRCUITS SAMPLE FINAL EXAMINATION FALL TERM NAME Some Possible Solutions a. Please answer all of the questions in the spaces provided. If you need additional space, use the backs of the sheets. b. Partial credit is achievable, so include all of your calculations and clearly indicate what you are trying to do. c. Note that you have modicum of choice in the first question. d. The relative credit assigned to each question is indicated as a prudent time allocation. That is, there is a possible total credit of (Prudent time allocation 90 minutes) Briefly answer NINE (9) of the following FOURTEEN (14) questions: a. In the space below, plot the net charge density (sign and magnitude) and the built-in electric field as a function of position along a line which intersects a pn homojunction at right angles. The n-side of the junction has a doping level that is 10 times that of the p-side (i.e., N D 10 N A ). Label and/or note important features. See discussion at: <-- p-side center of junction n-side --> E(x) qn(x) Q Q-

2 PAGE-2 b. Suppose that a particular BJT has the following collector current characteristic curve: Using this characteristic, find the common emitter current gain (CECG) and the common base current gain (CBCG) of the transistor when it is operated in the active mode. Also find the Early voltage (V A ) of the transistor. β α ( ) ma µa β β I 0 V A [ I( V m ) I( 0) ] V 15.5 m 20 V 310 V [ ]

3 PAGE-3 c. What does the circuit illustrated below do? Explain how it does it.. V c n-channel MOSFET Input analog voltage Output voltage -V c p-channel MOSFET See discussion at: ml#trans_gate d. A two-part question about operational amplifier offsets i.) What is meant by the input offset voltage of an op amp? How is it measured? ii.) What is meant by the input offset current of an op amp? See Section 2.9 Sedra & Smith and Laboratory Assignment 1.

4 PAGE-4 e. The following circuit has been described as an improved rectifier. Explain. V supply V O V in -V supply V' O R L - See discussion at: l.html#rectifier

PAGE-5 f. For a diode with the characteristic depicted below, calculate the effective or small-signal resistance at a forward bias of 0.5 volts. Slope Method: ff V I 0.7 V 4.

5 PAGE-5 f. For a diode with the characteristic depicted below, calculate the effective or small-signal resistance at a forward bias of 0.5 volts. Slope Method: ff V I 0.7 V 4.5 kω 155 µa Analytic Method: Assume that I V 1 therefore 1 ff I 0 exp V V T 1 d dv I exp V 0 V T I exp V 0 V T I V where V V T V V 1 2 T ln I ( V 1) I V 2 From graph: I( 0.50 V ) 45.5 µa; I 0.66 V V T V 1 V 2 ln I V 1 I V ln I V 45.5 µa ff V T 144 mv kω V 100 µa; I( 0.76 V ) 200 µa

6 PAGE-6 g. In the space below, sketch a complete small signal equivalent circuit of a MOS transistor (assume that the body is not connected to the source). Identify each element of the equivalent circuit and give a ball park estimate of its magnitude. See discussion at: ody_effect h. In the space below, draw a cascode amplifier stage and briefly describe the advantages this configuration offers in circuit design. See discussion at: i. An amplifier has the gain transfer function 10 2 s A s s 2π s /2π 10 5 In the space below sketch a Bode plot for its magnitude and specify the midband gain, the lower 3-dB frequency and the upper 3-dB frequency. ω /2π A ω 20 log A f 2 1 ω /2π log 1 1 ( ω /2π 10 5 ) 2 f 20 log 2 1 f / log 1 f /105

7 PAGE-7 60 db 40 db 20 log A ( f ) Midband Gain 20 db 0 db -20 db f ω/2π -40 db f 20 log log 1 ( f /10 2 ) 2 20 log 1 ( f /10 5 ) 2 See Section 7.1 and Example 7.1 in Sedra and Smith j. The following circuit is used as a temperature measuring device. Find an expression for v out as a function of the temperature to be measured. junction diode R s v s ideal op amp v out

8 PAGE-8 Assume that I V I 0 exp V n k T 1 therefore V S I R 0 exp V OUT S n k T 1 so that T V OUT V S n k ln 1 I 0 R S k. Consider the three Zener diode circuits illustrated below. In the spaces provide, sketch a representation of the time dependent output signal foach of the three cases

9 PAGE-9 l. In the following circuit, find v o in terms of v s1 and v s2 using the ideal op amp model. V V S2 2 kω V V S1 S 2 6 kω V - 4 kω V V S1 S 2 S1 6 kω V 2V S1 S2 3 V 1 9 V OUT therefore V OUT 3 ( V S1 2 V S2 ) m. Using expressions for the i D -v DS characteristics of an enhancement mode, n-channel MOSFET (as derived in the text and lecture), derive expressions for the small-signal transconductance g m in both the triode and saturation regions of operation. See discussion at:

PAGE-10 n. The following important characteristic curves for a particular BJT which tells us a good deal about that device performance. Briefly discuss the physics of this curve.

10 PAGE-10 n. The following important characteristic curves for a particular BJT which tells us a good deal about that device performance. Briefly discuss the physics of this curve. What is the origin of this current? Why does have the shape that it does? What does it tell us about the given transistor s performance? See discussion at:

11 PAGE (Prudent time allocation 15 minutes) For the amplifier circuit shown below, find an expression for the output v O in terms of the two inputs v 1 and v 2. From this expression find expressions for the differential gain G d, the common-mode gain G CM and the common-mode rejection ratio CMMR. R 2 R 3 V O V 1 V 2 R 4 - v - v 1 v 0 v - R 2 v - v v v - R 4 R 3 R 4 v 2 R 4 R 3 R 4 v 2 R 2 R 2 v 1 R 2 R 2 v 1 v 0 R R 1 2 R 4 R v R 3 R 2 2 v 4 2 R R 1 2 R 4 R 3 R 4 v d 2 R 2 v 0 v cm v d 2 R 2 R 2 R 2 R 4 R 2 R 3 R 4 v cm G d 1 R 2 R 4 R 2 2 R 3 R 4 CMRR 20 log G d G cm 20 log 1 2 R 2 v 0 v cm v d 2 R 4 R 2 R 3 ( R 3 R 4 ) G cm R 4 R 2 R 3 R 3 R 4 R 4 ( R 2 ) R 2 R 3 R 4 R 4 R 2 R 3

12 PAGE (Prudent time allocation 30 minutes) Consider an npn BJT with the following I C -V CE characteristic:

13 PAGE-13 Suppose that such a transistor is used in the circuit illustrated below. 7V R B 10kΩ V (t) in - C V (t) out - a. By drawing a load line on the characteristic curve, choose the circuit quiescent point or DC operating point to maximize the AC voltage swing of V out (t). What are the DC values of the bias current, the collector current, R B and V out at the quiescent point (carefully specify units)? DC bias current 3.5 µa DC collector current 0.39 ma DC output voltage 3.2 V Bias resistor ( )/3.5 x MΩ b. For these quiescent point values, sketch in the space on the next page a complete small-signal equivalent circuit of the transistor including values and units for all parameters of the equivalent circuit (neglect any high frequency effects).

14 PAGE-14 From the graph at the Q - point: β 0.33 ma 3 µa 110 g m I c V T r π β g m 0.39 ma 25 mv Ω k Ω Ω r o v ce 8 V i c 0.09 ma 89 k Ω r π 6.9 kω -1 g v π (0.016 Ω ) v m π v IN 10 kω v OUT R 1.8 MΩ B r 89 kω ο c. Again at the quiescent point found above and at frequencies where we can neglect capacitive effects, find the small-signal voltage gain, input impedance and output impedance of the circuit. Small-signal voltage gain (0.016 Ω -1 ) (89 10) kω 144 Small-signal input impedance 1.8 MΩ 6.9 kω 6.9 kω Small-signal output impedance (89 10) kω 9.0 kω

15 PAGE (Prudent time allocation 15 minutes) If in the following circuit we assume that the three transistors are identical, find an expression for the ratio I o /I ref in terms of the β of the transistors. I ref Q 3 I o Q 1 Q 2 See the discussion at:

16 PAGE (Prudent time allocation 10 minutes) Measurements on the three circuits below yield the voltages indicated. Find the value of β foach of the pnp transistors. 5 V 5 V 10 V 1 kω 4.3 V 4.3 V 8.3 V 9 V 2 V 20 kω 2.3 V 150 kω 430 kω 2 kω 230 Ω 1 kω (a) (b) (c) (a) β (b) β (c) β

17 PAGE (Prudent time allocation 20 minutes) Consider a NMOS enhancement transistor with the following characteristics: 15 ma 10 ma Output Characteristics of a 2N6762 NMOS Enhancement Transistor V D S V G S - V t VGS 5.0V VGS 4.5V i D 5 ma VGS 4.0V VGS 3.5V VGS 3.0V VGS < Vt V t 2V - 5 ma 0.0 V 1.0 V 2.0 V V DS 3.0 V 4.0 V Suppose two such transistors are used in a common source, NMOS amplifier configuration where one transistor serves as the load of the other. Assume that the amplifier is powered by a single-sided 6 volt supply. a. Draw a circuit of such an enhancement loaded amplifier in the space below:

18 PAGE-18 b. Draw directly on the characteristic curve above the appropriate load curve for the amplifier. See characteristic curve c. Using this load curve, choose a quiescent point or dc operating point so as to maximize the ac voltage swing of the amplifier output. What are the dc values of the bias voltage, the drain current, and the drain-source voltage at the quiescent point (carefully specify units)? dc bias voltage 3.5 V dc drain current 3 ma dc drain-source voltage 2.5 V d. For these quiescent point values, find the ac voltage gain of the amplifier. voltage gain 1 7. (Prudent time allocation 15 minutes) As the first step in analyzing the following BJT amplifier, replace the transistor with its lowfrequency T equivalent circuit. Then, derive the gain v E /v i, the gain v C /v i, and the input impedance of the amplifier. V CC R C v C v i v E R E -V EE

19 PAGE-19 Nodal Analysis (neglecting r o - i.e r o ): Node B i b g m Node C ( v i v E ) v E v i Nodal Analysis (including r o ): Node B i b g m Node C ( v i v E ) v E v i g m Node E ( v i v E ) v C 0 R C g m Node E ( v i v E ) v C r o R C v E r o v E R E v i v E r o v E v C v i R E r o Results (neglecting r o - i.e r o ): v E v i R E R E R E v C g v m R C i R E 1 i b g R in v i R E m 1

20 PAGE-20 Results (including r o ): v E v i v C v i R E g r o R C r m ( re R e r o E ) r 1 g o R C m ( re R r o E ) r R o C re R r o R C E g m ( r o R C ) 1 g m R E r o r o R C r o 1 r o r e R E R E r o R C r R e E r r o R C e R E r o R C r o R E 1 i r R o C ( re R R b E r o R C E ) R in v i r 1 g o R C m ( re R r o E ) r R o C re R r o R C E g m - 1 s 8. (Prudent time allocation 10 minutes) For a particular npn transistor operating in the active mode the collector current is measured to be 1 ma and 10 ma for base-to-emitter voltages of 0.63 V and 0.70 V, respectively. Find the corresponding values of n and I S for this transistor. Assume that I C ( V BE ) I S exp V BE therefore n 1 V V 1 2 V T ln I ( V 1) I V 2 and I S I V C BE 10 ma exp V BE 700 mv exp n V T 30 mv nv T 1 25 mv ( ) V ln ma A mv 1 25 mv a. If two such devices are connected in parallel and a forward bias o 0.65 V is applied across the two base-emitter junctions, what total collector current do you expect? I C ( 650 mv ) mv ( A ) exp 30 mv 3.8 ma

21 PAGE (Prudent time allocation 12 minutes a. Draw a complete circuit diagram of an emitter-follower amplifier which uses an npn BJT. b. Draw a small-signal version of this complete emitter-follower that utilizes the most appropriate BJT small-signal equivalent circuit. c. Using this small-signal circuit, find an expression for the voltage gain of the amplifier d. Again using this small-signal circuit, find an expression for the input impedance of the amplifier. See discussion at: _amp 10. (Prudent time allocation 10 minutes) a. Assuming that the op amp is ideal, find the transfer function H( s) V 2 ( s) V 1 ( s).

22 PAGE-22 V 1 s 10 3 s V s 2 H s s V ( s) 10 2 V 1 ( s) s 10 3 s 10 3 s 1 s 10 3 b. Describe the behavior of this transfer function in both the high and low frequency limits. V ( s) 2 ω V 1 ( s) V ( s) 2 ω 0 V 1 ( s) H s H s 10 3 s s 11. (Prudent time allocation 15 minutes) a. Draw a complete circuit diagram of an source-follower amplifier which uses an n-channel MOSFET. b. Draw a small-signal version of this complete source-follower that utilizes the most appropriate MOSFET small-signal equivalent circuit. c. Using this small-signal circuit, find an expression for the voltage gain of the amplifier c. Again using this small-signal circuit, find an expression for the input impedance of the amplifier. See and adapt the The Common-Collector Amplifier or Emitter Follower discussion on page in Sedra & Smith.

EE105 Fall 2015 Microelectronic Devices and Circuits

EE105 Fall 2015 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 11-1 Transistor Operating Mode in Amplifiers Transistors are biased in flat part of