Analysis and Design of Analog Integrated Circuits Lecture 18. Key Opamp Specifications

Transcription

1 Analysis and Design of Analog Integrated Circuits Lecture 8 Key Opamp Specifications Michael H. Perrott April 8, 0 Copyright 0 by Michael H. Perrott All rights reserved.

2 Recall: Key Specifications of Opamps (Open Loop) R huge For Open Loop Characterization C huge V dd Set R huge >> Z out V in V ss Z out and /(R huge C huge ) << w dom 0log(K) V dd 0log /V in 0dB V in V ss DC small signal gain: K Unity gain frequency: w 0 Dominant pole frequency: w dom Parasitic pole frequencies: w p (and higher order poles) Output swing (max output range for DC gain > K min ) w (rad/s) w dom w 0 w p

3 Recall: Key Specifications of Opamps (Closed Loop) V dd V offset V in V ss Offset voltage Settling time (closed loop bandwidth) Input common mode range Equivalent Input-Referred Noise Common-Mode Rejection Ratio (CMRR) CMRR = Ã! δvoffset δv in Power Supply Rejection Ratio (PSRR) Ã! PSRR + δvoffset = PSRR = δv dd Ã! δvoffset δv ss 3

4 Basic Two Stage CMOS Op Amp M 8 M 7 M 5 I ref V in- M M V in+ R c M 3 M 4 M 6 This is a common workhorse opamp for medium performance applications Provides a nice starting point to discuss various CMOS opamp design issues Starting assumptions: W /L = W /L, W 3 /L 3 = W 4 /L 4 4

5 Key Specifications Discussed In This Lecture Systematic offset voltage CMRR PSRR + and PSRR - Input-referred voltage noise Slew rate 5

6 A Closer Look at Offset Voltage V in- V dd = H(s) ³V in+ V in V off V in+ V off V ss V off V in V in- V in+ V off V dd Assume: - Input to opamp is a DC signal - Amplifier is not saturated - DC gain of amplifier is large = K ³V in+ V in V off V in+ V in = V off + /K V off Two sources of offset: systematic and random 6

7 Systematic Offset: First Stage Analysis M 8 M 7 M 5 I bias I ref V in- M M V in+ I bias I bias R c V gs3 M 6 M 3 M 4 For zero systematic offset we want to be at roughly mid-rail assuming V in+ = V in- - V in+ = V in- leads to equal currents in M 3 /M 4 - Equal currents and equal V gs for M 3 /M 4 leads to: V ds4 = V ds3 = V gs3 7

8 Key Constraints To Achieve Zero Systematic Offset M 8 M 7 M 5 I bias I bias I ref V in- M M V in+ I bias I bias R c I d6 assume L 6 = L 3 = L 4 V gs3 M 6 M 3 M 4 For mid-rail, we need I d6 = I bias Also: I d6 = μ nc ox W 6 μ nc ox W 3 L 3 L 6 ³ Vgs3 V TH = Ibias ³ Vgs3 V TH = I bias W 6 W 3 = I bias I bias = W 7 W 5 8

9 Key Common-Mode Rejection (CMRR) Observations M 8 M 7 M 5 I bias I ref V in- M M V in+ R c M 6 M 3 CMRR defined as a vd /a vc, where a vd = a vd a vd a vc = a vc a vd Inspection of the above reveals that CMRR is determined by the first stage M 4 CMRR = a vda vd a vc a vd = a vd a vc = CMRR 9

10 Common Mode Gain and Resulting CMRR r o5 r o5 r o5 r o5 r o5 V in- M M V in+ v ic M M v ic v ic M M v ic V V V gm3 M 4 gm3 M 4 g m3 g m4 Differential gain was derived in Lecture 7 a vd = g m (r o r o4 ) Common-mode gain is calculated from the above as /g a vc = m4 /g m +r o5 g m4 r o5 CMRR = a vd a vc = g m (r o r o4 )g m4 r o5 0

11 Characterizing CMRR with Changes in Offset Voltage V dd V offset V in V ss Consider V in as a common-mode signal which has an open loop impact on as = a vc V in However, the closed loop configuration above tries to keep V in+ = V in- subject to finite differential gain a vd = a vd (V in )=a vd V offset V offset = = a vc V in a vd a vd V offset V in = a vc a vd = (CMRR)

12 Power Supply Rejection Ratio (PSRR) M 8 M 7 M 5 I bias I ref V ic M M V ic R c M 6 M 3 M 4 We now consider the impact of positive and negative supply variation on the output of the amplifier - Key assumption: V in+ = V in- = V ic Definitions: PSRR + = a vd a + PSRR = a vd a

13 Simplification of Current Mirror g m8 M 5 I bias M 7 V ic M M V ic R c M 6 M 3 M 4 Replace current reference and diode connected device M 8 with their small signal models - We see that positive and negative supply variations have no impact on V gs of M 5 and M 7 We can ignore M 8 and current reference in our PSRR analysis 3

14 Further Simplifications for PSRR Calculations M 7 r o5 r o5 r o7 M 5 I bias V ic M M V ic V ic V ic M M CL R c R c M 6 g m3 g m4 M 6 M 3 M 4 Observe that positive and negative supply variations have equal impact on both sides of the differential pair - We can use common-mode analysis for the first stage 4

15 Calculation of PSRR + At Low Frequencies r o5 r o7 v s+ M V ic CL g m4 V R c M 6 Calculation of impact of V s+ on = r o6 V s+ + g m6 (r o6 r o7 ) r o6 + r o7 a + = V s+ Ã g m4 r o5! V s+ PSRR + = a vd a vd = g m (r o r o4 )g m6 (r o6 r o7 ) a v+ 5

16 Calculation of PSRR - At Low Frequencies r o5 r o7 M V ic CL v s- g m4 V R c M 6 Calculation of impact of V s- on V Ã out r o7 V s + g m6 (r o6 r o7 ) r o6 + r o7 g m4 (g m r o )r o5 a = V s PSRR = a vd a v a vd = g m (r o r o4 )g m6 (r o6 r o7 )! V s 6

17 Characterizing PSRR with Changes in Offset Voltage V dd V offset V in V ss Consider V dd as a common-mode signal which has an open loop impact on as = a + V dd However, the closed loop configuration above tries to keep V in+ = V in- subject to finite differential gain a vd = a vd (V in )=a vd V offset V offset = = a + V dd a vd a vd V offset V dd = a + a vd = ³ PSRR + (Similar for PSRR- ) 7

18 Noise Analysis for a Two Stage Opamp v id a vd a vd v out v in a vd a vd v out v n v n a vd v n + (avd a vd ) v n Each opamp stage will contribute noise - Typically the spectral density of the noise will be of the same order at each stage Input referral of the noise reveals that the second stage noise will have much less impact than the first stage noise - Input-referred noise calculations of an opamp need only focus on the first stage 8

19 Input-Referral of MOS Device Noise V in i nd V in i g nd m Transistor drain current noise: i nd =4kT γ α g m f + K f f g m WLC ox Thermal noise /f noise Input-referred voltage noise: vni =4kT γ f + K f αg m f WLC ox f f Note: g ds0 = g m α Thermal noise /f noise Impact of thermal versus /f noise depends on g m 9

20 Analysis of Op Amp Output Noise (First Stage) v ni5 M 5 Note that impact of M 5 noise is minor since it corresponds to common-mode noise v ni v ni M M v ni3 v ni4 M 3 M 4 i sc Assume: g m = g m g m3 = g m4 i sc = g m µ vni + v ni + g m3 µ vni3 + v ni4 i sc =g m v ni +g m3 v ni3 0

21 Determining Input-Referred Noise v neq M 5 M M Output noise due to equivalent input-referred noise: i sc = g m v neq i sc M 3 M 4 Assume: g m = g m g m3 = g m4 Output noise due to individual devices (Slide 0): i sc =g m v ni +g m3 v ni3 = g m v neq Ã! vneq gm3 =v ni + vni3 g m Want g m > g m3 for low noise

22 Characterizing Input-Referred Noise V dd V offset V in V ss Placing the amplifier within unity gain feedback configuration causes the overall output noise of the amplifier to become referred to the input - We can now examine the low frequency content of the input-referred noise by simply probing the noise of

23 Recall: Slew Rate Issues for Opamps V dd V in ideal V in V ss slew-rate limited Output currents of practical opamps have max limits - Impacts maximum rate of charging or discharging load capacitance, - For large step response, this leads to the output lagging behind the ideal response based on linear modeling We refer to this condition as being slew-rate limited Where slew-rate is of concern, the output stage of the opamp can be designed to help mitigate this issue - Will lead to extra complexity and perhaps other issues 3

24 Key Observations for Slew Rate Calculations I bias I bias -V id / V id / M M R c M 3 M 4 M 6 Current Limits V id a vd I a vd I First stage - Max I = I bias - Min I = -I bias Second stage - Max I = I bias - Min I = Large 4

25 Slew Rate Analysis (First Stage Limits) V id a vd I a vd I max I = I bias min I = -I bias max I = I bias min I = Large Slew rate refers to maximum voltage slope at output - Impact of current limits in first stage: = Z I dt d = I = I bias dt max max d = I = I bias dt min min 5

26 Slew Rate Analysis (Second Stage Limits) V id a vd I a vd I max I = I bias min I = -I bias max I = I bias min I = Large Impact of current limits in second stage - Maximum slope at the output: d dt = max I bias + - Minimum slope at the output: d =Large dt min 6

27 Slew Rate Analysis (Overall) V id a vd I a vd I max I = I bias min I = -I bias max I = I bias min I = Large Maximum slope at the output: d dt =min max Minimum slope at the output: d dt min = I bias à Ibias, I bias +! 7

28 Impact of Slew Rate V dd V in V ss Consider the closed loop, unity gain configuration above with a sine wave input V in = A sin(wt) Note: the max slope of the input depends on A and w dv in = Aw cos(wt) d = Aw dt dt max Slew rate limits the maximum frequency that the amplifier can track 8

29 Summary Opamp design must take into consideration many different specifcations Today we covered - Systematic offset voltage - CMRR - PSRR + and PSRR - - Input-referred voltage noise - Slew rate 9