Radivoje Đurić, 2015, Analogna Integrisana Kola 1

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Radivoje Đurić, 2015, Analogna Integrisana Kola 1"

Transcription

1 OTA-output buffer 1

2 According to the types of loads, the driving capability of the output stages differs. For switched capacitor circuits which have high impedance capacitive loads, class A output stage isagood choice For other applications, especially when the amplifier needs to drive off chip low resistive or high capacitive load, like earphone, class B or class AB output stage has to be utilized to have a large driving capability, and at the same time, a small quiescent current to save power especially in battery operated equipment. The output stage usually consumes most of the power of the amplifier in such cases. For low voltage designs, a rail-to-rail output swing is desirable to efficiently utilize the power supply voltage. Common-drain voltage follower output stage (Fig. (a)) is rarely used in low voltage design due to its small output voltage swing as a result of stacking of V GS,P and V GS,N. Instead, we have to use common source class AB configurations (Fig. (b)). 2

3 CMOS inverter-common Source Output Stages For a low-resistor load, a low output impedance is required. The source follower is the only simple transistor t stage which h provides this output t resistance. However, its DC current handling is not sufficient. For higher output voltages, we would need higher biasing currents as well. This would lead to an excessive power consumption. We now need a transistor circuit which can deliver large currents only when needed, but with a low quiescent biasing current to lower the power consumption as much as possible. Simple CMOS class-ab amplifier: The main disadvantage of this circuit is that its two VGS s are between supply voltage and ground. As a consequence, the quiescent current depends on the supply voltage. 3

4 Large Output Current Buffer-Common Source class AB In the case where the load consists of a large capacitor, the ability to sink and source a large current is much more important than reducing the output resistance. Consequently, the common-source, push-pull is ideal if the quiescent current can be controlled. If W4/L4 = W9/L9 and W3/L3 = W8/L8, then the quiescent currents in M1 and M2 can be determined by the following relationship: W / L1 W / L2 I1 I2 Ib Ib W / L W / L 7 10 When Vin is increased, M6 turns off M2 and turns on M1 to source current. Similarly, when Vin is decreased, M5 turns off M1 and turns on M2 to sink current. 4

5 CMOS amplifier with a class AB input stage Using the square-law model for MOS devices in the saturation region, the drain currents are given by Applying Kirchhoff s voltage law on the left and right sides of the transconductor, we have The transfer characteristic ti of the differential stage is plotted in the next figure. The corresponding transconductance is The transistors remain in the saturation region provided that 5

6 Due to the biasing condition realized by source followers T5 T8, a current can flow through the input stage even for zero differential input. Given an increase in the voltage on the positive input and a corresponding decrease on the negative input, the drain currents of T1 and T4, and the ones of T2 and T3 increase and decrease from their initial values, as a result of a rise and reduction of their gate-source voltages, respectively. That is, the current in one side of the differential stage increases monotonically with the applied voltage and is limited by the power supply level, while the one in the otherside decreases until a transistor turns off. The input currents are then directed to the output branches by current mirrors. The cascode transistors, T17 T20, are used to increase the amplifier gain. The conflicting requirements of high output current during the slewing period and large output swing during the settling are met by dynamically biasing the gates of cascode transistors so that the common-source transistors T13 T16 remain in the saturation region. The common-mode feedback is realized by controlling the bias current of T29 and T30. Transistors T31 and T32 are connected to the bias voltage, VB, in order to deliver constant currents. 6

7 Cross-coupled transistor based Fully Differential Op amp 7

8 Complementary Common Source Output Stage Independent loop is used to set each floating voltage required for the biasing of the output transistor. In the class AB output stage implementation shown in Figure (b), the common-source connected output transistors, T1 and T2, are driven by in-phase input signals. The quiescent current flowing through the output transistors is determined by two independent translinear loops. Let the transistors of the same channel type be designed with identical threshold voltages and mobility parameters. Using Kirchhoff s voltage law for the loop including T1,T4, T7, and T8, we obtain 8

9 Based on the square law characteristic of transistors, the current I1 can be written as Considering the loop formed by T2, T3, T5, and T6, the voltage equation is of the form It can then be shown that To proceed further, we assume that When the output current I0 is set to zero, each of the currents I1 and I2 is reduced to the quiescent current, IQ, flowing through the transistors T1 and T2. Hence, The maximum value of the current I1 is obtained when T4 is forced to operate in the cutoff region, that is, V SG4 V Tp, and the overall current 2I B1 flows through T3. As a result, 9

10 The current I2 is reduced to the minimum value given by Similarly, when the current I1 becomes equal to its minimum value, due to the fact that T3 is forced to operate in the cutoff region, that is, V GS3 V Tn, the overall current 2I B1 flows through T4. The current I2 is then set to its maximum value. Frequency compensation by using C gs, C gd and C gb Similar to conventional two-stage operational amplifiers, Miller compensation capacitors are used to stabilize the operation of the op amp in closed loop operation. The compensation capacitor is placed across the complementary output gain stage, and the dominant pole frequency of the overall amplifier will then be g mi p gm0rlcc where g mi is the input device transconductance, MA3 or MA4, and g m0 is the output device transconductance MA1 or MA2. 10

11 Rail to rail operational amplifier schematic: 11

12 Low voltage class AB output stage In general, the minimum supply voltage is limited by the output stage, which uses transistors operating with sufficiently high gate-source voltages in order to drive high output currents. To reduce the minimum value of the supply voltage to the sum of one gate source voltage and two saturation voltages, the gate voltages of the output transistors T1 and T2aresetbythe folded mesh loop consisting of T3 T6, which, together with the minimum current selector realized by T7 T10, also regulates the minimum i current flowing throughh the output t transistors. 12

13 The transistors T12, T4, T6, and T11 form a translinear loop, which defines the current IREF. Applying Kirchhoff s voltage law around this loop gives Hence, When K n4 =K n6, the expression of the current I REF is reduced to 13

14 For the loop including transistors T1, T10, and T9, Kirchhoff s voltage law equation can be written as Because V GS2 = V GS7,wehave I D7 = I 2 = I D8. Using the fact thatt we obtain Assuming that I 1 =I 2 =I Q and K p1 =K p8, it can be deduced that where I Q is the quiescent current flowing through the output transistors. During normal operation, the transistor T9 operates in the linear region, where its drain current is a function of both the source-gate voltage set by the transistor t T8 and the sourcedrain voltage adjusted via the transistor T10. 14

15 The source-drain voltage of the transistor T9, or the source voltage of the transistor T10, can then be maintained sufficiently low such that the variations in the current I1 can be tracked by the transistor t T10. The transistor T7, which operates with the same gate-source voltage as the transistor T2, is used to detect the current I2. The minimum selector circuit T7 T10 then evaluates the magnitudes of the currents I1 and I2 to help set a minimum current flowing through each of the output transistorsasafunctionof the current I REF. However, as the drain current of the transistor T1 increases such that its source-gate voltage becomes sufficiently i highh to provide enough headroom for the operation of T9 in the saturation ti region, the transistors T8 T10 realize a cascoded current mirror. When the current I2 reaches its minimum value, I Q /2, the maximum value of the current I1 is 2I Q. With V SD9 =V SG9 V Tp and V SG9 =V SG10,V SG1 =2V SG9 and the drain current of T9 is equal to I Q /2. Because V SG8 =V SG9, the bias current of the transistor T7 is also set to I Q /2. On the other hand, an increase in the current I2 produces an augmentation ti of the current flowing throughh T7 and T8, and a decrease in the current I1 leading to a reduction in the source-gate voltage of the transistor T1. The source-gate voltage of the transistor T1 can then be reduced until the source-drain voltage of the transistor T9 becomes negligible. Hence, V SG1 V SG10 and the current I1 takes the minimum value I Q /2, while the current I2 is maximum. It should be noted that the stability can be affected by poles associated with the folded mesh loop, the current mirror T8 T9 and cascode transistor t T10. 15

16 Low-voltage compact op-amp with PMOS input stage and folded mesh with simple minimum selector (PMOS). 16

17 Use of the BJT in Buffered Op Amps Substrate BJTs Illustration of an NPN substrate BJT available in a p-well CMOS technology: Comments: gm of the BJT is larger than the FET so that the output resistance w/o feedback is lower Collector current will be flowing in the substrate Current is required to drive the BJT Only an NPN or a PNP bipolar transistor is available 17

18 A Lateral Bipolar Transistor n-well CMOS technology: It is desirable to have the lateral collector current much larger than the vertical collector current. Triple well technology allows the current of the vertical collector to avoid flowing in the substrate. Lateral BJT generally has good matching. A Field-Aided Lateral BJT: Use minimum channel length to enhance beta, ßF 50 to 100 depending on the process 18

19 Two-Stage Op Amp with a Class-A BJT Output Buffer Stage Purpose of the M8-M9 source follower: 1) Reduce the output t resistance (includes whatever is seen from the base to ground divided by 1+βF). 2) Reduces the output load at the drains of M6 and M7 Two-Stage Folded Casode Op Amp with a Class-A BJT Output Buffer Stage 19

20 TSMC180: npn 5x5 F f I C 20

21 TSMC130: npn 5x5 F f I C 21

22 TSMC90: npn 5x5 F f I C 22

23 TSMC130: pnp 2x2 F f I C 23

Index. Small-Signal Models, 14 saturation current, 3, 5 Transistor Cutoff Frequency, 18 transconductance, 16, 22 transit time, 10

Index. Small-Signal Models, 14 saturation current, 3, 5 Transistor Cutoff Frequency, 18 transconductance, 16, 22 transit time, 10 Index A absolute value, 308 additional pole, 271 analog multiplier, 190 B BiCMOS,107 Bode plot, 266 base-emitter voltage, 16, 50 base-emitter voltages, 296 bias current, 111, 124, 133, 137, 166, 185 bipolar

More information

Chapter 12 Opertational Amplifier Circuits

Chapter 12 Opertational Amplifier Circuits 1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded cascode circuit.

More information

Solid State Devices & Circuits. 18. Advanced Techniques

Solid State Devices & Circuits. 18. Advanced Techniques ECE 442 Solid State Devices & Circuits 18. Advanced Techniques Jose E. Schutt-Aine Electrical l&c Computer Engineering i University of Illinois jschutt@emlab.uiuc.edu 1 Darlington Configuration - Popular

More information

d. Can you find intrinsic gain more easily by examining the equation for current? Explain.

d. Can you find intrinsic gain more easily by examining the equation for current? Explain. EECS140 Final Spring 2017 Name SID 1. [8] In a vacuum tube, the plate (or anode) current is a function of the plate voltage (output) and the grid voltage (input). I P = k(v P + µv G ) 3/2 where µ is a

More information

Design and Simulation of Low Voltage Operational Amplifier

Design and Simulation of Low Voltage Operational Amplifier Design and Simulation of Low Voltage Operational Amplifier Zach Nelson Department of Electrical Engineering, University of Nevada, Las Vegas 4505 S Maryland Pkwy, Las Vegas, NV 89154 United States of America

More information

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1 Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1 LECTURE 300 LOW VOLTAGE OP AMPS LECTURE ORGANIZATION Outline Introduction Low voltage input stages Low voltage gain stages Low voltage bias circuits

More information

Class-AB Low-Voltage CMOS Unity-Gain Buffers

Class-AB Low-Voltage CMOS Unity-Gain Buffers Class-AB Low-Voltage CMOS Unity-Gain Buffers Mariano Jimenez, Antonio Torralba, Ramón G. Carvajal and J. Ramírez-Angulo Abstract Class-AB circuits, which are able to deal with currents several orders of

More information

Hello, and welcome to the TI Precision Labs video series discussing comparator applications. The comparator s job is to compare two analog input

Hello, and welcome to the TI Precision Labs video series discussing comparator applications. The comparator s job is to compare two analog input Hello, and welcome to the TI Precision Labs video series discussing comparator applications. The comparator s job is to compare two analog input signals and produce a digital or logic level output based

More information

A 16Ω Audio Amplifier with 93.8 mw Peak loadpower and 1.43 quiscent power consumption

A 16Ω Audio Amplifier with 93.8 mw Peak loadpower and 1.43 quiscent power consumption A 16Ω Audio Amplifier with 93.8 mw Peak loadpower and 1.43 quiscent power consumption IEEE Transactions on circuits and systems- Vol 59 No:3 March 2012 Abstract A class AB audio amplifier is used to drive

More information

ES 330 Electronics II Homework # 6 Soltuions (Fall 2016 Due Wednesday, October 26, 2016)

ES 330 Electronics II Homework # 6 Soltuions (Fall 2016 Due Wednesday, October 26, 2016) Page1 Name Solutions ES 330 Electronics Homework # 6 Soltuions (Fall 016 ue Wednesday, October 6, 016) Problem 1 (18 points) You are given a common-emitter BJT and a common-source MOSFET (n-channel). Fill

More information

CMOS Operational-Amplifier

CMOS Operational-Amplifier CMOS Operational-Amplifier 1 What will we learn in this course How to design a good OP Amp. Basic building blocks Biasing and Loading Swings and Bandwidth CH2(8) Operational Amplifier as A Black Box Copyright

More information

A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage

A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage EEE 523 Advanced Analog Integrated Circuits Project Report Fuding Ge You are an engineer who is assigned the project to design

More information

Microelectronic Circuits II. Ch 10 : Operational-Amplifier Circuits

Microelectronic Circuits II. Ch 10 : Operational-Amplifier Circuits Microelectronic Circuits II Ch 0 : Operational-Amplifier Circuits 0. The Two-stage CMOS Op Amp 0.2 The Folded-Cascode CMOS Op Amp CNU EE 0.- Operational-Amplifier Introduction - Analog ICs : operational

More information

Low Power Op-Amp Based on Weak Inversion with Miller-Cascoded Frequency Compensation

Low Power Op-Amp Based on Weak Inversion with Miller-Cascoded Frequency Compensation Low Power Op-Amp Based on Weak Inversion with Miller-Cascoded Frequency Compensation Maryam Borhani, Farhad Razaghian Abstract A design for a rail-to-rail input and output operational amplifier is introduced.

More information

BJT Amplifier. Superposition principle (linear amplifier)

BJT Amplifier. Superposition principle (linear amplifier) BJT Amplifier Two types analysis DC analysis Applied DC voltage source AC analysis Time varying signal source Superposition principle (linear amplifier) The response of a linear amplifier circuit excited

More information

Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation

Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation Rail-To-Rail Op-Amp Design with Negative Miller Capacitance Compensation Muhaned Zaidi, Ian Grout, Abu Khari bin A ain Abstract In this paper, a two-stage op-amp design is considered using both Miller

More information

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,

More information

INF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation

INF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation INF3410 Fall 2013 Compensation content Introduction Two Stage Opamps Compensation Slew Rate Systematic Offset Advanced Current Mirrors Operational Transconductance Amplifiers Current Mirror Opamps Folded

More information

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

Radivoje Đurić, 2015, Analogna Integrisana Kola 1 Low power OTA 1 Two-Stage, Miller Op Amp Operating in Weak Inversion Low frequency response: gm1 gm6 Av 0 g g g g A v 0 ds2 ds4 ds6 ds7 I D m, ds D nvt g g I n GB and SR: GB 1 1 n 1 2 4 6 6 7 g 2 2 m1

More information

Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching

Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching RESEARCH ARTICLE OPEN ACCESS Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching Annu Saini, Prity Yadav (M.Tech. Student, Department

More information

444 Index. F Fermi potential, 146 FGMOS transistor, 20 23, 57, 83, 84, 98, 205, 208, 213, 215, 216, 241, 242, 251, 280, 311, 318, 332, 354, 407

444 Index. F Fermi potential, 146 FGMOS transistor, 20 23, 57, 83, 84, 98, 205, 208, 213, 215, 216, 241, 242, 251, 280, 311, 318, 332, 354, 407 Index A Accuracy active resistor structures, 46, 323, 328, 329, 341, 344, 360 computational circuits, 171 differential amplifiers, 30, 31 exponential circuits, 285, 291, 292 multifunctional structures,

More information

CMOS Operational-Amplifier

CMOS Operational-Amplifier CMOS Operational-Amplifier 1 What will we learn in this course How to design a good OP Amp. Basic building blocks Biasing and Loading Swings and Bandwidth CH2(8) Operational Amplifier as A Black Box Copyright

More information

ECE 442 Solid State Devices & Circuits. 15. Differential Amplifiers

ECE 442 Solid State Devices & Circuits. 15. Differential Amplifiers ECE 442 Solid State Devices & Circuits 15. Differential Amplifiers Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 442 Jose Schutt Aine 1 Background

More information

Advanced Operational Amplifiers

Advanced Operational Amplifiers IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage

More information

TWO AND ONE STAGES OTA

TWO AND ONE STAGES OTA TWO AND ONE STAGES OTA F. Maloberti Department of Electronics Integrated Microsystem Group University of Pavia, 7100 Pavia, Italy franco@ele.unipv.it tel. +39-38-50505; fax. +39-038-505677 474 EE Department

More information

Design of High-Speed Op-Amps for Signal Processing

Design of High-Speed Op-Amps for Signal Processing Design of High-Speed Op-Amps for Signal Processing R. Jacob (Jake) Baker, PhD, PE Professor and Chair Boise State University 1910 University Dr. Boise, ID 83725-2075 jbaker@ieee.org Abstract - As CMOS

More information

Low-Voltage Wide Linear Range Tunable Operational Transconductance Amplifier

Low-Voltage Wide Linear Range Tunable Operational Transconductance Amplifier Low-Voltage Wide Linear Range Tunable Operational Transconductance Amplifier A dissertation submitted in partial fulfillment of the requirement for the award of degree of Master of Technology in VLSI Design

More information

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,

More information

Advanced OPAMP Design

Advanced OPAMP Design Advanced OPAMP Design Two Stage OPAMP with Cascoding To increase the gain, the idea of cascoding can be combined with the idea of cascading. A two stage amplifier with one stage being cascode is possible.

More information

INF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation

INF3410 Fall Book Chapter 6: Basic Opamp Design and Compensation INF3410 Fall 2015 Book Chapter 6: Basic Opamp Design and Compensation content Introduction Two Stage Opamps Compensation Slew Rate Systematic Offset Advanced Current Mirrors Operational Transconductance

More information

Basic Circuits. Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair,

Basic Circuits. Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair, Basic Circuits Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair, CCS - Basic Circuits P. Fischer, ZITI, Uni Heidelberg, Seite 1 Reminder: Effect of Transistor Sizes Very crude classification:

More information

Gechstudentszone.wordpress.com

Gechstudentszone.wordpress.com UNIT 4: Small Signal Analysis of Amplifiers 4.1 Basic FET Amplifiers In the last chapter, we described the operation of the FET, in particular the MOSFET, and analyzed and designed the dc response of circuits

More information

55:041 Electronic Circuits

55:041 Electronic Circuits 55:041 Electronic Circuits MOSFETs Sections of Chapter 3 &4 A. Kruger MOSFETs, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width = 1 10-6 m or less Thickness = 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor

More information

Rail to Rail Input Amplifier with constant G M and High Unity Gain Frequency. Arun Ramamurthy, Amit M. Jain, Anuj Gupta

Rail to Rail Input Amplifier with constant G M and High Unity Gain Frequency. Arun Ramamurthy, Amit M. Jain, Anuj Gupta 1 Rail to Rail Input Amplifier with constant G M and High Frequency Arun Ramamurthy, Amit M. Jain, Anuj Gupta Abstract A rail to rail input, 2.5V CMOS input amplifier is designed that amplifies uniformly

More information

Lecture 34: Designing amplifiers, biasing, frequency response. Context

Lecture 34: Designing amplifiers, biasing, frequency response. Context Lecture 34: Designing amplifiers, biasing, frequency response Prof J. S. Smith Context We will figure out more of the design parameters for the amplifier we looked at in the last lecture, and then we will

More information

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic

More information

Chapter 7 Building Blocks of Integrated Circuit Amplifiers: Part D: Advanced Current Mirrors

Chapter 7 Building Blocks of Integrated Circuit Amplifiers: Part D: Advanced Current Mirrors 1 Chapter 7 Building Blocks of Integrated Circuit Amplifiers: Part D: Advanced Current Mirrors Current Mirror Example 2 Two Stage Op Amp (MOSFET) Current Mirror Example Three Stage 741 Opamp (BJT) 3 4

More information

55:041 Electronic Circuits The University of Iowa Fall Exam 3. Question 1 Unless stated otherwise, each question below is 1 point.

55:041 Electronic Circuits The University of Iowa Fall Exam 3. Question 1 Unless stated otherwise, each question below is 1 point. Exam 3 Name: Score /65 Question 1 Unless stated otherwise, each question below is 1 point. 1. An engineer designs a class-ab amplifier to deliver 2 W (sinusoidal) signal power to an resistive load. Ignoring

More information

Lecture 240 Cascode Op Amps (3/28/10) Page 240-1

Lecture 240 Cascode Op Amps (3/28/10) Page 240-1 Lecture 240 Cascode Op Amps (3/28/10) Page 2401 LECTURE 240 CASCODE OP AMPS LECTURE ORGANIZATION Outline Lecture Organization Single Stage Cascode Op Amps Two Stage Cascode Op Amps Summary CMOS Analog

More information

F9 Differential and Multistage Amplifiers

F9 Differential and Multistage Amplifiers Lars Ohlsson 018-10-0 F9 Differential and Multistage Amplifiers Outline MOS differential pair Common mode signal operation Differential mode signal operation Large signal operation Small signal operation

More information

Reading. Lecture 33: Context. Lecture Outline. Chapter 9, multi-stage amplifiers. Prof. J. S. Smith

Reading. Lecture 33: Context. Lecture Outline. Chapter 9, multi-stage amplifiers. Prof. J. S. Smith eading Lecture 33: Chapter 9, multi-stage amplifiers Prof J. S. Smith Context Lecture Outline We are continuing to review some of the building blocks for multi-stage amplifiers, including current sources

More information

Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem

Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem A report Submitted to Canopus Systems Inc. Zuhail Sainudeen and Navid Yazdi Arizona State University July 2001 1. Overview

More information

Lecture 33: Context. Prof. J. S. Smith

Lecture 33: Context. Prof. J. S. Smith Lecture 33: Prof J. S. Smith Context We are continuing to review some of the building blocks for multi-stage amplifiers, including current sources and cascode connected devices, and we will also look at

More information

Microelectronic Devices and Circuits Lecture 22 - Diff-Amp Anal. III: Cascode, µa Outline Announcements DP:

Microelectronic Devices and Circuits Lecture 22 - Diff-Amp Anal. III: Cascode, µa Outline Announcements DP: 6.012 Microelectronic Devices and Circuits Lecture 22 DiffAmp Anal. III: Cascode, µa741 Outline Announcements DP: Discussion of Q13, Q13' impact. Gain expressions. Review Output Stages DC Offset of an

More information

An Improved Bandgap Reference (BGR) Circuit with Constant Voltage and Current Outputs

An Improved Bandgap Reference (BGR) Circuit with Constant Voltage and Current Outputs International Journal of Research in Engineering and Innovation Vol-1, Issue-6 (2017), 60-64 International Journal of Research in Engineering and Innovation (IJREI) journal home page: http://www.ijrei.com

More information

A CMOS Low-Voltage, High-Gain Op-Amp

A CMOS Low-Voltage, High-Gain Op-Amp A CMOS Low-Voltage, High-Gain Op-Amp G N Lu and G Sou LEAM, Université Pierre et Marie Curie Case 203, 4 place Jussieu, 75252 Paris Cedex 05, France Telephone: (33 1) 44 27 75 11 Fax: (33 1) 44 27 48 37

More information

ECE315 / ECE515 Lecture 8 Date:

ECE315 / ECE515 Lecture 8 Date: ECE35 / ECE55 Lecture 8 Date: 05.09.06 CS Amplifier with Constant Current Source Current Steering Circuits CS Stage Followed by CG Stage Cascode as Current Source Cascode as Amplifier ECE35 / ECE55 CS

More information

Atypical op amp consists of a differential input stage,

Atypical op amp consists of a differential input stage, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 6, JUNE 1998 915 Low-Voltage Class Buffers with Quiescent Current Control Fan You, S. H. K. Embabi, and Edgar Sánchez-Sinencio Abstract This paper presents

More information

Analog Integrated Circuit Configurations

Analog Integrated Circuit Configurations Analog Integrated Circuit Configurations Basic stages: differential pairs, current biasing, mirrors, etc. Approximate analysis for initial design MOSFET and Bipolar circuits Basic Current Bias Sources

More information

Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier

Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in double-ended

More information

LOW-VOLTAGE, CLASS AB AND HIGH SLEW-RATE TWO STAGE OPERATIONAL AMPLIFIERS. CARLOS FERNANDO NIEVA-LOZANO, B.Sc.E.E

LOW-VOLTAGE, CLASS AB AND HIGH SLEW-RATE TWO STAGE OPERATIONAL AMPLIFIERS. CARLOS FERNANDO NIEVA-LOZANO, B.Sc.E.E LOW-VOLTAGE, CLASS AB AND HIGH SLEW-RATE TWO STAGE OPERATIONAL AMPLIFIERS BY CARLOS FERNANDO NIEVA-LOZANO, B.Sc.E.E A thesis submitted to the Graduate School in partial fulfillment of the requirements

More information

Revision History. Contents

Revision History. Contents Revision History Ver. # Rev. Date Rev. By Comment 0.0 9/15/2012 Initial draft 1.0 9/16/2012 Remove class A part 2.0 9/17/2012 Comments and problem 2 added 3.0 10/3/2012 cmdmprobe re-simulation, add supplement

More information

ECEN 474/704 Lab 6: Differential Pairs

ECEN 474/704 Lab 6: Differential Pairs ECEN 474/704 Lab 6: Differential Pairs Objective Design, simulate and layout various differential pairs used in different types of differential amplifiers such as operational transconductance amplifiers

More information

4.2.2 Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

4.2.2 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 4.2.2 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) The Metal Oxide Semitonductor Field Effect Transistor (MOSFET) has two modes of operation, the depletion mode, and the enhancement mode.

More information

CHAPTER 3. Instrumentation Amplifier (IA) Background. 3.1 Introduction. 3.2 Instrumentation Amplifier Architecture and Configurations

CHAPTER 3. Instrumentation Amplifier (IA) Background. 3.1 Introduction. 3.2 Instrumentation Amplifier Architecture and Configurations CHAPTER 3 Instrumentation Amplifier (IA) Background 3.1 Introduction The IAs are key circuits in many sensor readout systems where, there is a need to amplify small differential signals in the presence

More information

55:041 Electronic Circuits

55:041 Electronic Circuits 55:041 Electronic Circuits Mosfet Review Sections of Chapter 3 &4 A. Kruger Mosfet Review, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width 1 10-6 m or less Thickness 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor

More information

Lecture 030 ECE4430 Review III (1/9/04) Page 030-1

Lecture 030 ECE4430 Review III (1/9/04) Page 030-1 Lecture 030 ECE4430 Review III (1/9/04) Page 0301 LECTURE 030 ECE 4430 REVIEW III (READING: GHLM Chaps. 3 and 4) Objective The objective of this presentation is: 1.) Identify the prerequisite material

More information

Design of Low Voltage Low Power CMOS OP-AMP

Design of Low Voltage Low Power CMOS OP-AMP RESEARCH ARTICLE OPEN ACCESS Design of Low Voltage Low Power CMOS OP-AMP Shahid Khan, Prof. Sampath kumar V. Electronics & Communication department, JSSATE ABSTRACT Operational amplifiers are an integral

More information

EE 501 Lab 10 Output Amplifier Due: December 10th, 2015

EE 501 Lab 10 Output Amplifier Due: December 10th, 2015 EE 501 Lab 10 Output Amplifier Due: December 10th, 2015 Objective: Get familiar with output amplifier. Design an output amplifier driving small resistor load. Design an output amplifier driving large capacitive

More information

Current Mirrors. Basic BJT Current Mirror. Current mirrors are basic building blocks of analog design. Figure shows the basic NPN current mirror.

Current Mirrors. Basic BJT Current Mirror. Current mirrors are basic building blocks of analog design. Figure shows the basic NPN current mirror. Current Mirrors Basic BJT Current Mirror Current mirrors are basic building blocks of analog design. Figure shows the basic NPN current mirror. For its analysis, we assume identical transistors and neglect

More information

Operational Amplifiers

Operational Amplifiers CHAPTER 9 Operational Amplifiers Analog IC Analysis and Design 9- Chih-Cheng Hsieh Outline. General Consideration. One-Stage Op Amps / Two-Stage Op Amps 3. Gain Boosting 4. Common-Mode Feedback 5. Input

More information

CSE 577 Spring Insoo Kim, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Penn State University

CSE 577 Spring Insoo Kim, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Penn State University CSE 577 Spring 2011 Basic Amplifiers and Differential Amplifier, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Penn State University Don t let the computer

More information

Design Analysis and Performance Comparison of Low Power High Gain 2nd Stage Differential Amplifier Along with 1st Stage

Design Analysis and Performance Comparison of Low Power High Gain 2nd Stage Differential Amplifier Along with 1st Stage Design Analysis and Performance Comparison of Low Power High Gain 2nd Stage Differential Amplifier Along with 1st Stage Sadeque Reza Khan Department of Electronic and Communication Engineering, National

More information

UNIT-1 Bipolar Junction Transistors. Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press

UNIT-1 Bipolar Junction Transistors. Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press UNIT-1 Bipolar Junction Transistors Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press Figure 6.1 A simplified structure of the npn transistor. Microelectronic Circuits, Sixth

More information

Experiment 9- Single Stage Amplifiers with Passive Loads - MOS

Experiment 9- Single Stage Amplifiers with Passive Loads - MOS Experiment 9- Single Stage Amplifiers with Passive oads - MOS D. Yee,.T. Yeung, M. Yang, S.M. Mehta, and R.T. Howe UC Berkeley EE 105 1.0 Objective This is the second part of the single stage amplifier

More information

Design of High Gain Two stage Op-Amp using 90nm Technology

Design of High Gain Two stage Op-Amp using 90nm Technology Design of High Gain Two stage Op-Amp using 90nm Technology Shaik Aqeel 1, P. Krishna Deva 2, C. Mahesh Babu 3 and R.Ganesh 4 1 CVR College of Engineering/UG Student, Hyderabad, India 2 CVR College of Engineering/UG

More information

ECEN474: (Analog) VLSI Circuit Design Fall 2011

ECEN474: (Analog) VLSI Circuit Design Fall 2011 ECEN474: (Analog) VLSI Circuit Design Fall 20 Lecture 22: Output Stages Sebastian Hoyos Analog & Mixed-Signal Center Texas A&M University Agenda Output Stages Source Follower (Class A) Push-Pull (Class

More information

DESIGN OF A PROGRAMMABLE LOW POWER LOW DROP-OUT REGULATOR

DESIGN OF A PROGRAMMABLE LOW POWER LOW DROP-OUT REGULATOR DESIGN OF A PROGRAMMABLE LOW POWER LOW DROP-OUT REGULATOR Jayanthi Vanama and G.L.Sampoorna Trainee Engineer, Powerwave Technologies Pvt. Ltd., R&D India jayanthi.vanama@pwav.com Intern, CONEXANT Systems

More information

EE301 Electronics I , Fall

EE301 Electronics I , Fall EE301 Electronics I 2018-2019, Fall 1. Introduction to Microelectronics (1 Week/3 Hrs.) Introduction, Historical Background, Basic Consepts 2. Rewiev of Semiconductors (1 Week/3 Hrs.) Semiconductor materials

More information

Design of a Capacitor-less Low Dropout Voltage Regulator

Design of a Capacitor-less Low Dropout Voltage Regulator Design of a Capacitor-less Low Dropout Voltage Regulator Sheenam Ahmed 1, Isha Baokar 2, R Sakthivel 3 1 Student, M.Tech VLSI, School of Electronics Engineering, VIT University, Vellore, Tamil Nadu, India

More information

Lecture 13. Biasing and Loading Single Stage FET Amplifiers. The Building Blocks of Analog Circuits - III

Lecture 13. Biasing and Loading Single Stage FET Amplifiers. The Building Blocks of Analog Circuits - III Lecture 3 Biasing and Loading Single Stage FET Amplifiers The Building Blocks of Analog Circuits III In this lecture you will learn: Current biasing of circuits Current sources and sinks for CS, CG, and

More information

Design and Layout of Two Stage High Bandwidth Operational Amplifier

Design and Layout of Two Stage High Bandwidth Operational Amplifier Design and Layout of Two Stage High Bandwidth Operational Amplifier Yasir Mahmood Qureshi Abstract This paper presents the design and layout of a two stage, high speed operational amplifiers using standard

More information

COMPARISON OF THE MOSFET AND THE BJT:

COMPARISON OF THE MOSFET AND THE BJT: COMPARISON OF THE MOSFET AND THE BJT: In this section we present a comparison of the characteristics of the two major electronic devices: the MOSFET and the BJT. To facilitate this comparison, typical

More information

University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1. A High Speed Operational Amplifier

University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1. A High Speed Operational Amplifier University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1 A High Speed Operational Amplifier A. Halim El-Saadi, Mohammed El-Tanani, University of Michigan Abstract This paper

More information

AN increasing number of video and communication applications

AN increasing number of video and communication applications 1470 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 9, SEPTEMBER 1997 A Low-Power, High-Speed, Current-Feedback Op-Amp with a Novel Class AB High Current Output Stage Jim Bales Abstract A complementary

More information

Building Blocks of Integrated-Circuit Amplifiers

Building Blocks of Integrated-Circuit Amplifiers CHAPTER 7 Building Blocks of Integrated-Circuit Amplifiers Introduction 7. 493 IC Design Philosophy 7. The Basic Gain Cell 494 495 7.3 The Cascode Amplifier 506 7.4 IC Biasing Current Sources, Current

More information

Chapter 10 Feedback ECE 3120 Microelectronics II Dr. Suketu Naik

Chapter 10 Feedback ECE 3120 Microelectronics II Dr. Suketu Naik 1 Chapter 10 Feedback Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: Active-Loaded Differential Pair 4. Ch 10: Feedback 5. Ch 11: Output

More information

Lecture 14. FET Current and Voltage Sources and Current Mirrors. The Building Blocks of Analog Circuits - IV

Lecture 14. FET Current and Voltage Sources and Current Mirrors. The Building Blocks of Analog Circuits - IV Lecture 4 FET Current and oltage s and Current Mirrors The Building Blocks of Analog Circuits n this lecture you will learn: Current and voltage sources using FETs FET current mirrors Cascode current mirror

More information

Design and Simulation of Low Dropout Regulator

Design and Simulation of Low Dropout Regulator Design and Simulation of Low Dropout Regulator Chaitra S Kumar 1, K Sujatha 2 1 MTech Student, Department of Electronics, BMSCE, Bangalore, India 2 Assistant Professor, Department of Electronics, BMSCE,

More information

Output Stage and Power Amplifiers

Output Stage and Power Amplifiers Microelectronic Circuits Output Stage and ower Amplifiers Slide 1 ntroduction Most of the challenging requirement in the design of the output stage is ower delivery to the load. ower consumption at the

More information

EE 501 Lab 4 Design of two stage op amp with miller compensation

EE 501 Lab 4 Design of two stage op amp with miller compensation EE 501 Lab 4 Design of two stage op amp with miller compensation Objectives: 1. Design a two stage op amp 2. Investigate how to miller compensate a two-stage operational amplifier. Tasks: 1. Build a two-stage

More information

ECE 546 Lecture 12 Integrated Circuits

ECE 546 Lecture 12 Integrated Circuits ECE 546 Lecture 12 Integrated Circuits Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine 1 Integrated Circuits IC Requirements

More information

LOW VOLTAGE ANALOG IC DESIGN PROJECT 1. CONSTANT Gm RAIL TO RAIL INPUT STAGE DESIGN. Prof. Dr. Ali ZEKĐ. Umut YILMAZER

LOW VOLTAGE ANALOG IC DESIGN PROJECT 1. CONSTANT Gm RAIL TO RAIL INPUT STAGE DESIGN. Prof. Dr. Ali ZEKĐ. Umut YILMAZER LOW VOLTAGE ANALOG IC DESIGN PROJECT 1 CONSTANT Gm RAIL TO RAIL INPUT STAGE DESIGN Prof. Dr. Ali ZEKĐ Umut YILMAZER 1 1. Introduction In this project, two constant Gm input stages are designed. First circuit

More information

Federal Urdu University of Arts, Science & Technology Islamabad Pakistan THIRD SEMESTER ELECTRONICS - II BASIC ELECTRICAL & ELECTRONICS LAB

Federal Urdu University of Arts, Science & Technology Islamabad Pakistan THIRD SEMESTER ELECTRONICS - II BASIC ELECTRICAL & ELECTRONICS LAB THIRD SEMESTER ELECTRONICS - II BASIC ELECTRICAL & ELECTRONICS LAB DEPARTMENT OF ELECTRICAL ENGINEERING Prepared By: Checked By: Approved By: Engr. Saqib Riaz Engr. M.Nasim Khan Dr.Noman Jafri Lecturer

More information

You will be asked to make the following statement and provide your signature on the top of your solutions.

You will be asked to make the following statement and provide your signature on the top of your solutions. 1 EE 435 Name Exam 1 Spring 216 Instructions: The points allocated to each problem are as indicated. Note that the first and last problem are weighted more heavily than the rest of the problems. On those

More information

Improving Amplifier Voltage Gain

Improving Amplifier Voltage Gain 15.1 Multistage ac-coupled Amplifiers 1077 TABLE 15.3 Three-Stage Amplifier Summary HAND ANALYSIS SPICE RESULTS Voltage gain 998 1010 Input signal range 92.7 V Input resistance 1 M 1M Output resistance

More information

Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design

Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design RESEARCH ARTICLE OPEN ACCESS Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design Ankush S. Patharkar*, Dr. Shirish M. Deshmukh** *(Department of Electronics and Telecommunication,

More information

Lab 2: Discrete BJT Op-Amps (Part I)

Lab 2: Discrete BJT Op-Amps (Part I) Lab 2: Discrete BJT Op-Amps (Part I) This is a three-week laboratory. You are required to write only one lab report for all parts of this experiment. 1.0. INTRODUCTION In this lab, we will introduce and

More information

EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design

EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design References: Analog Integrated Circuit Design by D. Johns and K. Martin and Design of Analog CMOS Integrated Circuits by B. Razavi All figures

More information

A low voltage rail-to-rail operational amplifier with constant operation and improved process robustness

A low voltage rail-to-rail operational amplifier with constant operation and improved process robustness Graduate Theses and Dissertations Graduate College 2009 A low voltage rail-to-rail operational amplifier with constant operation and improved process robustness Rien Lerone Beal Iowa State University Follow

More information

EE LINEAR INTEGRATED CIRCUITS & APPLICATIONS

EE LINEAR INTEGRATED CIRCUITS & APPLICATIONS UNITII CHARACTERISTICS OF OPAMP 1. What is an opamp? List its functions. The opamp is a multi terminal device, which internally is quite complex. It is a direct coupled high gain amplifier consisting of

More information

Basic distortion definitions

Basic distortion definitions Conclusions The push-pull second-generation current-conveyor realised with a complementary bipolar integration technology is probably the most appropriate choice as a building block for low-distortion

More information

Sensors & Transducers Published by IFSA Publishing, S. L.,

Sensors & Transducers Published by IFSA Publishing, S. L., Sensors & Transducers Published by IFSA Publishing, S. L., 208 http://www.sensorsportal.com Fully Differential Operation Amplifier Using Self Cascode MOSFET Structure for High Slew Rate Applications Kalpraj

More information

Basic OpAmp Design and Compensation. Chapter 6

Basic OpAmp Design and Compensation. Chapter 6 Basic OpAmp Design and Compensation Chapter 6 6.1 OpAmp applications Typical applications of OpAmps in analog integrated circuits: (a) Amplification and filtering (b) Biasing and regulation (c) Switched-capacitor

More information

Field Effect Transistors

Field Effect Transistors Field Effect Transistors Purpose In this experiment we introduce field effect transistors (FETs). We will measure the output characteristics of a FET, and then construct a common-source amplifier stage,

More information

I1 19u 5V R11 1MEG IDC Q7 Q2N3904 Q2N3904. Figure 3.1 A scaled down 741 op amp used in this lab

I1 19u 5V R11 1MEG IDC Q7 Q2N3904 Q2N3904. Figure 3.1 A scaled down 741 op amp used in this lab Lab 3: 74 Op amp Purpose: The purpose of this laboratory is to become familiar with a two stage operational amplifier (op amp). Students will analyze the circuit manually and compare the results with SPICE.

More information

ECE315 / ECE515 Lecture 9 Date:

ECE315 / ECE515 Lecture 9 Date: Lecture 9 Date: 03.09.2015 Biasing in MOS Amplifier Circuits Biasing using Single Power Supply The general form of a single-supply MOSFET amplifier biasing circuit is: We typically attempt to satisfy three

More information

Low-Voltage Current-Mode Analog Cells

Low-Voltage Current-Mode Analog Cells M.Tech. credit seminar report, Electronic Systems Group, EE Dept, IIT Bombay, submitted November 2002. Low-Voltage Current-Mode Analog Cells Mohit Kumar (02307026) Supervisor: Prof. T.S.Rathore Abstract

More information

ENEE307 Lab 7 MOS Transistors 2: Small Signal Amplifiers and Digital Circuits

ENEE307 Lab 7 MOS Transistors 2: Small Signal Amplifiers and Digital Circuits ENEE307 Lab 7 MOS Transistors 2: Small Signal Amplifiers and Digital Circuits In this lab, we will be looking at ac signals with MOSFET circuits and digital electronics. The experiments will be performed

More information