Chapter 15 Goals. ac-coupled Amplifiers Example of a Three-Stage Amplifier

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1 Chapter 15 Goals ac-coupled multistage amplifiers including voltage gain, input and output resistances, and small-signal limitations. dc-coupled multistage amplifiers. Darlington configuration and cascode amplifier. dc and ac properties of differential amplifiers. Class-A, Class-B, Class-AB output stages. Characteristics and design of electronic current sources. Chap 15-1 ac-coupled Amplifiers Example of a Three-Stage Amplifier Chap 15-1

2 ac-coupled Amplifiers Equivalent Circuits ac Equivalent Small-signal Equivalent dc Equivalent Chap 15-3 ac-coupled Amplifiers Input Resistance and Voltage Gain R L = R I R in3 = R I r π 3 +(β o3 +1)R L3 = 3.54 kω R I1 = 60Ω17.kΩ=598Ω R I = 4.7kΩ 51.8kΩ=4.31kΩ R L3 = 3.3kΩ 50Ω=3Ω R L1 = R I1 R in = 598Ω r π =598Ω 390Ω=478Ω A v1 = v v 1 = g m1 R L1 = 0.01S 478Ω=-4.78 A v = v 3 v = g m R L = 6.8mS 3.54kΩ=- A v3 = v o = (β +1)R o3 L3 = v 3 r π 3 +(β o3 +1)R L3 R in = R G =1 MΩ R in A v = A v3 A v A v1 =+998 R I +R in Chap 15-4

3 Coupling and Bypass Capacitor Design for C-E and C-S Amplifiers For the C-E amplifier, R in = R B R in CE R out = E 3 Rout For the C-S amplifier, R in = R G R in CS R out = S 3 Rout For coupling capacitor C 1, 1 C 1 >> ω R I +R in For coupling capacitor C 3, 1 C 3 >> ω R 7 +R out ω is chosen to be lowest frequency for which midband operation is needed in the given application. Chap 14-5 Coupling and Bypass Capacitor Design for C-E and C-S Amplifiers (cont.) In this case, we can neglect impedances of capacitors C 1 and C 3, the find the equivalent resistance looking up into emitter or source of amplifier. 1 C - E Stage : C >> ω R 6 R E + 1 C -S Stage : C >> 1 ω R 6 R S + 1 g m g m Chap

ac-coupled Amplifiers Output Resistance R th3 = v x = R I R i x CE out = R I r o = 4310Ω 5400Ω= 3990Ω To find output resistance, test voltage is applied at amplifier output.

4 ac-coupled Amplifiers Output Resistance R th3 = v x = R I R i x CE out = R I r o = 4310Ω 5400Ω= 3990Ω To find output resistance, test voltage is applied at amplifier output. i x =i r +i e = v x v x R out3 R out = v x = 3300 R i out3 = 3300 α o3 + R th3 x g m3 β o3 +1 = S Ω 81 =60.5Ω Chap 15-7 For first stage, For second stage, For third stage, ac-coupled Amplifiers Input Signal Range v 1 0.(V GS V TN ) v i 0.( 1+) =0.0V v be = v = A v1 v 1 5mV v 1 5mV = A v =1.05mV v 1.05mV =1.06 mv i v be3 v 3 1+g m3 R L3 = A v1 A v (0.990v s ) 1+g m3 R L3 On the whole, v be3 5mV v i 1+ g R m3 L V =9.7 μv A v1 A v (0.990) v i min(0mv,1.06mv,9.7μv )= 9.7 μv v o A v (9.7μV )=998(9.7μV )= 9.5 mv Chap

5 Common-Emitter Cascade To achieve maximum gain, several C-E stages can be cascaded. A v = v 1 v i v v 1... v o v n -1 = A vt3 A vt A vt1 For the final stage, A vtn = g mn R L 10V CC For all other stages, A vti = g mi (R Li r πi +1 ) If gain is limited by interstage resistances, each stage has a gain of about -10V CC and overall gain is: A vn = 10V CC If gain is limited by input resistance of transistors, it is given by: A vn = 1 n I C1 β o β o3...β on 10V I CC Cn Normally I Cn I C1 as signal and power levels usually increase in each successive stage of most amplifiers. Since β o < 10V CC, this case often represents the actual limit. n Chap 15-9 Direct-coupled Amplifiers Example of a Three-Stage Amplifier Coupling capacitors in series with signal path- C 1, C 3, C 5, and C 6 are eliminated as they prevent the amplifier from providing gain at dc or very low frequencies. Additional bias resistors in individual stages are also removed, making design less expensive. Bypass capacitors - C and C 4 affect gain at low frequencies but don t inherently prevent the amplifier from operating at dc. Symmetrical power supplies are used to set Q-point voltages at input and output to about zero. Alternating pnp or p-channel and npn or n-channel transistors are used from stage-to-stage to take maximum advantage of available power supply voltage. Chap

6 Voltage at drain of M 1 provides base bias for Q, and voltage at collector of Q provides base bias for Q 3. All transistors are designed to operate in active region irrespective of direct connection between stages. Direct-coupled Amplifiers dc Analysis I D = K n V GS V TN = ( I D + So, I D = ma (which would produce 10.7 V drop across R S1 and cut off FET) or I D = 5.9 ma (correct value). I B << I D, V D I D = 4. V V DS = = 3.6 V which is enough to pinch off M 1. I E = 7.5 V V D EB =1.84 ma 1400Ω β F = 150, so I C = 1.83 ma and I B = 1. μa. I B3 << I C, V C 4700 I C 7.5V =1.10 V V EC =V D1 +V EB V C = 3.8 V which < 0.7 V, so Q is in active region. Chap Direct-coupled Amplifiers dc Analysis (cont.) V O =V C V BE 3 =1.10V -0.7V = 0.4 V I E 3 = I 3 + I L = V + 7.5V O 3300Ω + V O = 3.99 ma 50Ω β F3 = 80, so I C3 =3.94 ma and I B3 = 49.3 μa V CE 3 = 7.5 V E 3 = V = 7.10 V the Q 3 is in the active region There is an offset voltage of 0.4 V at output, and a nonzero dc current exists in the 50 Ω load resistor. In an ideal design, offset voltage would be zero and no dc current would appear in load. Based on Q-point values, the small-signal parameters can be calculated. Chap

7 Direct-coupled Amplifiers ac Analysis Overall characteristics are similar to those in accoupled amplifier as Q- points and small-signal parameters of transistors are similar dc coupling requires fewer components than ac-coupling, but Q-points of various stages become interdependent. If Q-point of one stage shifts, Q-points of all other stages may also shift. Chap Direct-coupled Amplifiers Darlington Circuit ac Analysis: For the composite transistor, Darlington circuit behaves similar to the single transistor but has a current gain given by the product of current gains of individual transistors. DC Analysis: For β F1, β F >> 1, I C = I C1 + I C β F1 β F I B V BE of composite transistor = diode voltage drops. So V CE >(V BE1 + V BE ). r' π = y11 1 β o1 r π y 1 0 g m ' = y 1 g m r' o = y 1 3 r o β' y o = 1 β o1 β o y 11 v = 0 μ' f = v μ f v 1 3 i = 0 Chap

8 Direct-coupled Amplifiers Cascode Circuit ac Analysis: For the composite transistor, Cascode circuit is cascade connection of C-E and C-B amplifiers, used in high gain amplifiers and high output resistance current sources. DC Analysis: For a high current gain, I C = I C =α F I C1 I C1 For forward-active operation of Q, V CE1 =V BB V BE V BE1 V BB V BE r' π = y11 1 r π1 y 1 0 g' m = y 1 g m1 r' o = y 1 β o r o β' y o = 1 β o1 y 11 v = 0 μ' f = v β o μ f v 1 i = 0 Chap Differential Amplifiers Differential amplifiers, also considered the C-C/C-B cascade, eliminate the bypass capacitors as well as the external coupling capacitors at the input and output of direct-coupled Differential-mode output voltage is the voltage difference between collectors, drains of the two transistors. Ground referenced outputs can also be taken from collector/drain. Ideal differential amplifier uses Chap perfectly matched 8

9 Bipolar Differential Amplifiers dc Analysis Terminal currents are also equal. I C1 = I C = I C I E1 = I E = I E I B1 = I B = I B I E = V EE V BE R EE I C =α F I E I B = I C β F V C1 =V C =V CC I C V CE1 =V CE Both inputs are set to zero, emitters are connected together. V OD =V C1 V C = 0V V BE1 =V BE =V BE If transistors are matched, VC1 =VC =VC Chap v 1 = v ic + Bipolar Differential Amplifiers ac Analysis v = v ic Circuit analysis is done by superposition of differential-mode and common-mode signal portions. v od = v c1 v c v od v oc = A A dd cd A dc v oc = v + v c1 c v id A v cc ic A dd = differential-mode gain A cd = common-mode to differential-mode conversion gain A cc = common-mode gain A dc = differential mode to common-mode conversion gain For ideal symmetrical amplifier, A cd = A dc = 0. v od = A dd v oc 0 A v cc ic Purely differential-mode input gives purely differential-mode output and vice versa. 0 v id Chap

10 Bipolar Differential Amplifier Differential-mode Gain and Input Resistance v 3 = v v = e 4 v e (g m +g π )(v 3 +v 4 )=G EE v e v e (G EE +g π +g m )=0 v e =0 Emitter node in differential amplifier represents virtual ground for differential-mode input signals. v 3 = v 4 = Output signal voltages are: v c1 = g m v c =+g m v od = g m Chap Bipolar Differential Amplifiers: Differentialmode Gain and Input Resistance (cont.) Differential-mode gain for a balanced output, v od = v c1 -v c, is: A dd = v od = g m v = 0 ic If either v c1 or v c is used alone as output, output is said to be single-ended. A dd1 = v c1 = g R m C = A dd v = 0 ic A dd = v c = g R m C = A dd v = 0 ic Differential-mode input resistance is small-signal resistance presented to differential-mode input voltage between the two transistor bases. i b1 =( /)/r π R id = /i b1 = r π If = 0, R od = ( r o ). For single-ended outputs, R od Chap

11 Bipolar Differential Amplifiers: Commonmode Gain and Input Resistance Both arms of differential amplifier are symmetrical. So terminal currents and collector voltages are equal. Characteristics of differential pair with commonmode input are similar to those of a C-E (or C-S) amplifier with large emitter (or source) resistor. v ic i b = r π +(β o +1)R EE Output voltages are: β v c1 =v c = β o i b = o v ic r π +(β o +1)R EE v e = (β o +1)i b R EE v e = (β +1)R o EE v ic v ic r π +(β o +1)R EE Chap 15-1 Bipolar Differential Amplifiers: Commonmode Gain and Input Resistance (cont.) Common-mode gain is given by: A cc = v β oc = o V C v ic r v = 0 π +(β o +1)R EE R EE V EE id For symmetrical power supplies, common-mode gain = 0.5. Thus, commonmode output voltage and A cc is 0 if R EE is infinite. This result is obtained since output resistances of transistors are neglected. A more accurate expression is: 1 A cc 1 β o r o R EE v od = v c1 v c =0 Therefore, common-mode conversion gain is found to be 0. R ic = v ic = r +(β +1)R π o EE = r π i b +(β +1)R o EE Chap 15-11

12 Common-Mode Rejection ratio (CMRR) Represents ability of amplifier to amplify desired differentialmode input signal and reject undesired common-mode input signal. For differential output, common-mode gain of balanced amplifier is zero, CMRR is infinite. For single-ended output, CMRR = A dm = A dd / = 1 A cm A cc β 1 1 o μ f g m R EE CMRR g m R EE = 40I C R EE 0V EE For infinite R EE, CMRR is limited by β o μ f. If term containing R EE is dominant Thus for differential pair biased by resistor R EE, CMRR is limited by available negative power supply. Chap 15-3 Analysis of Differential Amplifiers Using Half- Circuits Half-circuits are constructed by first drawing the differential amplifier in a fully symmetrical form Power supplies are split into two equal halves in parallel Bias resistor R EE is separated into two equal resistors in parallel. None of the currents or voltages in the circuit are changed. For differential mode signals, points on the line of symmetry Chap 15-4 are virtual grounds for ac 1

13 Bipolar Differential-mode Half-circuits Direct analysis of the half-circuits yields: v c1 = g m v c =+g m Applying rules for drawing halfcircuits, the two power supply lines and emitter become ac grounds. The half-circuit represents a C-E amplifier stage. v o = v c1 v c = g m R id = /i b1 = r π R od = ( r o ) Chap 15-5 Bipolar Common-mode Half-circuits All points on line of symmetry become open circuits. DC circuit with V IC set to zero is used to find amplifier s Q-point. Last circuit is used for for common-mode signal Chap

14 Bipolar Common-mode Input Voltage Range V CB =V CC I C V IC 0 I C α F V IC V BE +V EE R EE V IC V CC 1 α F R EE V V EE BE V CC 1+α F R EE For symmetrical power supplies, V EE >> V BE, and = R EE, V IC V CC 3 Chap 15-7 Biasing with Electronic Current Sources Differential amplifiers are biased using electronic current sources to stabilize the operating point and increase effective value of R EE to improve CMRR Electronic current source has a Q- point current of I SS and an output resistance of R SS as shown. I DC = I SS V O DC model of the electronic current R SS source is a dc current source, I SS while ac model is a resistance R SS. SPICE model Chap

15 MOSFET Differential Amplifiers: DC Analysis I D = K n V GS V TN Op amps with MOSFET inputs have a high input resistance and much higher slew rate that those with bipolar input stages. Using half-circuit analysis, we see that I S = I SS /. V GS =V TN + I D K n =V TN + I SS K n V D1 =V D =V DD I D R D and V OD = 0 V DS =V D V S =V DD I D R D +V GS Chap 15-9 Small-Signal Transfer Characteristic MOS differential amplifier gives improved linear input signal range and distortion characteristics over that of a single transistor. ( ) ( v GS V TN ) i D1 i D = K n v GS1 V TN For symmetrical differential amplifier with purely differential-mode input v GS1 =V GS + v GS =V GS i D1 i D = K n V GS V TN v id = g m Second-order distortion product is eliminated and distortion is greatly reduced. However some distortion prevails as MOSFETs are not perfect square-law devices and some distortion arises through voltage dependence of output impedances of the transistors. Chap

16 MOSFET Differential Amplifiers DC Analysis (Example) Problem: Find Q-points of transistors in the differential amplifier. Given data: V DD = V SS = 1 V, I SS = 00 μa, R SS = 500 kω, R D = 6 kω, λ = I V -1, K n = 5 ma/ V D = I SS =100 μa, V TN = 1V Analysis: 00μA V GS =1+ 5mA/V =1.0 V V DS =1V -(100μA)(6kΩ)+1.V = 7 V To maintain pinch-off operation of M 1 for nonzero V IC, V GD =V IC -V DD -I D R D V TN V IC V DD -I D R D +V TN = 6.8 V Chap MOSFET Differential Amplifiers Differential-mode Input Signals Source node in differential amplifier represents a virtual ground. Differential-mode gain for balanced output is A dd = v od = g m R D v = 0 ic Gain for single-ended output is v d1 = g m R D v d =+g m R D A dd1 = v d1 = g R m D = A dd v = 0 ic A dd = v d =+ g m R D = A dd v = 0 ic v od = g m R D R id = R od = R D Chap

17 MOSFET Differential Amplifiers: Commonmode Input Signals Electronic current source is modeled by twice its smallsignal output resistance representing output resistance of the current source. Common-mode half-circuit is similar to inverting amplifier with R SS as source resistor. v d1 =v d = g R m D v ic v s = g R m SS v ic v ic 1+g m R SS 1+g m R SS v od = v d1 v d =0 Thus, common-mode conversion gain = 0 A cc = v oc = g R m D R D R v ic 1+g v = 0 m R SS R ic = R oc = R D SS id Chap Common-Mode Rejection Ratio (CMRR) For purely common-mode input signal, output of balanced MOS amplifier is zero. CMRR is infinite. For a single-ended output, CMRR= A dm = A dd/ = (g R )/ m D A cm A cc R D /(R SS ) = g R m SS R SS (which is much > R EE and thus provides more Q-point stability) should be maximized. R SS = V V SS GS CMRR= I R D SS = I R SS SS = (V V ) SS GS To compare MOS I SS amplifier directly V GS V TN to BJT V GS Vamplifier, TN V GS TN assume that MOS amplifier is biased by Chap From given data in example MOS amplifier s CMRR = 54 or 17

18 Two-port model for Differential Amplifiers i dm = g m v dm g i cm = m v cm v cm 1+g m R EE R EE R od = r o R oc μ f R EE Two-port model simplifies circuit analysis of differential amplifiers. Expressions for FET are obtained by substituting R SS for R EE. Chap

Improving Amplifier Voltage Gain

Improving Amplifier Voltage Gain 15.1 Multistage ac-coupled Amplifiers 1077 TABLE 15.3 Three-Stage Amplifier Summary HAND ANALYSIS SPICE RESULTS Voltage gain 998 1010 Input signal range 92.7 V Input resistance 1 M 1M Output resistance